[llvm] [RISCV] Add BREV8 to isSignExtendedW in RISCVOptWInstrs. (PR #141893)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/141893

If the input to a BREV8 has 33 sign bits, the result does too. BREV8 reverses the bits in each byte. If bits 63:32 are all the same, reversing the bits in each of those 4 bytes still keeps them the same.

>From 73b11e2964de48e6b334e97a5985a3182b45b583 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 28 May 2025 21:07:46 -0700
Subject: [PATCH] [RISCV] Add BREV8 to isSignExtendedW in RISCVOptWInstrs.

If the input to a BREV8 has 33 sign bits, the result does too. BREV8
reverses the bits in each byte. If bits 63:32 are all the same,
reversing the bits in each of those 4 bytes doesn't change that.
---
 llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp     | 1 +
 llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index 3b601bb43bf28..e4fd5a88d4d8a 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -503,6 +503,7 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
         return false;
       [[fallthrough]];
     case RISCV::REM:
+    case RISCV::BREV8:
     case RISCV::ANDI:
     case RISCV::ORI:
     case RISCV::XORI:
diff --git a/llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll
index 3169f65f64671..0ed57d859becf 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll
@@ -42,7 +42,6 @@ define signext i32 @brev8_i32(i32 signext %a) nounwind {
 ; RV64ZBKB-LABEL: brev8_i32:
 ; RV64ZBKB:       # %bb.0:
 ; RV64ZBKB-NEXT:    brev8 a0, a0
-; RV64ZBKB-NEXT:    sext.w a0, a0
 ; RV64ZBKB-NEXT:    ret
   %val = call i32 @llvm.riscv.brev8.i32(i32 %a)
   ret i32 %val