[llvm] [LoongArch] Allow difference across sections (PR #141722)

[Jinyang He via llvm-commits]

================
@@ -447,19 +447,16 @@ bool LoongArchAsmBackend::addReloc(const MCFragment &F, const MCFixup &Fixup,
     if (!force) {
----------------
MQ-mengqing wrote:

Because later it calls SA.getSection() and SB.getSection(). I want to handle the other cases by these section info.
E.g. for case (SecB == SecCur and SecA != SecCur), use Fallback() to emit PCRel.
For `llvm/test/MC/LoongArch/Relocations/sub-expr.s`,
LoongArch emits,
```
0000000000000000  000000010000006d R_LARCH_64_PCREL       0000000000000004 x + 0
0000000000000008  000000020000006d R_LARCH_64_PCREL       0000000000000004 y + 0
0000000000000010  0000000100000063 R_LARCH_32_PCREL       0000000000000004 x + 0
0000000000000014  0000000200000063 R_LARCH_32_PCREL       0000000000000004 y + 0
...
```
RISCV emits,
```
0000000000000000  0000000200000024 R_RISCV_ADD64          0000000000000004 x + 0
0000000000000000  0000000300000028 R_RISCV_SUB64          0000000000000000 .L0  + 0
0000000000000008  0000000600000024 R_RISCV_ADD64          0000000000000004 y + 0
0000000000000008  0000000500000028 R_RISCV_SUB64          0000000000000008 .L0  + 0
0000000000000010  0000000200000023 R_RISCV_ADD32          0000000000000004 x + 0
0000000000000010  0000000700000027 R_RISCV_SUB32          0000000000000010 .L0  + 0
0000000000000014  0000000600000023 R_RISCV_ADD32          0000000000000004 y + 0
0000000000000014  0000000800000027 R_RISCV_SUB32          0000000000000014 .L0  + 0
...
```

https://github.com/llvm/llvm-project/pull/141722