[llvm] AMDGPU: Custom lower fptrunc vectors for f32 -> f16 (PR #141883)
Shilei Tian via llvm-commits
llvm-commits at lists.llvm.org
Wed May 28 19:21:24 PDT 2025
================
@@ -2749,6 +2752,20 @@ bool AMDGPULegalizerInfo::legalizeMinNumMaxNum(LegalizerHelper &Helper,
return Helper.lowerFMinNumMaxNum(MI) == LegalizerHelper::Legalized;
}
+bool AMDGPULegalizerInfo::legalizeFPTrunc(LegalizerHelper &Helper,
+ MachineInstr &MI,
+ MachineRegisterInfo &MRI) const {
+ Register DstReg = MI.getOperand(0).getReg();
+ LLT DstTy = MRI.getType(DstReg);
+ assert (DstTy.isVector() && DstTy.getNumElements() > 2);
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shiltian wrote:
I think the format is off here
https://github.com/llvm/llvm-project/pull/141883
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