[llvm] [RISCV] Add X0_Pair to RISCVDeadRegisterDefinitions. (PR #141831)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/141831

None

>From 4e6cbbaca94b728646f876133013e1b9a137e17f Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 28 May 2025 12:29:42 -0700
Subject: [PATCH] [RISCV] Add X0_Pair to RISCVDeadRegisterDefinitions.

---
 llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp | 2 ++
 llvm/test/CodeGen/RISCV/double-mem.ll                  | 4 ++--
 llvm/test/CodeGen/RISCV/zilsd.ll                       | 2 +-
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp b/llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
index 47510ec6b0ea8..2f4bdb7b64f4e 100644
--- a/llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+++ b/llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
@@ -99,6 +99,8 @@ bool RISCVDeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
           X0Reg = RISCV::X0_W;
         } else if (RC && RC->contains(RISCV::X0_H)) {
           X0Reg = RISCV::X0_H;
+        } else if (RC && RC->contains(RISCV::X0_Pair)) {
+          X0Reg = RISCV::X0_Pair;
         } else {
           LLVM_DEBUG(dbgs() << "    Ignoring, register is not a GPR.\n");
           continue;
diff --git a/llvm/test/CodeGen/RISCV/double-mem.ll b/llvm/test/CodeGen/RISCV/double-mem.ll
index 0210e0252deca..81ef194da8b47 100644
--- a/llvm/test/CodeGen/RISCV/double-mem.ll
+++ b/llvm/test/CodeGen/RISCV/double-mem.ll
@@ -141,10 +141,10 @@ define dso_local double @fld_fsd_global(double %a, double %b) nounwind {
 ; RV32IZFINXZDINXZILSD:       # %bb.0:
 ; RV32IZFINXZDINXZILSD-NEXT:    lui a4, %hi(G)
 ; RV32IZFINXZDINXZILSD-NEXT:    fadd.d a0, a0, a2
-; RV32IZFINXZDINXZILSD-NEXT:    ld a2, %lo(G)(a4)
+; RV32IZFINXZDINXZILSD-NEXT:    ld zero, %lo(G)(a4)
 ; RV32IZFINXZDINXZILSD-NEXT:    addi a2, a4, %lo(G)
 ; RV32IZFINXZDINXZILSD-NEXT:    sd a0, %lo(G)(a4)
-; RV32IZFINXZDINXZILSD-NEXT:    ld a4, 72(a2)
+; RV32IZFINXZDINXZILSD-NEXT:    ld zero, 72(a2)
 ; RV32IZFINXZDINXZILSD-NEXT:    sd a0, 72(a2)
 ; RV32IZFINXZDINXZILSD-NEXT:    ret
 ; Use %a and %b in an FP op to ensure floating point registers are used, even
diff --git a/llvm/test/CodeGen/RISCV/zilsd.ll b/llvm/test/CodeGen/RISCV/zilsd.ll
index 3eaaffba250dd..bc2f7d486f16b 100644
--- a/llvm/test/CodeGen/RISCV/zilsd.ll
+++ b/llvm/test/CodeGen/RISCV/zilsd.ll
@@ -8,7 +8,7 @@ define i64 @load(ptr %a) nounwind {
 ; CHECK-LABEL: load:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ld a2, 80(a0)
-; CHECK-NEXT:    ld a0, 0(a0)
+; CHECK-NEXT:    ld zero, 0(a0)
 ; CHECK-NEXT:    mv a0, a2
 ; CHECK-NEXT:    mv a1, a3
 ; CHECK-NEXT:    ret