[llvm] AMDGPU: Add is_fpclass to isBoolSGPR (PR #141801)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/141801

>From 31f69ea76918b538a1cebf6da2f36d6661ec3a96 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Wed, 28 May 2025 17:55:38 +0200
Subject: [PATCH] AMDGPU: Add is_fpclass to isBoolSGPR

---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp     |  1 +
 .../CodeGen/AMDGPU/combine-and-sext-bool.ll   | 25 +++++++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index b19fa4b47f91f..70205195891e1 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -11901,6 +11901,7 @@ bool llvm::isBoolSGPR(SDValue V) {
   default:
     break;
   case ISD::SETCC:
+  case ISD::IS_FPCLASS:
   case AMDGPUISD::FP_CLASS:
     return true;
   case ISD::AND:
diff --git a/llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll b/llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll
index b763bec89eef3..bdad6f40480d3 100644
--- a/llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll
+++ b/llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll
@@ -20,6 +20,31 @@ bb:
   ret void
 }
 
+; GCN-LABEL: {{^}}and_sext_bool_fcmp:
+; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GCN-NEXT: s_setpc_b64
+define i32 @and_sext_bool_fcmp(float %x, i32 %y) {
+  %cmp = fcmp oeq float %x, 0.0
+  %sext = sext i1 %cmp to i32
+  %and = and i32 %sext, %y
+  ret i32 %and
+}
+
+; GCN-LABEL: {{^}}and_sext_bool_fpclass:
+; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 [[K:v[0-9]+]], 0x7b
+; GCN-NEXT: v_cmp_class_f32_e32 vcc, v0, [[K]]
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GCN-NEXT: s_setpc_b64
+define i32 @and_sext_bool_fpclass(float %x, i32 %y) {
+  %class = call i1 @llvm.is.fpclass(float %x, i32 123)
+  %sext = sext i1 %class to i32
+  %and = and i32 %sext, %y
+  ret i32 %and
+}
+
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 
 declare i32 @llvm.amdgcn.workitem.id.y() #0