[llvm] [AMDGPU] Extend SRA i64 simplification for shift amts in range [33:62] (PR #138913)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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You can test this locally with the following command:
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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
``````````

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<details>
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index a3e87d3f0..a5fc9cad9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -4173,7 +4173,7 @@ SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
     SDValue HiShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
                                   DAG.getConstant(31, SL, MVT::i32));
     SDValue LoShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
-				  DAG.getConstant(RHSVal - 32, SL, MVT::i32));
+                                  DAG.getConstant(RHSVal - 32, SL, MVT::i32));
 
     SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {LoShift, HiShift});
     return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);

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https://github.com/llvm/llvm-project/pull/138913