[llvm] [PowerPC10][XXEVAL] Exploit xxeval instruction for cases of the ternary(A,X, and(B,C)), ternary(A,X,B), ternary(A,X,C), ternary(A,X,xor(B,C)) forms. (PR #141733)
Tony Varghese via llvm-commits
llvm-commits at lists.llvm.org
Wed May 28 10:44:12 PDT 2025
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https://github.com/tonykuttai updated https://github.com/llvm/llvm-project/pull/141733
>From 46eeffca9c0a51f724eb6f859a8ff9778686619e Mon Sep 17 00:00:00 2001
From: Tony Varghese <tony.varghese at ibm.com>
Date: Tue, 27 May 2025 13:36:08 +0000
Subject: [PATCH 1/8] [NFC] Add testcases for locking down the xxeval
instruction support for ternary operators
---
.../CodeGen/PowerPC/xxeval-vselect-x-and.ll | 188 ++++++++++++++++++
.../CodeGen/PowerPC/xxeval-vselect-x-b.ll | 169 ++++++++++++++++
.../CodeGen/PowerPC/xxeval-vselect-x-c.ll | 138 +++++++++++++
.../CodeGen/PowerPC/xxeval-vselect-x-xor.ll | 177 +++++++++++++++++
4 files changed, 672 insertions(+)
create mode 100644 llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
create mode 100644 llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
create mode 100644 llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
create mode 100644 llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
new file mode 100644
index 0000000000000..05fb6534bebcd
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
@@ -0,0 +1,188 @@
+; Test file to verify the emission of Vector selection instructions when ternary operators are used.
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; Function to test ternary(A, xor(B, C), and(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_xor_BC_and_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_xor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <4 x i32> %B, %C
+ %and = and <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %xor, <4 x i32> %and
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, xor(B, C), and(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_xor_BC_and_BC_2x64
+; CHECK: xxlxor vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_xor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <2 x i64> %B, %C
+ %and = and <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %xor, <2 x i64> %and
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, nor(B, C), and(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_nor_BC_and_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_nor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <4 x i32> %B, %C
+ %nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector NOR operation
+ %and = and <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %nor, <4 x i32> %and
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, nor(B, C), and(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_nor_BC_and_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_nor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <2 x i64> %B, %C
+ %nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; Vector NOR operation
+ %and = and <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %nor, <2 x i64> %and
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, eqv(B, C), and(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_eqv_BC_and_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_eqv_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <4 x i32> %B, %C
+ %eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
+ %and = and <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %eqv, <4 x i32> %and
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, eqv(B, C), and(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_eqv_BC_and_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_eqv_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <2 x i64> %B, %C
+ %eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
+ %and = and <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %eqv, <2 x i64> %and
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, not(C), and(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_not_C_and_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_not_C_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %not = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
+ %and = and <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %and
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, not(C), and(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_not_C_and_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_not_C_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
+ %and = and <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %and
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, not(B), and(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_not_B_and_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v3
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_not_B_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %not = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
+ %and = and <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %and
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, not(B), and(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_not_B_and_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v3
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_not_B_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %not = xor <2 x i64> %B, <i64 -1, i64 -1> ; Vector not operation
+ %and = and <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %and
+ ret <2 x i64> %res
+}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
new file mode 100644
index 0000000000000..3966c69636986
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
@@ -0,0 +1,169 @@
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; Function to test ternary(A, and(B, C), B) for <4 x i32>
+; CHECK-LABEL: ternary_A_and_BC_B_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_and_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %and, <4 x i32> %B
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, and(B, C), B) for <2 x i64>
+; CHECK-LABEL: ternary_A_and_BC_B_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_and_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %and, <2 x i64> %B
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, nor(B, C), B) for <4 x i32>
+; CHECK-LABEL: ternary_A_nor_BC_B_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_nor_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <4 x i32> %B, %C
+ %nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector NOR operation
+ %res = select <4 x i1> %A, <4 x i32> %nor, <4 x i32> %B
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, nor(B, C), B) for <2 x i64>
+; CHECK-LABEL: ternary_A_nor_BC_B_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_nor_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <2 x i64> %B, %C
+ %nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; Vector NOR operation
+ %res = select <2 x i1> %A, <2 x i64> %nor, <2 x i64> %B
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, eqv(B, C), B) for <4 x i32>
+; CHECK-LABEL: ternary_A_eqv_BC_B_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_eqv_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <4 x i32> %B, %C
+ %eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
+ %res = select <4 x i1> %A, <4 x i32> %eqv, <4 x i32> %B
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, eqv(B, C), B) for <2 x i64>
+; CHECK-LABEL: ternary_A_eqv_BC_B_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_eqv_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <2 x i64> %B, %C
+ %eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
+ %res = select <2 x i1> %A, <2 x i64> %eqv, <2 x i64> %B
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, not(C), B) for <4 x i32>
+; CHECK-LABEL: ternary_A_not_C_B_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_not_C_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %not = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
+ %res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %B
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, not(C), B) for <2 x i64>
+; CHECK-LABEL: ternary_A_not_C_B_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_not_C_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
+ %res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %B
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, nand(B, C), B) for <4 x i32>
+; CHECK-LABEL: ternary_A_nand_BC_B_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_nand_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <4 x i32> %B, %C
+ %nand = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector nand operation
+ %res = select <4 x i1> %A, <4 x i32> %nand, <4 x i32> %B
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, nand(B, C), B) for <2 x i64>
+; CHECK-LABEL: ternary_A_nand_BC_B_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_nand_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <2 x i64> %B, %C
+ %nand = xor <2 x i64> %and, <i64 -1, i64 -1> ; Vector nand operation
+ %res = select <2 x i1> %A, <2 x i64> %nand, <2 x i64> %B
+ ret <2 x i64> %res
+}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
new file mode 100644
index 0000000000000..76ff1b2f2f683
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
@@ -0,0 +1,138 @@
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; Function to test ternary(A, and(B, C), C) for <4 x i32>
+; CHECK-LABEL: ternary_A_and_BC_C_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_and_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %and, <4 x i32> %C
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, and(B, C), C) for <2 x i64>
+; CHECK-LABEL: ternary_A_and_BC_C_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_and_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %and, <2 x i64> %C
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, nor(B, C), C) for <4 x i32>
+; CHECK-LABEL: ternary_A_nor_BC_C_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_nor_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <4 x i32> %B, %C
+ %nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector NOR operation
+ %res = select <4 x i1> %A, <4 x i32> %nor, <4 x i32> %C
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, nor(B, C), C) for <2 x i64>
+; CHECK-LABEL: ternary_A_nor_BC_C_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_nor_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <2 x i64> %B, %C
+ %nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; Vector NOR operation
+ %res = select <2 x i1> %A, <2 x i64> %nor, <2 x i64> %C
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, eqv(B, C), C) for <4 x i32>
+; CHECK-LABEL: ternary_A_eqv_BC_C_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_eqv_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <4 x i32> %B, %C
+ %eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
+ %res = select <4 x i1> %A, <4 x i32> %eqv, <4 x i32> %C
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, eqv(B, C), C) for <2 x i64>
+; CHECK-LABEL: ternary_A_eqv_BC_C_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_eqv_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <2 x i64> %B, %C
+ %eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
+ %res = select <2 x i1> %A, <2 x i64> %eqv, <2 x i64> %C
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, nand(B, C), C) for <4 x i32>
+; CHECK-LABEL: ternary_A_nand_BC_C_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_nand_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <4 x i32> %B, %C
+ %nand = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector nand operation
+ %res = select <4 x i1> %A, <4 x i32> %nand, <4 x i32> %C
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, nand(B, C), C) for <2 x i64>
+; CHECK-LABEL: ternary_A_nand_BC_C_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_nand_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <2 x i64> %B, %C
+ %nand = xor <2 x i64> %and, <i64 -1, i64 -1> ; Vector nand operation
+ %res = select <2 x i1> %A, <2 x i64> %nand, <2 x i64> %C
+ ret <2 x i64> %res
+}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
new file mode 100644
index 0000000000000..0a919bc982c85
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
@@ -0,0 +1,177 @@
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+; Function to test ternary(A, and(B, C), xor(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_and_BC_xor_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_and_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <4 x i32> %B, %C
+ %xor = xor <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %and, <4 x i32> %xor
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, and(B, C), xor(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_and_BC_xor_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_and_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %and = and <2 x i64> %B, %C
+ %xor = xor <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %and, <2 x i64> %xor
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, B, xor(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_B_xor_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_B_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %B, <4 x i32> %xor
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, B, xor(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_B_xor_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_B_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %B, <2 x i64> %xor
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, C, xor(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_C_xor_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_C_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %C, <4 x i32> %xor
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, C, xor(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_C_xor_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_C_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %xor = xor <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %C, <2 x i64> %xor
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, or(B, C), xor(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_or_BC_xor_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlor vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_or_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <4 x i32> %B, %C
+ %xor = xor <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %or, <4 x i32> %xor
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, or(B, C), xor(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_or_BC_xor_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlor vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_or_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <2 x i64> %B, %C
+ %xor = xor <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %or, <2 x i64> %xor
+ ret <2 x i64> %res
+}
+
+; Function to test ternary(A, nor(B, C), xor(B, C)) for <4 x i32>
+; CHECK-LABEL: ternary_A_nor_BC_xor_BC_4x32
+; CHECK: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <4 x i32> @ternary_A_nor_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <4 x i32> %B, %C
+ %nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; vector nor operation
+ %xor = xor <4 x i32> %B, %C
+ %res = select <4 x i1> %A, <4 x i32> %nor, <4 x i32> %xor
+ ret <4 x i32> %res
+}
+
+; Function to test ternary(A, nor(B, C), xor(B, C)) for <2 x i64>
+; CHECK-LABEL: ternary_A_nor_BC_xor_BC_2x64
+; CHECK: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
+define dso_local <2 x i64> @ternary_A_nor_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+entry:
+ %or = or <2 x i64> %B, %C
+ %nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; vector nor operation
+ %xor = xor <2 x i64> %B, %C
+ %res = select <2 x i1> %A, <2 x i64> %nor, <2 x i64> %xor
+ ret <2 x i64> %res
+}
>From f4010619d6a75ebc62b49d1081bfb007c6636610 Mon Sep 17 00:00:00 2001
From: Tony Varghese <tony.varghese at ibm.com>
Date: Wed, 28 May 2025 04:58:44 +0000
Subject: [PATCH 2/8] Removed the xxspltiw instructions from the check
---
llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll | 15 +++++----------
llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll | 15 +++++----------
llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll | 12 ++++--------
llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll | 15 +++++----------
4 files changed, 19 insertions(+), 38 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
index 05fb6534bebcd..e65e41adb0df7 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
@@ -11,8 +11,7 @@
; Function to test ternary(A, xor(B, C), and(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_xor_BC_and_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK: xxlxor vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -45,8 +44,7 @@ entry:
; Function to test ternary(A, nor(B, C), and(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_nor_BC_and_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK: xxlnor vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -82,8 +80,7 @@ entry:
; Function to test ternary(A, eqv(B, C), and(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_eqv_BC_and_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK: xxleqv vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -119,8 +116,7 @@ entry:
; Function to test ternary(A, not(C), and(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_not_C_and_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK: xxlnor vs0, v4, v4
; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -154,8 +150,7 @@ entry:
; Function to test ternary(A, not(B), and(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_not_B_and_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v3, v3
+; CHECK: xxlnor vs0, v3, v3
; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
index 3966c69636986..8ae82d7c6a275 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
@@ -9,8 +9,7 @@
; Function to test ternary(A, and(B, C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_and_BC_B_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK: xxland vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v3, vs0, v2
@@ -40,8 +39,7 @@ entry:
; Function to test ternary(A, nor(B, C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_nor_BC_B_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK: xxlnor vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v3, vs0, v2
@@ -73,8 +71,7 @@ entry:
; Function to test ternary(A, eqv(B, C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_eqv_BC_B_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK: xxleqv vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v3, vs0, v2
@@ -106,8 +103,7 @@ entry:
; Function to test ternary(A, not(C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_not_C_B_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK: xxlnor vs0, v4, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v3, vs0, v2
@@ -137,8 +133,7 @@ entry:
; Function to test ternary(A, nand(B, C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_nand_BC_B_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK: xxlnand vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v3, vs0, v2
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
index 76ff1b2f2f683..a53c0b845732b 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
@@ -9,8 +9,7 @@
; Function to test ternary(A, and(B, C), C) for <4 x i32>
; CHECK-LABEL: ternary_A_and_BC_C_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK: xxland vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v4, vs0, v2
@@ -40,8 +39,7 @@ entry:
; Function to test ternary(A, nor(B, C), C) for <4 x i32>
; CHECK-LABEL: ternary_A_nor_BC_C_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK: xxlnor vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v4, vs0, v2
@@ -73,8 +71,7 @@ entry:
; Function to test ternary(A, eqv(B, C), C) for <4 x i32>
; CHECK-LABEL: ternary_A_eqv_BC_C_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK: xxleqv vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v4, vs0, v2
@@ -106,8 +103,7 @@ entry:
; Function to test ternary(A, nand(B, C), C) for <4 x i32>
; CHECK-LABEL: ternary_A_nand_BC_C_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK: xxlnand vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, v4, vs0, v2
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
index 0a919bc982c85..25b6fd6e4c540 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
@@ -9,8 +9,7 @@
; Function to test ternary(A, and(B, C), xor(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_and_BC_xor_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK: xxland vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -44,8 +43,7 @@ entry:
; Function to test ternary(A, B, xor(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_B_xor_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK: xxlxor vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, vs0, v3, v2
@@ -75,8 +73,7 @@ entry:
; Function to test ternary(A, C, xor(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_C_xor_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK: xxlxor vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
; CHECK-NEXT: xxsel v2, vs0, v4, v2
@@ -106,8 +103,7 @@ entry:
; Function to test ternary(A, or(B, C), xor(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_or_BC_xor_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlor vs0, v3, v4
+; CHECK: xxlor vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
@@ -141,8 +137,7 @@ entry:
; Function to test ternary(A, nor(B, C), xor(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_nor_BC_xor_BC_4x32
-; CHECK: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK: xxlnor vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
>From 2b8924ad169b9eefce9ff20c2dbf5a7ff6543d45 Mon Sep 17 00:00:00 2001
From: Tony Varghese <tony.varghese at ibm.com>
Date: Wed, 28 May 2025 06:09:34 +0000
Subject: [PATCH 3/8] Add test summary
---
llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll | 2 ++
llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll | 2 ++
llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll | 2 ++
3 files changed, 6 insertions(+)
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
index 8ae82d7c6a275..a04c2500ea91a 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
@@ -1,3 +1,5 @@
+; Test file to verify the emission of Vector selection instructions when ternary operators are used.
+
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
index a53c0b845732b..5b5b5eaeb50cf 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
@@ -1,3 +1,5 @@
+; Test file to verify the emission of Vector selection instructions when ternary operators are used.
+
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
index 25b6fd6e4c540..dcdf463b924e1 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
@@ -1,3 +1,5 @@
+; Test file to verify the emission of Vector selection instructions when ternary operators are used.
+
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
>From 5db66cfbf282042135ffc06c3da93865c8783526 Mon Sep 17 00:00:00 2001
From: Tony Varghese <tony.varghese at ibm.com>
Date: Wed, 28 May 2025 09:02:10 +0000
Subject: [PATCH 4/8] Modified test files to capture only the essential
instructions
---
.../CodeGen/PowerPC/xxeval-vselect-x-and.ll | 57 +++++-------------
.../CodeGen/PowerPC/xxeval-vselect-x-b.ll | 60 +++++--------------
.../CodeGen/PowerPC/xxeval-vselect-x-c.ll | 48 ++++-----------
.../CodeGen/PowerPC/xxeval-vselect-x-xor.ll | 60 +++++--------------
4 files changed, 56 insertions(+), 169 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
index e65e41adb0df7..7187d3bf30f0e 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
@@ -13,9 +13,7 @@
; CHECK-LABEL: ternary_A_xor_BC_and_BC_4x32
; CHECK: xxlxor vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_xor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -29,10 +27,7 @@ entry:
; CHECK-LABEL: ternary_A_xor_BC_and_BC_2x64
; CHECK: xxlxor vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_xor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -46,9 +41,7 @@ entry:
; CHECK-LABEL: ternary_A_nor_BC_and_BC_4x32
; CHECK: xxlnor vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -61,13 +54,9 @@ entry:
; Function to test ternary(A, nor(B, C), and(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_nor_BC_and_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK: xxlnor vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -82,9 +71,7 @@ entry:
; CHECK-LABEL: ternary_A_eqv_BC_and_BC_4x32
; CHECK: xxleqv vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_eqv_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -97,13 +84,9 @@ entry:
; Function to test ternary(A, eqv(B, C), and(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_eqv_BC_and_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK: xxleqv vs0, v3, v4
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_eqv_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -118,9 +101,7 @@ entry:
; CHECK-LABEL: ternary_A_not_C_and_BC_4x32
; CHECK: xxlnor vs0, v4, v4
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_not_C_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -132,13 +113,9 @@ entry:
; Function to test ternary(A, not(C), and(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_not_C_and_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK: xxlnor vs0, v4, v4
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_not_C_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -152,9 +129,7 @@ entry:
; CHECK-LABEL: ternary_A_not_B_and_BC_4x32
; CHECK: xxlnor vs0, v3, v3
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_not_B_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -166,13 +141,9 @@ entry:
; Function to test ternary(A, not(B), and(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_not_B_and_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v3, v3
+; CHECK: xxlnor vs0, v3, v3
; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_not_B_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
index a04c2500ea91a..7f9741d7d37f7 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
@@ -12,9 +12,7 @@
; Function to test ternary(A, and(B, C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_and_BC_B_4x32
; CHECK: xxland vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_and_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -25,12 +23,8 @@ entry:
; Function to test ternary(A, and(B, C), B) for <2 x i64>
; CHECK-LABEL: ternary_A_and_BC_B_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxland vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxland vs0, v3, v4
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_and_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -42,9 +36,7 @@ entry:
; Function to test ternary(A, nor(B, C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_nor_BC_B_4x32
; CHECK: xxlnor vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nor_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -56,12 +48,8 @@ entry:
; Function to test ternary(A, nor(B, C), B) for <2 x i64>
; CHECK-LABEL: ternary_A_nor_BC_B_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxlnor vs0, v3, v4
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nor_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -74,9 +62,7 @@ entry:
; Function to test ternary(A, eqv(B, C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_eqv_BC_B_4x32
; CHECK: xxleqv vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_eqv_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -88,12 +74,8 @@ entry:
; Function to test ternary(A, eqv(B, C), B) for <2 x i64>
; CHECK-LABEL: ternary_A_eqv_BC_B_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxleqv vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxleqv vs0, v3, v4
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_eqv_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -106,9 +88,7 @@ entry:
; Function to test ternary(A, not(C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_not_C_B_4x32
; CHECK: xxlnor vs0, v4, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_not_C_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -119,12 +99,8 @@ entry:
; Function to test ternary(A, not(C), B) for <2 x i64>
; CHECK-LABEL: ternary_A_not_C_B_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v4, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxlnor vs0, v4, v4
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_not_C_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -136,9 +112,7 @@ entry:
; Function to test ternary(A, nand(B, C), B) for <4 x i32>
; CHECK-LABEL: ternary_A_nand_BC_B_4x32
; CHECK: xxlnand vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nand_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -150,12 +124,8 @@ entry:
; Function to test ternary(A, nand(B, C), B) for <2 x i64>
; CHECK-LABEL: ternary_A_nand_BC_B_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnand vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK: xxlnand vs0, v3, v4
+; CHECK: xxsel v2, v3, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nand_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
index 5b5b5eaeb50cf..ba614941cfea4 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
@@ -12,9 +12,7 @@
; Function to test ternary(A, and(B, C), C) for <4 x i32>
; CHECK-LABEL: ternary_A_and_BC_C_4x32
; CHECK: xxland vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK: xxsel v2, v4, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_and_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -25,12 +23,8 @@ entry:
; Function to test ternary(A, and(B, C), C) for <2 x i64>
; CHECK-LABEL: ternary_A_and_BC_C_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxland vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK: xxland vs0, v3, v4
+; CHECK: xxsel v2, v4, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_and_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -42,9 +36,7 @@ entry:
; Function to test ternary(A, nor(B, C), C) for <4 x i32>
; CHECK-LABEL: ternary_A_nor_BC_C_4x32
; CHECK: xxlnor vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK: xxsel v2, v4, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nor_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -56,12 +48,8 @@ entry:
; Function to test ternary(A, nor(B, C), C) for <2 x i64>
; CHECK-LABEL: ternary_A_nor_BC_C_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK: xxlnor vs0, v3, v4
+; CHECK: xxsel v2, v4, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nor_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -74,9 +62,7 @@ entry:
; Function to test ternary(A, eqv(B, C), C) for <4 x i32>
; CHECK-LABEL: ternary_A_eqv_BC_C_4x32
; CHECK: xxleqv vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK: xxsel v2, v4, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_eqv_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -88,12 +74,8 @@ entry:
; Function to test ternary(A, eqv(B, C), C) for <2 x i64>
; CHECK-LABEL: ternary_A_eqv_BC_C_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxleqv vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK: xxleqv vs0, v3, v4
+; CHECK: xxsel v2, v4, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_eqv_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -106,9 +88,7 @@ entry:
; Function to test ternary(A, nand(B, C), C) for <4 x i32>
; CHECK-LABEL: ternary_A_nand_BC_C_4x32
; CHECK: xxlnand vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK: xxsel v2, v4, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nand_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -120,12 +100,8 @@ entry:
; Function to test ternary(A, nand(B, C), C) for <2 x i64>
; CHECK-LABEL: ternary_A_nand_BC_C_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnand vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK: xxlnand vs0, v3, v4
+; CHECK: xxsel v2, v4, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nand_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
index dcdf463b924e1..dfce8ef56ba01 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
@@ -13,9 +13,7 @@
; CHECK-LABEL: ternary_A_and_BC_xor_BC_4x32
; CHECK: xxland vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_and_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -27,13 +25,9 @@ entry:
; Function to test ternary(A, and(B, C), xor(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_and_BC_xor_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK: xxland vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_and_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -46,9 +40,7 @@ entry:
; Function to test ternary(A, B, xor(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_B_xor_BC_4x32
; CHECK: xxlxor vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK: xxsel v2, vs0, v3, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_B_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -59,12 +51,8 @@ entry:
; Function to test ternary(A, B, xor(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_B_xor_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlxor vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK: xxlxor vs0, v3, v4
+; CHECK: xxsel v2, vs0, v3, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_B_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -76,9 +64,7 @@ entry:
; Function to test ternary(A, C, xor(B, C)) for <4 x i32>
; CHECK-LABEL: ternary_A_C_xor_BC_4x32
; CHECK: xxlxor vs0, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK: xxsel v2, vs0, v4, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_C_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -89,12 +75,8 @@ entry:
; Function to test ternary(A, C, xor(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_C_xor_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlxor vs0, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK: xxlxor vs0, v3, v4
+; CHECK: xxsel v2, vs0, v4, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_C_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -107,9 +89,7 @@ entry:
; CHECK-LABEL: ternary_A_or_BC_xor_BC_4x32
; CHECK: xxlor vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_or_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -121,13 +101,9 @@ entry:
; Function to test ternary(A, or(B, C), xor(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_or_BC_xor_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlor vs0, v3, v4
+; CHECK: xxlor vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_or_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
@@ -141,9 +117,7 @@ entry:
; CHECK-LABEL: ternary_A_nor_BC_xor_BC_4x32
; CHECK: xxlnor vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK-NEXT: vslw v2, v2, v5
-; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nor_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
entry:
@@ -156,13 +130,9 @@ entry:
; Function to test ternary(A, nor(B, C), xor(B, C)) for <2 x i64>
; CHECK-LABEL: ternary_A_nor_BC_xor_BC_2x64
-; CHECK: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK: xxlnor vs0, v3, v4
; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK-NEXT: xxsplti32dx v5, 1, 63
-; CHECK-NEXT: vsld v2, v2, v5
-; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK: xxsel v2, vs1, vs0, v2
; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nor_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
entry:
>From 0c1b7d0b7362f4eda1ee021c927deee97acd359a Mon Sep 17 00:00:00 2001
From: Tony Varghese <tony.varghese at ibm.com>
Date: Wed, 28 May 2025 17:25:12 +0000
Subject: [PATCH 5/8] Updated tests using update_llc_test_checks.py
---
.../CodeGen/PowerPC/xxeval-vselect-x-and.ll | 148 ++++++++++++------
.../CodeGen/PowerPC/xxeval-vselect-x-b.ll | 128 ++++++++++-----
.../CodeGen/PowerPC/xxeval-vselect-x-c.ll | 103 ++++++++----
.../CodeGen/PowerPC/xxeval-vselect-x-xor.ll | 138 ++++++++++------
4 files changed, 346 insertions(+), 171 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
index 7187d3bf30f0e..c07db2c584ed2 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Test file to verify the emission of Vector selection instructions when ternary operators are used.
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
@@ -10,12 +11,16 @@
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
; Function to test ternary(A, xor(B, C), and(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_xor_BC_and_BC_4x32
-; CHECK: xxlxor vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_xor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_xor_BC_and_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
%and = and <4 x i32> %B, %C
@@ -24,12 +29,17 @@ entry:
}
; Function to test ternary(A, xor(B, C), and(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_xor_BC_and_BC_2x64
-; CHECK: xxlxor vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_xor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_xor_BC_and_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
%and = and <2 x i64> %B, %C
@@ -38,12 +48,16 @@ entry:
}
; Function to test ternary(A, nor(B, C), and(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_nor_BC_and_BC_4x32
-; CHECK: xxlnor vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nor_BC_and_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <4 x i32> %B, %C
%nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector NOR operation
@@ -53,12 +67,17 @@ entry:
}
; Function to test ternary(A, nor(B, C), and(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_nor_BC_and_BC_2x64
-; CHECK: xxlnor vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nor_BC_and_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <2 x i64> %B, %C
%nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; Vector NOR operation
@@ -68,12 +87,16 @@ entry:
}
; Function to test ternary(A, eqv(B, C), and(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_eqv_BC_and_BC_4x32
-; CHECK: xxleqv vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_eqv_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_eqv_BC_and_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
%eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
@@ -83,12 +106,17 @@ entry:
}
; Function to test ternary(A, eqv(B, C), and(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_eqv_BC_and_BC_2x64
-; CHECK: xxleqv vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_eqv_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_eqv_BC_and_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
%eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
@@ -98,12 +126,16 @@ entry:
}
; Function to test ternary(A, not(C), and(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_not_C_and_BC_4x32
-; CHECK: xxlnor vs0, v4, v4
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_not_C_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_not_C_and_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%not = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
%and = and <4 x i32> %B, %C
@@ -112,12 +144,17 @@ entry:
}
; Function to test ternary(A, not(C), and(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_not_C_and_BC_2x64
-; CHECK: xxlnor vs0, v4, v4
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_not_C_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_not_C_and_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
%and = and <2 x i64> %B, %C
@@ -126,12 +163,16 @@ entry:
}
; Function to test ternary(A, not(B), and(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_not_B_and_BC_4x32
-; CHECK: xxlnor vs0, v3, v3
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_not_B_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_not_B_and_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v3
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%not = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
%and = and <4 x i32> %B, %C
@@ -140,15 +181,20 @@ entry:
}
; Function to test ternary(A, not(B), and(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_not_B_and_BC_2x64
-; CHECK: xxlnor vs0, v3, v3
-; CHECK-NEXT: xxland vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_not_B_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_not_B_and_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v3
+; CHECK-NEXT: xxland vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%not = xor <2 x i64> %B, <i64 -1, i64 -1> ; Vector not operation
%and = and <2 x i64> %B, %C
%res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %and
ret <2 x i64> %res
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
index 7f9741d7d37f7..dc22b5786b695 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Test file to verify the emission of Vector selection instructions when ternary operators are used.
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
@@ -10,11 +11,15 @@
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
; Function to test ternary(A, and(B, C), B) for <4 x i32>
-; CHECK-LABEL: ternary_A_and_BC_B_4x32
-; CHECK: xxland vs0, v3, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_and_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_and_BC_B_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <4 x i32> %B, %C
%res = select <4 x i1> %A, <4 x i32> %and, <4 x i32> %B
@@ -22,11 +27,16 @@ entry:
}
; Function to test ternary(A, and(B, C), B) for <2 x i64>
-; CHECK-LABEL: ternary_A_and_BC_B_2x64
-; CHECK: xxland vs0, v3, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_and_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_and_BC_B_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <2 x i64> %B, %C
%res = select <2 x i1> %A, <2 x i64> %and, <2 x i64> %B
@@ -34,11 +44,15 @@ entry:
}
; Function to test ternary(A, nor(B, C), B) for <4 x i32>
-; CHECK-LABEL: ternary_A_nor_BC_B_4x32
-; CHECK: xxlnor vs0, v3, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nor_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nor_BC_B_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <4 x i32> %B, %C
%nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector NOR operation
@@ -47,11 +61,16 @@ entry:
}
; Function to test ternary(A, nor(B, C), B) for <2 x i64>
-; CHECK-LABEL: ternary_A_nor_BC_B_2x64
-; CHECK: xxlnor vs0, v3, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nor_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nor_BC_B_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <2 x i64> %B, %C
%nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; Vector NOR operation
@@ -60,11 +79,15 @@ entry:
}
; Function to test ternary(A, eqv(B, C), B) for <4 x i32>
-; CHECK-LABEL: ternary_A_eqv_BC_B_4x32
-; CHECK: xxleqv vs0, v3, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_eqv_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_eqv_BC_B_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
%eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
@@ -73,11 +96,16 @@ entry:
}
; Function to test ternary(A, eqv(B, C), B) for <2 x i64>
-; CHECK-LABEL: ternary_A_eqv_BC_B_2x64
-; CHECK: xxleqv vs0, v3, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_eqv_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_eqv_BC_B_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
%eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
@@ -86,11 +114,15 @@ entry:
}
; Function to test ternary(A, not(C), B) for <4 x i32>
-; CHECK-LABEL: ternary_A_not_C_B_4x32
-; CHECK: xxlnor vs0, v4, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_not_C_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_not_C_B_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%not = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
%res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %B
@@ -98,11 +130,16 @@ entry:
}
; Function to test ternary(A, not(C), B) for <2 x i64>
-; CHECK-LABEL: ternary_A_not_C_B_2x64
-; CHECK: xxlnor vs0, v4, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_not_C_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_not_C_B_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v4, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
%res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %B
@@ -110,11 +147,15 @@ entry:
}
; Function to test ternary(A, nand(B, C), B) for <4 x i32>
-; CHECK-LABEL: ternary_A_nand_BC_B_4x32
-; CHECK: xxlnand vs0, v3, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nand_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nand_BC_B_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <4 x i32> %B, %C
%nand = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector nand operation
@@ -123,14 +164,19 @@ entry:
}
; Function to test ternary(A, nand(B, C), B) for <2 x i64>
-; CHECK-LABEL: ternary_A_nand_BC_B_2x64
-; CHECK: xxlnand vs0, v3, v4
-; CHECK: xxsel v2, v3, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nand_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nand_BC_B_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <2 x i64> %B, %C
%nand = xor <2 x i64> %and, <i64 -1, i64 -1> ; Vector nand operation
%res = select <2 x i1> %A, <2 x i64> %nand, <2 x i64> %B
ret <2 x i64> %res
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
index ba614941cfea4..59f046ced9a8e 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Test file to verify the emission of Vector selection instructions when ternary operators are used.
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
@@ -10,11 +11,15 @@
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
; Function to test ternary(A, and(B, C), C) for <4 x i32>
-; CHECK-LABEL: ternary_A_and_BC_C_4x32
-; CHECK: xxland vs0, v3, v4
-; CHECK: xxsel v2, v4, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_and_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_and_BC_C_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <4 x i32> %B, %C
%res = select <4 x i1> %A, <4 x i32> %and, <4 x i32> %C
@@ -22,11 +27,16 @@ entry:
}
; Function to test ternary(A, and(B, C), C) for <2 x i64>
-; CHECK-LABEL: ternary_A_and_BC_C_2x64
-; CHECK: xxland vs0, v3, v4
-; CHECK: xxsel v2, v4, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_and_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_and_BC_C_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <2 x i64> %B, %C
%res = select <2 x i1> %A, <2 x i64> %and, <2 x i64> %C
@@ -34,11 +44,15 @@ entry:
}
; Function to test ternary(A, nor(B, C), C) for <4 x i32>
-; CHECK-LABEL: ternary_A_nor_BC_C_4x32
-; CHECK: xxlnor vs0, v3, v4
-; CHECK: xxsel v2, v4, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nor_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nor_BC_C_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <4 x i32> %B, %C
%nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector NOR operation
@@ -47,11 +61,16 @@ entry:
}
; Function to test ternary(A, nor(B, C), C) for <2 x i64>
-; CHECK-LABEL: ternary_A_nor_BC_C_2x64
-; CHECK: xxlnor vs0, v3, v4
-; CHECK: xxsel v2, v4, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nor_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nor_BC_C_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <2 x i64> %B, %C
%nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; Vector NOR operation
@@ -60,11 +79,15 @@ entry:
}
; Function to test ternary(A, eqv(B, C), C) for <4 x i32>
-; CHECK-LABEL: ternary_A_eqv_BC_C_4x32
-; CHECK: xxleqv vs0, v3, v4
-; CHECK: xxsel v2, v4, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_eqv_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_eqv_BC_C_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
%eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
@@ -73,11 +96,16 @@ entry:
}
; Function to test ternary(A, eqv(B, C), C) for <2 x i64>
-; CHECK-LABEL: ternary_A_eqv_BC_C_2x64
-; CHECK: xxleqv vs0, v3, v4
-; CHECK: xxsel v2, v4, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_eqv_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_eqv_BC_C_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxleqv vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
%eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
@@ -86,11 +114,15 @@ entry:
}
; Function to test ternary(A, nand(B, C), C) for <4 x i32>
-; CHECK-LABEL: ternary_A_nand_BC_C_4x32
-; CHECK: xxlnand vs0, v3, v4
-; CHECK: xxsel v2, v4, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nand_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nand_BC_C_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <4 x i32> %B, %C
%nand = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector nand operation
@@ -99,14 +131,19 @@ entry:
}
; Function to test ternary(A, nand(B, C), C) for <2 x i64>
-; CHECK-LABEL: ternary_A_nand_BC_C_2x64
-; CHECK: xxlnand vs0, v3, v4
-; CHECK: xxsel v2, v4, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nand_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nand_BC_C_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnand vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <2 x i64> %B, %C
%nand = xor <2 x i64> %and, <i64 -1, i64 -1> ; Vector nand operation
%res = select <2 x i1> %A, <2 x i64> %nand, <2 x i64> %C
ret <2 x i64> %res
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
index dfce8ef56ba01..88f8bb29dc337 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Test file to verify the emission of Vector selection instructions when ternary operators are used.
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
@@ -10,12 +11,16 @@
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
; Function to test ternary(A, and(B, C), xor(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_and_BC_xor_BC_4x32
-; CHECK: xxland vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_and_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_and_BC_xor_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <4 x i32> %B, %C
%xor = xor <4 x i32> %B, %C
@@ -24,12 +29,17 @@ entry:
}
; Function to test ternary(A, and(B, C), xor(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_and_BC_xor_BC_2x64
-; CHECK: xxland vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_and_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_and_BC_xor_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxland vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%and = and <2 x i64> %B, %C
%xor = xor <2 x i64> %B, %C
@@ -38,11 +48,15 @@ entry:
}
; Function to test ternary(A, B, xor(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_B_xor_BC_4x32
-; CHECK: xxlxor vs0, v3, v4
-; CHECK: xxsel v2, vs0, v3, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_B_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_B_xor_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
%res = select <4 x i1> %A, <4 x i32> %B, <4 x i32> %xor
@@ -50,11 +64,16 @@ entry:
}
; Function to test ternary(A, B, xor(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_B_xor_BC_2x64
-; CHECK: xxlxor vs0, v3, v4
-; CHECK: xxsel v2, vs0, v3, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_B_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_B_xor_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
%res = select <2 x i1> %A, <2 x i64> %B, <2 x i64> %xor
@@ -62,11 +81,15 @@ entry:
}
; Function to test ternary(A, C, xor(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_C_xor_BC_4x32
-; CHECK: xxlxor vs0, v3, v4
-; CHECK: xxsel v2, vs0, v4, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_C_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_C_xor_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
%res = select <4 x i1> %A, <4 x i32> %C, <4 x i32> %xor
@@ -74,11 +97,16 @@ entry:
}
; Function to test ternary(A, C, xor(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_C_xor_BC_2x64
-; CHECK: xxlxor vs0, v3, v4
-; CHECK: xxsel v2, vs0, v4, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_C_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_C_xor_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlxor vs0, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
%res = select <2 x i1> %A, <2 x i64> %C, <2 x i64> %xor
@@ -86,12 +114,16 @@ entry:
}
; Function to test ternary(A, or(B, C), xor(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_or_BC_xor_BC_4x32
-; CHECK: xxlor vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_or_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_or_BC_xor_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlor vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <4 x i32> %B, %C
%xor = xor <4 x i32> %B, %C
@@ -100,12 +132,17 @@ entry:
}
; Function to test ternary(A, or(B, C), xor(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_or_BC_xor_BC_2x64
-; CHECK: xxlor vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_or_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_or_BC_xor_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlor vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <2 x i64> %B, %C
%xor = xor <2 x i64> %B, %C
@@ -114,12 +151,16 @@ entry:
}
; Function to test ternary(A, nor(B, C), xor(B, C)) for <4 x i32>
-; CHECK-LABEL: ternary_A_nor_BC_xor_BC_4x32
-; CHECK: xxlnor vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <4 x i32> @ternary_A_nor_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nor_BC_xor_BC_4x32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltiw v5, 31
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: vslw v2, v2, v5
+; CHECK-NEXT: vsraw v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <4 x i32> %B, %C
%nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; vector nor operation
@@ -129,12 +170,17 @@ entry:
}
; Function to test ternary(A, nor(B, C), xor(B, C)) for <2 x i64>
-; CHECK-LABEL: ternary_A_nor_BC_xor_BC_2x64
-; CHECK: xxlnor vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
-; CHECK: xxsel v2, vs1, vs0, v2
-; CHECK-NEXT: blr
define dso_local <2 x i64> @ternary_A_nor_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
+; CHECK-LABEL: ternary_A_nor_BC_xor_BC_2x64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxlxor v5, v5, v5
+; CHECK-NEXT: xxlnor vs0, v3, v4
+; CHECK-NEXT: xxlxor vs1, v3, v4
+; CHECK-NEXT: xxsplti32dx v5, 1, 63
+; CHECK-NEXT: vsld v2, v2, v5
+; CHECK-NEXT: vsrad v2, v2, v5
+; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: blr
entry:
%or = or <2 x i64> %B, %C
%nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; vector nor operation
>From c70ced43a327a712df6518b352b3e07e002586c3 Mon Sep 17 00:00:00 2001
From: Tony Varghese <tony.varghese at ibm.com>
Date: Wed, 28 May 2025 06:40:25 +0000
Subject: [PATCH 6/8] [P10][xxeval] Support xxeval instructions for ternary
operations.
---
llvm/lib/Target/PowerPC/PPCInstrP10.td | 202 +++++++++++++++++++++----
1 file changed, 170 insertions(+), 32 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td
index 39a1ab0d388a7..99f77e18e43a0 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -2159,8 +2159,133 @@ let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in {
(COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
}
-class xxevalPattern <dag pattern, bits<8> imm> :
- Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {}
+class xxevalPattern <ValueType vt, dag pattern, bits<8> imm> :
+ Pat<(vt pattern), (XXEVAL $vA, $vB, $vC, imm)> {}
+
+class DagUnaryVNot<ValueType vt, string opstr>{
+ // Defines a class that returns the UnaryVNot dag for an operand string based on a value type.
+ dag res = !cond(
+ !eq(vt, v4i32) : !dag(vnot, [v4i32], [opstr]),
+ !eq(vt, v2i64) : (v2i64 (bitconvert (vnot (v4i32 !dag(bitconvert, [v2i64], [opstr])))))
+ );
+}
+
+class DagCondVNot<dag d, bit negate> {
+ // Defines a class that generates a vnot around the dag.
+ dag res = !if(!ne(negate, 0),
+ (vnot d),
+ d);
+}
+
+class XXEvalUnaryNot<ValueType vt> {
+ // Defines a wrapper class for unary NOT operations for v4i32 and v2i64 vector types.
+ // Unary NOT on operand B or C based on value type.
+ dag opB = DagUnaryVNot<vt, "vB">.res;
+ dag opC = DagUnaryVNot<vt, "vC">.res;
+}
+
+class XXEvalBinaryPattern<ValueType vt, SDPatternOperator op, bit notResult = 0> {
+ // Defines a wrapper class for binary patterns with optional NOT on result.
+ // Generate op pattern with optional NOT wrapping for result depending on "notResult".
+ dag opPat = !cond(
+ !eq(vt, v4i32) : DagCondVNot<(op v4i32:$vB, v4i32:$vC), notResult>.res,
+ !eq(vt, v2i64) : (v2i64 (bitconvert DagCondVNot<(op
+ (v4i32 (bitconvert v2i64:$vB)),
+ (v4i32 (bitconvert v2i64:$vC))), notResult>.res))
+ );
+}
+
+multiclass XXEvalVSelectWithXAnd<ValueType vt, bits<8> baseImm> {
+ // Multiclass for Ternary(A, X, and(B, C)) style patterns.
+ // Ternary(A, xor(B,C), and(B,C)) => imm: baseImm
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, XXEvalBinaryPattern<vt, xor>.opPat, XXEvalBinaryPattern<vt, and>.opPat),
+ baseImm>;
+ // Ternary(A, nor(B,C), and(B,C)) => imm: baseImm + 2
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, XXEvalBinaryPattern<vt, or, 1>.opPat, XXEvalBinaryPattern<vt, and>.opPat),
+ !add(baseImm, 2)>;
+ // Ternary(A, eqv(B,C), and(B,C)) => imm: baseImm + 3
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, XXEvalBinaryPattern<vt, xor, 1>.opPat, XXEvalBinaryPattern<vt, and>.opPat),
+ !add(baseImm, 3)>;
+ // Ternary(A, not(C), and(B,C)) => imm: baseImm + 4
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, XXEvalUnaryNot<vt>.opC, XXEvalBinaryPattern<vt, and>.opPat),
+ !add(baseImm, 4)>;
+ // Ternary(A, not(B), and(B,C)) => imm: baseImm + 6
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, XXEvalUnaryNot<vt>.opB, XXEvalBinaryPattern<vt, and>.opPat),
+ !add(baseImm, 6)>;
+}
+
+multiclass XXEvalVSelectWithXB<ValueType vt, bits<8> baseImm>{
+ // Multiclass for Ternary(A, X, B) style patterns
+ // Ternary(A, and(B,C), B) => imm: baseImm
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, XXEvalBinaryPattern<vt, and>.opPat, vt:$vB),
+ baseImm>;
+ // Ternary(A, nor(B,C), B) => imm: baseImm + 7
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, XXEvalBinaryPattern<vt, or, 1>.opPat, vt:$vB),
+ !add(baseImm, 7)>;
+ // Ternary(A, eqv(B,C), B) => imm: baseImm + 8
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, XXEvalBinaryPattern<vt, xor, 1>.opPat, vt:$vB),
+ !add(baseImm, 8)>;
+ // Ternary(A, not(C), B) => imm: baseImm + 9
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, XXEvalUnaryNot<vt>.opC, vt:$vB),
+ !add(baseImm, 9)>;
+ // Ternary(A, nand(B,C), B) => imm: baseImm + 13
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, XXEvalBinaryPattern<vt, and, 1>.opPat, vt:$vB),
+ !add(baseImm, 13)>;
+}
+
+multiclass XXEvalVSelectWithXC<ValueType vt, bits<8> baseImm>{
+ // Multiclass for Ternary(A, X, C) style patterns
+ // Ternary(A, and(B,C), C) => imm: baseImm
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, XXEvalBinaryPattern<vt, and>.opPat, vt:$vC),
+ baseImm>;
+ // Ternary(A, nor(B,C), C) => imm: baseImm + 7
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, XXEvalBinaryPattern<vt, or, 1>.opPat, vt:$vC),
+ !add(baseImm, 7)>;
+ // Ternary(A, eqv(B,C), C) => imm: baseImm + 8
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, XXEvalBinaryPattern<vt, xor, 1>.opPat, vt:$vC),
+ !add(baseImm, 8)>;
+ // Ternary(A, nand(B,C), C) => imm: baseImm + 13
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, XXEvalBinaryPattern<vt, and, 1>.opPat, vt:$vC),
+ !add(baseImm, 13)>;
+}
+
+multiclass XXEvalVSelectWithXXor<ValueType vt, bits<8> baseImm>{
+ // Multiclass for Ternary(A, X, xor(B,C)) style patterns
+ // Ternary(A, and(B,C), xor(B,C)) => imm: baseImm
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, XXEvalBinaryPattern<vt, and>.opPat, XXEvalBinaryPattern<vt, xor>.opPat),
+ baseImm>;
+ // Ternary(A, B, xor(B,C)) => imm: baseImm + 2
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, vt:$vB, XXEvalBinaryPattern<vt, xor>.opPat),
+ !add(baseImm, 2)>;
+ // Ternary(A, C, xor(B,C)) => imm: baseImm + 4
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, vt:$vC, XXEvalBinaryPattern<vt, xor>.opPat),
+ !add(baseImm, 4)>;
+ // Ternary(A, or(B,C), xor(B,C)) => imm: baseImm + 6
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, XXEvalBinaryPattern<vt, or>.opPat, XXEvalBinaryPattern<vt, xor>.opPat),
+ !add(baseImm, 6)>;
+ // Ternary(A, nor(B,C), xor(B,C)) => imm: baseImm + 7
+ def : xxevalPattern<vt,
+ (vselect vt:$vA, XXEvalBinaryPattern<vt, or, 1>.opPat, XXEvalBinaryPattern<vt, xor>.opPat),
+ !add(baseImm, 7)>;
+}
let Predicates = [PrefixInstrs, HasP10Vector] in {
let AddedComplexity = 400 in {
@@ -2192,83 +2317,96 @@ let Predicates = [PrefixInstrs, HasP10Vector] in {
// Anonymous patterns for XXEVAL
// AND
// and(A, B, C)
- def : xxevalPattern<(and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>;
+ def : xxevalPattern<v4i32, (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>;
// and(A, xor(B, C))
- def : xxevalPattern<(and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 6>;
+ def : xxevalPattern<v4i32, (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 6>;
// and(A, or(B, C))
- def : xxevalPattern<(and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>;
+ def : xxevalPattern<v4i32, (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>;
// and(A, nor(B, C))
- def : xxevalPattern<(and v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 8>;
+ def : xxevalPattern<v4i32, (and v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 8>;
// and(A, eqv(B, C))
- def : xxevalPattern<(and v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 9>;
+ def : xxevalPattern<v4i32, (and v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 9>;
// and(A, nand(B, C))
- def : xxevalPattern<(and v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 14>;
+ def : xxevalPattern<v4i32, (and v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 14>;
// NAND
// nand(A, B, C)
- def : xxevalPattern<(vnot (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))),
+ def : xxevalPattern<v4i32, (vnot (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))),
!sub(255, 1)>;
// nand(A, xor(B, C))
- def : xxevalPattern<(vnot (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))),
+ def : xxevalPattern<v4i32, (vnot (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))),
!sub(255, 6)>;
// nand(A, or(B, C))
- def : xxevalPattern<(vnot (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))),
+ def : xxevalPattern<v4i32, (vnot (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))),
!sub(255, 7)>;
// nand(A, nor(B, C))
- def : xxevalPattern<(or (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)),
+ def : xxevalPattern<v4i32, (or (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)),
!sub(255, 8)>;
// nand(A, eqv(B, C))
- def : xxevalPattern<(or (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)),
+ def : xxevalPattern<v4i32, (or (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)),
!sub(255, 9)>;
// nand(A, nand(B, C))
- def : xxevalPattern<(or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)),
+ def : xxevalPattern<v4i32, (or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)),
!sub(255, 14)>;
// EQV
// (eqv A, B, C)
- def : xxevalPattern<(or (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)),
+ def : xxevalPattern<v4i32, (or (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)),
(vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)))),
150>;
// (eqv A, (and B, C))
- def : xxevalPattern<(vnot (xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 225>;
+ def : xxevalPattern<v4i32, (vnot (xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 225>;
// (eqv A, (or B, C))
- def : xxevalPattern<(vnot (xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 135>;
+ def : xxevalPattern<v4i32, (vnot (xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 135>;
// NOR
// (nor A, B, C)
- def : xxevalPattern<(vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 128>;
+ def : xxevalPattern<v4i32, (vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 128>;
// (nor A, (and B, C))
- def : xxevalPattern<(vnot (or v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 224>;
+ def : xxevalPattern<v4i32, (vnot (or v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 224>;
// (nor A, (eqv B, C))
- def : xxevalPattern<(and (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), 96>;
+ def : xxevalPattern<v4i32, (and (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), 96>;
// (nor A, (nand B, C))
- def : xxevalPattern<(and (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), 16>;
+ def : xxevalPattern<v4i32, (and (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), 16>;
// (nor A, (nor B, C))
- def : xxevalPattern<(and (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), 112>;
+ def : xxevalPattern<v4i32, (and (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), 112>;
// (nor A, (xor B, C))
- def : xxevalPattern<(vnot (or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), 144>;
+ def : xxevalPattern<v4i32, (vnot (or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), 144>;
// OR
// (or A, B, C)
- def : xxevalPattern<(or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 127>;
+ def : xxevalPattern<v4i32, (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 127>;
// (or A, (and B, C))
- def : xxevalPattern<(or v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 31>;
+ def : xxevalPattern<v4i32, (or v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 31>;
// (or A, (eqv B, C))
- def : xxevalPattern<(or v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 159>;
+ def : xxevalPattern<v4i32, (or v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 159>;
// (or A, (nand B, C))
- def : xxevalPattern<(or v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 239>;
+ def : xxevalPattern<v4i32, (or v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 239>;
// (or A, (nor B, C))
- def : xxevalPattern<(or v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 143>;
+ def : xxevalPattern<v4i32, (or v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 143>;
// (or A, (xor B, C))
- def : xxevalPattern<(or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 111>;
+ def : xxevalPattern<v4i32, (or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 111>;
// XOR
// (xor A, B, C)
- def : xxevalPattern<(xor v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 105>;
+ def : xxevalPattern<v4i32, (xor v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 105>;
// (xor A, (and B, C))
- def : xxevalPattern<(xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 30>;
+ def : xxevalPattern<v4i32, (xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 30>;
// (xor A, (or B, C))
- def : xxevalPattern<(xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 120>;
+ def : xxevalPattern<v4i32, (xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 120>;
+
+ // Ternary operation support with the xxeval instruction.
+ defm : XXEvalVSelectWithXAnd<v4i32, 22>;
+ defm : XXEvalVSelectWithXAnd<v2i64, 22>;
+
+ defm : XXEvalVSelectWithXB<v4i32, 49>;
+ defm : XXEvalVSelectWithXB<v2i64, 49>;
+
+ defm : XXEvalVSelectWithXC<v4i32, 81>;
+ defm : XXEvalVSelectWithXC<v2i64, 81>;
+
+ defm : XXEvalVSelectWithXXor<v4i32, 97>;
+ defm : XXEvalVSelectWithXXor<v2i64, 97>;
// Anonymous patterns to select prefixed VSX loads and stores.
// Load / Store f128
>From d1b8c480853030107166698a8a0279f480e9e4b0 Mon Sep 17 00:00:00 2001
From: Tony Varghese <tony.varghese at ibm.com>
Date: Wed, 28 May 2025 17:40:16 +0000
Subject: [PATCH 7/8] rebased to the NFC patch branch
---
.../CodeGen/PowerPC/xxeval-vselect-x-and.ll | 40 +++++--------------
.../CodeGen/PowerPC/xxeval-vselect-x-b.ll | 30 +++++---------
.../CodeGen/PowerPC/xxeval-vselect-x-c.ll | 24 ++++-------
.../CodeGen/PowerPC/xxeval-vselect-x-xor.ll | 36 +++++------------
4 files changed, 38 insertions(+), 92 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
index c07db2c584ed2..37c30374a3a18 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
@@ -15,11 +15,9 @@ define dso_local <4 x i32> @ternary_A_xor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32>
; CHECK-LABEL: ternary_A_xor_BC_and_BC_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxlxor vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 22
; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
@@ -33,12 +31,10 @@ define dso_local <2 x i64> @ternary_A_xor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64>
; CHECK-LABEL: ternary_A_xor_BC_and_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlxor vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 22
; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
@@ -52,11 +48,9 @@ define dso_local <4 x i32> @ternary_A_nor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32>
; CHECK-LABEL: ternary_A_nor_BC_and_BC_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 24
; CHECK-NEXT: blr
entry:
%or = or <4 x i32> %B, %C
@@ -71,12 +65,10 @@ define dso_local <2 x i64> @ternary_A_nor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64>
; CHECK-LABEL: ternary_A_nor_BC_and_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 24
; CHECK-NEXT: blr
entry:
%or = or <2 x i64> %B, %C
@@ -91,11 +83,9 @@ define dso_local <4 x i32> @ternary_A_eqv_BC_and_BC_4x32(<4 x i1> %A, <4 x i32>
; CHECK-LABEL: ternary_A_eqv_BC_and_BC_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxleqv vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 25
; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
@@ -110,12 +100,10 @@ define dso_local <2 x i64> @ternary_A_eqv_BC_and_BC_2x64(<2 x i1> %A, <2 x i64>
; CHECK-LABEL: ternary_A_eqv_BC_and_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxleqv vs0, v3, v4
-; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 25
; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
@@ -130,11 +118,9 @@ define dso_local <4 x i32> @ternary_A_not_C_and_BC_4x32(<4 x i1> %A, <4 x i32> %
; CHECK-LABEL: ternary_A_not_C_and_BC_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v4, v4
-; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 26
; CHECK-NEXT: blr
entry:
%not = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
@@ -148,12 +134,10 @@ define dso_local <2 x i64> @ternary_A_not_C_and_BC_2x64(<2 x i1> %A, <2 x i64> %
; CHECK-LABEL: ternary_A_not_C_and_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v4, v4
-; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 26
; CHECK-NEXT: blr
entry:
%not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
@@ -167,11 +151,9 @@ define dso_local <4 x i32> @ternary_A_not_B_and_BC_4x32(<4 x i1> %A, <4 x i32> %
; CHECK-LABEL: ternary_A_not_B_and_BC_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v3, v3
-; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 28
; CHECK-NEXT: blr
entry:
%not = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
@@ -185,12 +167,10 @@ define dso_local <2 x i64> @ternary_A_not_B_and_BC_2x64(<2 x i1> %A, <2 x i64> %
; CHECK-LABEL: ternary_A_not_B_and_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v3, v3
-; CHECK-NEXT: xxland vs1, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 28
; CHECK-NEXT: blr
entry:
%not = xor <2 x i64> %B, <i64 -1, i64 -1> ; Vector not operation
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
index dc22b5786b695..2ee9a4875ac3c 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
@@ -15,10 +15,9 @@ define dso_local <4 x i32> @ternary_A_and_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <
; CHECK-LABEL: ternary_A_and_BC_B_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxland vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 49
; CHECK-NEXT: blr
entry:
%and = and <4 x i32> %B, %C
@@ -31,11 +30,10 @@ define dso_local <2 x i64> @ternary_A_and_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <
; CHECK-LABEL: ternary_A_and_BC_B_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxland vs0, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 49
; CHECK-NEXT: blr
entry:
%and = and <2 x i64> %B, %C
@@ -48,10 +46,9 @@ define dso_local <4 x i32> @ternary_A_nor_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <
; CHECK-LABEL: ternary_A_nor_BC_B_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 56
; CHECK-NEXT: blr
entry:
%or = or <4 x i32> %B, %C
@@ -65,11 +62,10 @@ define dso_local <2 x i64> @ternary_A_nor_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <
; CHECK-LABEL: ternary_A_nor_BC_B_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 56
; CHECK-NEXT: blr
entry:
%or = or <2 x i64> %B, %C
@@ -83,10 +79,9 @@ define dso_local <4 x i32> @ternary_A_eqv_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <
; CHECK-LABEL: ternary_A_eqv_BC_B_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxleqv vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 57
; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
@@ -100,11 +95,10 @@ define dso_local <2 x i64> @ternary_A_eqv_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <
; CHECK-LABEL: ternary_A_eqv_BC_B_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxleqv vs0, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 57
; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
@@ -118,10 +112,9 @@ define dso_local <4 x i32> @ternary_A_not_C_B_4x32(<4 x i1> %A, <4 x i32> %B, <4
; CHECK-LABEL: ternary_A_not_C_B_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v4, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 58
; CHECK-NEXT: blr
entry:
%not = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
@@ -134,11 +127,10 @@ define dso_local <2 x i64> @ternary_A_not_C_B_2x64(<2 x i1> %A, <2 x i64> %B, <2
; CHECK-LABEL: ternary_A_not_C_B_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v4, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 58
; CHECK-NEXT: blr
entry:
%not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
@@ -151,10 +143,9 @@ define dso_local <4 x i32> @ternary_A_nand_BC_B_4x32(<4 x i1> %A, <4 x i32> %B,
; CHECK-LABEL: ternary_A_nand_BC_B_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxlnand vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 62
; CHECK-NEXT: blr
entry:
%and = and <4 x i32> %B, %C
@@ -168,11 +159,10 @@ define dso_local <2 x i64> @ternary_A_nand_BC_B_2x64(<2 x i1> %A, <2 x i64> %B,
; CHECK-LABEL: ternary_A_nand_BC_B_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnand vs0, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v3, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 62
; CHECK-NEXT: blr
entry:
%and = and <2 x i64> %B, %C
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
index 59f046ced9a8e..80a2eb52e708a 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
@@ -15,10 +15,9 @@ define dso_local <4 x i32> @ternary_A_and_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <
; CHECK-LABEL: ternary_A_and_BC_C_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxland vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 81
; CHECK-NEXT: blr
entry:
%and = and <4 x i32> %B, %C
@@ -31,11 +30,10 @@ define dso_local <2 x i64> @ternary_A_and_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <
; CHECK-LABEL: ternary_A_and_BC_C_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxland vs0, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 81
; CHECK-NEXT: blr
entry:
%and = and <2 x i64> %B, %C
@@ -48,10 +46,9 @@ define dso_local <4 x i32> @ternary_A_nor_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <
; CHECK-LABEL: ternary_A_nor_BC_C_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 88
; CHECK-NEXT: blr
entry:
%or = or <4 x i32> %B, %C
@@ -65,11 +62,10 @@ define dso_local <2 x i64> @ternary_A_nor_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <
; CHECK-LABEL: ternary_A_nor_BC_C_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 88
; CHECK-NEXT: blr
entry:
%or = or <2 x i64> %B, %C
@@ -83,10 +79,9 @@ define dso_local <4 x i32> @ternary_A_eqv_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <
; CHECK-LABEL: ternary_A_eqv_BC_C_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxleqv vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 89
; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
@@ -100,11 +95,10 @@ define dso_local <2 x i64> @ternary_A_eqv_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <
; CHECK-LABEL: ternary_A_eqv_BC_C_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxleqv vs0, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 89
; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
@@ -118,10 +112,9 @@ define dso_local <4 x i32> @ternary_A_nand_BC_C_4x32(<4 x i1> %A, <4 x i32> %B,
; CHECK-LABEL: ternary_A_nand_BC_C_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxlnand vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 94
; CHECK-NEXT: blr
entry:
%and = and <4 x i32> %B, %C
@@ -135,11 +128,10 @@ define dso_local <2 x i64> @ternary_A_nand_BC_C_2x64(<2 x i1> %A, <2 x i64> %B,
; CHECK-LABEL: ternary_A_nand_BC_C_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnand vs0, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, v4, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 94
; CHECK-NEXT: blr
entry:
%and = and <2 x i64> %B, %C
diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
index 88f8bb29dc337..86790856dc613 100644
--- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
+++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
@@ -15,11 +15,9 @@ define dso_local <4 x i32> @ternary_A_and_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32>
; CHECK-LABEL: ternary_A_and_BC_xor_BC_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxland vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 97
; CHECK-NEXT: blr
entry:
%and = and <4 x i32> %B, %C
@@ -33,12 +31,10 @@ define dso_local <2 x i64> @ternary_A_and_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64>
; CHECK-LABEL: ternary_A_and_BC_xor_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxland vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 97
; CHECK-NEXT: blr
entry:
%and = and <2 x i64> %B, %C
@@ -52,10 +48,9 @@ define dso_local <4 x i32> @ternary_A_B_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <
; CHECK-LABEL: ternary_A_B_xor_BC_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxlxor vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 99
; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
@@ -68,11 +63,10 @@ define dso_local <2 x i64> @ternary_A_B_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <
; CHECK-LABEL: ternary_A_B_xor_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlxor vs0, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs0, v3, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 99
; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
@@ -85,10 +79,9 @@ define dso_local <4 x i32> @ternary_A_C_xor_BC_4x32(<4 x i1> %A, <4 x i32> %B, <
; CHECK-LABEL: ternary_A_C_xor_BC_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxlxor vs0, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 101
; CHECK-NEXT: blr
entry:
%xor = xor <4 x i32> %B, %C
@@ -101,11 +94,10 @@ define dso_local <2 x i64> @ternary_A_C_xor_BC_2x64(<2 x i1> %A, <2 x i64> %B, <
; CHECK-LABEL: ternary_A_C_xor_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlxor vs0, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs0, v4, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 101
; CHECK-NEXT: blr
entry:
%xor = xor <2 x i64> %B, %C
@@ -118,11 +110,9 @@ define dso_local <4 x i32> @ternary_A_or_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32> %
; CHECK-LABEL: ternary_A_or_BC_xor_BC_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxlor vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 103
; CHECK-NEXT: blr
entry:
%or = or <4 x i32> %B, %C
@@ -136,12 +126,10 @@ define dso_local <2 x i64> @ternary_A_or_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64> %
; CHECK-LABEL: ternary_A_or_BC_xor_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlor vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 103
; CHECK-NEXT: blr
entry:
%or = or <2 x i64> %B, %C
@@ -155,11 +143,9 @@ define dso_local <4 x i32> @ternary_A_nor_BC_xor_BC_4x32(<4 x i1> %A, <4 x i32>
; CHECK-LABEL: ternary_A_nor_BC_xor_BC_4x32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltiw v5, 31
-; CHECK-NEXT: xxlnor vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
; CHECK-NEXT: vslw v2, v2, v5
; CHECK-NEXT: vsraw v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 104
; CHECK-NEXT: blr
entry:
%or = or <4 x i32> %B, %C
@@ -174,12 +160,10 @@ define dso_local <2 x i64> @ternary_A_nor_BC_xor_BC_2x64(<2 x i1> %A, <2 x i64>
; CHECK-LABEL: ternary_A_nor_BC_xor_BC_2x64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor v5, v5, v5
-; CHECK-NEXT: xxlnor vs0, v3, v4
-; CHECK-NEXT: xxlxor vs1, v3, v4
; CHECK-NEXT: xxsplti32dx v5, 1, 63
; CHECK-NEXT: vsld v2, v2, v5
; CHECK-NEXT: vsrad v2, v2, v5
-; CHECK-NEXT: xxsel v2, vs1, vs0, v2
+; CHECK-NEXT: xxeval v2, v2, v3, v4, 104
; CHECK-NEXT: blr
entry:
%or = or <2 x i64> %B, %C
>From 27a80947fb800ff377f29ab078e1d70889841fa9 Mon Sep 17 00:00:00 2001
From: Tony Varghese <tony.varghese at ibm.com>
Date: Wed, 28 May 2025 17:46:01 +0000
Subject: [PATCH 8/8] Changed the classname to XXEvalPattern
---
llvm/lib/Target/PowerPC/PPCInstrP10.td | 100 ++++++++++++-------------
1 file changed, 50 insertions(+), 50 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td
index 99f77e18e43a0..3a77ebb6cdfe6 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -2159,7 +2159,7 @@ let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in {
(COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
}
-class xxevalPattern <ValueType vt, dag pattern, bits<8> imm> :
+class XXEvalPattern <ValueType vt, dag pattern, bits<8> imm> :
Pat<(vt pattern), (XXEVAL $vA, $vB, $vC, imm)> {}
class DagUnaryVNot<ValueType vt, string opstr>{
@@ -2198,23 +2198,23 @@ class XXEvalBinaryPattern<ValueType vt, SDPatternOperator op, bit notResult = 0>
multiclass XXEvalVSelectWithXAnd<ValueType vt, bits<8> baseImm> {
// Multiclass for Ternary(A, X, and(B, C)) style patterns.
// Ternary(A, xor(B,C), and(B,C)) => imm: baseImm
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, XXEvalBinaryPattern<vt, xor>.opPat, XXEvalBinaryPattern<vt, and>.opPat),
baseImm>;
// Ternary(A, nor(B,C), and(B,C)) => imm: baseImm + 2
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, XXEvalBinaryPattern<vt, or, 1>.opPat, XXEvalBinaryPattern<vt, and>.opPat),
!add(baseImm, 2)>;
// Ternary(A, eqv(B,C), and(B,C)) => imm: baseImm + 3
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, XXEvalBinaryPattern<vt, xor, 1>.opPat, XXEvalBinaryPattern<vt, and>.opPat),
!add(baseImm, 3)>;
// Ternary(A, not(C), and(B,C)) => imm: baseImm + 4
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, XXEvalUnaryNot<vt>.opC, XXEvalBinaryPattern<vt, and>.opPat),
!add(baseImm, 4)>;
// Ternary(A, not(B), and(B,C)) => imm: baseImm + 6
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, XXEvalUnaryNot<vt>.opB, XXEvalBinaryPattern<vt, and>.opPat),
!add(baseImm, 6)>;
}
@@ -2222,23 +2222,23 @@ multiclass XXEvalVSelectWithXAnd<ValueType vt, bits<8> baseImm> {
multiclass XXEvalVSelectWithXB<ValueType vt, bits<8> baseImm>{
// Multiclass for Ternary(A, X, B) style patterns
// Ternary(A, and(B,C), B) => imm: baseImm
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, XXEvalBinaryPattern<vt, and>.opPat, vt:$vB),
baseImm>;
// Ternary(A, nor(B,C), B) => imm: baseImm + 7
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, XXEvalBinaryPattern<vt, or, 1>.opPat, vt:$vB),
!add(baseImm, 7)>;
// Ternary(A, eqv(B,C), B) => imm: baseImm + 8
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, XXEvalBinaryPattern<vt, xor, 1>.opPat, vt:$vB),
!add(baseImm, 8)>;
// Ternary(A, not(C), B) => imm: baseImm + 9
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, XXEvalUnaryNot<vt>.opC, vt:$vB),
!add(baseImm, 9)>;
// Ternary(A, nand(B,C), B) => imm: baseImm + 13
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, XXEvalBinaryPattern<vt, and, 1>.opPat, vt:$vB),
!add(baseImm, 13)>;
}
@@ -2246,19 +2246,19 @@ multiclass XXEvalVSelectWithXB<ValueType vt, bits<8> baseImm>{
multiclass XXEvalVSelectWithXC<ValueType vt, bits<8> baseImm>{
// Multiclass for Ternary(A, X, C) style patterns
// Ternary(A, and(B,C), C) => imm: baseImm
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, XXEvalBinaryPattern<vt, and>.opPat, vt:$vC),
baseImm>;
// Ternary(A, nor(B,C), C) => imm: baseImm + 7
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, XXEvalBinaryPattern<vt, or, 1>.opPat, vt:$vC),
!add(baseImm, 7)>;
// Ternary(A, eqv(B,C), C) => imm: baseImm + 8
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, XXEvalBinaryPattern<vt, xor, 1>.opPat, vt:$vC),
!add(baseImm, 8)>;
// Ternary(A, nand(B,C), C) => imm: baseImm + 13
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, XXEvalBinaryPattern<vt, and, 1>.opPat, vt:$vC),
!add(baseImm, 13)>;
}
@@ -2266,23 +2266,23 @@ multiclass XXEvalVSelectWithXC<ValueType vt, bits<8> baseImm>{
multiclass XXEvalVSelectWithXXor<ValueType vt, bits<8> baseImm>{
// Multiclass for Ternary(A, X, xor(B,C)) style patterns
// Ternary(A, and(B,C), xor(B,C)) => imm: baseImm
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, XXEvalBinaryPattern<vt, and>.opPat, XXEvalBinaryPattern<vt, xor>.opPat),
baseImm>;
// Ternary(A, B, xor(B,C)) => imm: baseImm + 2
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, vt:$vB, XXEvalBinaryPattern<vt, xor>.opPat),
!add(baseImm, 2)>;
// Ternary(A, C, xor(B,C)) => imm: baseImm + 4
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, vt:$vC, XXEvalBinaryPattern<vt, xor>.opPat),
!add(baseImm, 4)>;
// Ternary(A, or(B,C), xor(B,C)) => imm: baseImm + 6
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, XXEvalBinaryPattern<vt, or>.opPat, XXEvalBinaryPattern<vt, xor>.opPat),
!add(baseImm, 6)>;
// Ternary(A, nor(B,C), xor(B,C)) => imm: baseImm + 7
- def : xxevalPattern<vt,
+ def : XXEvalPattern<vt,
(vselect vt:$vA, XXEvalBinaryPattern<vt, or, 1>.opPat, XXEvalBinaryPattern<vt, xor>.opPat),
!add(baseImm, 7)>;
}
@@ -2317,83 +2317,83 @@ let Predicates = [PrefixInstrs, HasP10Vector] in {
// Anonymous patterns for XXEVAL
// AND
// and(A, B, C)
- def : xxevalPattern<v4i32, (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>;
+ def : XXEvalPattern<v4i32, (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>;
// and(A, xor(B, C))
- def : xxevalPattern<v4i32, (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 6>;
+ def : XXEvalPattern<v4i32, (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 6>;
// and(A, or(B, C))
- def : xxevalPattern<v4i32, (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>;
+ def : XXEvalPattern<v4i32, (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>;
// and(A, nor(B, C))
- def : xxevalPattern<v4i32, (and v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 8>;
+ def : XXEvalPattern<v4i32, (and v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 8>;
// and(A, eqv(B, C))
- def : xxevalPattern<v4i32, (and v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 9>;
+ def : XXEvalPattern<v4i32, (and v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 9>;
// and(A, nand(B, C))
- def : xxevalPattern<v4i32, (and v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 14>;
+ def : XXEvalPattern<v4i32, (and v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 14>;
// NAND
// nand(A, B, C)
- def : xxevalPattern<v4i32, (vnot (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))),
+ def : XXEvalPattern<v4i32, (vnot (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))),
!sub(255, 1)>;
// nand(A, xor(B, C))
- def : xxevalPattern<v4i32, (vnot (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))),
+ def : XXEvalPattern<v4i32, (vnot (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))),
!sub(255, 6)>;
// nand(A, or(B, C))
- def : xxevalPattern<v4i32, (vnot (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))),
+ def : XXEvalPattern<v4i32, (vnot (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))),
!sub(255, 7)>;
// nand(A, nor(B, C))
- def : xxevalPattern<v4i32, (or (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)),
+ def : XXEvalPattern<v4i32, (or (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)),
!sub(255, 8)>;
// nand(A, eqv(B, C))
- def : xxevalPattern<v4i32, (or (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)),
+ def : XXEvalPattern<v4i32, (or (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)),
!sub(255, 9)>;
// nand(A, nand(B, C))
- def : xxevalPattern<v4i32, (or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)),
+ def : XXEvalPattern<v4i32, (or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)),
!sub(255, 14)>;
// EQV
// (eqv A, B, C)
- def : xxevalPattern<v4i32, (or (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)),
+ def : XXEvalPattern<v4i32, (or (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)),
(vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)))),
150>;
// (eqv A, (and B, C))
- def : xxevalPattern<v4i32, (vnot (xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 225>;
+ def : XXEvalPattern<v4i32, (vnot (xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 225>;
// (eqv A, (or B, C))
- def : xxevalPattern<v4i32, (vnot (xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 135>;
+ def : XXEvalPattern<v4i32, (vnot (xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 135>;
// NOR
// (nor A, B, C)
- def : xxevalPattern<v4i32, (vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 128>;
+ def : XXEvalPattern<v4i32, (vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 128>;
// (nor A, (and B, C))
- def : xxevalPattern<v4i32, (vnot (or v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 224>;
+ def : XXEvalPattern<v4i32, (vnot (or v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 224>;
// (nor A, (eqv B, C))
- def : xxevalPattern<v4i32, (and (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), 96>;
+ def : XXEvalPattern<v4i32, (and (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), 96>;
// (nor A, (nand B, C))
- def : xxevalPattern<v4i32, (and (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), 16>;
+ def : XXEvalPattern<v4i32, (and (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), 16>;
// (nor A, (nor B, C))
- def : xxevalPattern<v4i32, (and (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), 112>;
+ def : XXEvalPattern<v4i32, (and (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), 112>;
// (nor A, (xor B, C))
- def : xxevalPattern<v4i32, (vnot (or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), 144>;
+ def : XXEvalPattern<v4i32, (vnot (or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), 144>;
// OR
// (or A, B, C)
- def : xxevalPattern<v4i32, (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 127>;
+ def : XXEvalPattern<v4i32, (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 127>;
// (or A, (and B, C))
- def : xxevalPattern<v4i32, (or v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 31>;
+ def : XXEvalPattern<v4i32, (or v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 31>;
// (or A, (eqv B, C))
- def : xxevalPattern<v4i32, (or v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 159>;
+ def : XXEvalPattern<v4i32, (or v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 159>;
// (or A, (nand B, C))
- def : xxevalPattern<v4i32, (or v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 239>;
+ def : XXEvalPattern<v4i32, (or v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 239>;
// (or A, (nor B, C))
- def : xxevalPattern<v4i32, (or v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 143>;
+ def : XXEvalPattern<v4i32, (or v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 143>;
// (or A, (xor B, C))
- def : xxevalPattern<v4i32, (or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 111>;
+ def : XXEvalPattern<v4i32, (or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 111>;
// XOR
// (xor A, B, C)
- def : xxevalPattern<v4i32, (xor v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 105>;
+ def : XXEvalPattern<v4i32, (xor v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 105>;
// (xor A, (and B, C))
- def : xxevalPattern<v4i32, (xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 30>;
+ def : XXEvalPattern<v4i32, (xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 30>;
// (xor A, (or B, C))
- def : xxevalPattern<v4i32, (xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 120>;
+ def : XXEvalPattern<v4i32, (xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 120>;
// Ternary operation support with the xxeval instruction.
defm : XXEvalVSelectWithXAnd<v4i32, 22>;
- Previous message: [llvm] [PowerPC10][XXEVAL] Exploit xxeval instruction for cases of the ternary(A,X, and(B,C)), ternary(A,X,B), ternary(A,X,C), ternary(A,X,xor(B,C)) forms. (PR #141733)
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