[llvm] [RISCV] Add bltu/bgeu zero => bnez/beqz canonicalisation to RISCVInstrInfo::simplifyInstruction (PR #141775)
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Wed May 28 08:55:21 PDT 2025
================
@@ -4191,6 +4191,24 @@ bool RISCVInstrInfo::simplifyInstruction(MachineInstr &MI) const {
return true;
}
break;
+ case RISCV::BLTU:
+ // bltu zero, rs, imm => bne rs, zero, imm
+ if (MI.getOperand(0).getReg() == RISCV::X0) {
+ MachineOperand MO0 = MI.getOperand(0);
+ MI.removeOperand(0);
+ MI.insert(MI.operands_begin() + 1, {MO0});
+ MI.setDesc(get(RISCV::BNE));
+ }
+ break;
+ case RISCV::BGEU:
+ // bgeu zero, rs, imm => beq rs, zero, imm
----------------
preames wrote:
Thinking about other cases here:
bgeu rs, zero, imm is an unconditionally taken branch. Rewriting as a unconditional branch is hard (due to CFG updates), but maybe we could turn this into beq zero, zero, imm? That would remove the register use, and might compress better?
https://github.com/llvm/llvm-project/pull/141775
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