[llvm] [AMDGPU][SDAG] Initial support for ISD::PTRADD (PR #141725)

[Fabian Ritter via llvm-commits]

================
@@ -1376,6 +1376,37 @@ def : GCNPat <
       (i32 (V_MOV_B32_e32 (i32 0))), sub1)
 >;
 
+//===----------------------------------------------------------------------===//
+// PTRADD Patterns
+//===----------------------------------------------------------------------===//
+
+def : GCNPat<
+  (DivergentBinFrag<ptradd> i64:$src0, i64:$src1),
+  (V_ADD_U64_PSEUDO $src0, $src1)>;
+
+def : GCNPat<
+  (DivergentBinFrag<ptradd> i32:$src0, i32:$src1),
+  (V_ADD_U32_e64 $src0, $src1, 0)> {
+  let SubtargetPredicate = HasAddNoCarryInsts;
+}
+
+def : GCNPat<
+  (DivergentBinFrag<ptradd> i32:$src0, i32:$src1),
+  (V_ADD_CO_U32_e64 $src0, $src1)> {
+  let SubtargetPredicate = NotHasAddNoCarryInsts;
+}
+
+def : GCNPat<
+  (UniformBinFrag<ptradd> i64:$src0, i64:$src1),
+  (S_ADD_U64_PSEUDO $src0, $src1)>;
+
+// Whether we select S_ADD_I32 or S_ADD_U32 does not make much of a
+// difference. Most notably, S_ADD_I32 instructions can be transformed
+// to S_ADDK_I32, so we select that.
+def : GCNPat<
+  (UniformBinFrag<ptradd> i32:$src0, i32:$src1),
+  (S_ADD_I32 $src0, $src1)>;
----------------
ritter-x2a wrote:

I don't think so, GlobalISel lowered that in `AMDGPUInstructionSelector::selectG_ADD_SUB`, with the same code that lowers normal ADDs.

https://github.com/llvm/llvm-project/pull/141725