[llvm] [AMDGPU] Consider FLAT instructions for VMEM hazard detection (PR #137170)

[Robert Imschweiler via llvm-commits]

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@@ -1417,9 +1417,8 @@ static bool shouldRunLdsBranchVmemWARHazardFixup(const MachineFunction &MF,
   bool HasVmem = false;
   for (auto &MBB : MF) {
     for (auto &MI : MBB) {
-      HasLds |= SIInstrInfo::isDS(MI);
-      HasVmem |= (SIInstrInfo::isVMEM(MI) && !SIInstrInfo::isFLAT(MI)) ||
-                 SIInstrInfo::isSegmentSpecificFLAT(MI);
+      HasLds |= SIInstrInfo::isDS(MI) || SIInstrInfo::isLDSDMA(MI);
+      HasVmem |= SIInstrInfo::isVMEM(MI) && !SIInstrInfo::isLDSDMA(MI);
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ro-i wrote:

Are you sure that this applies to all architectures? Because in the MI300 ISA, for example, 9.1.9 says: "The MUBUF instruction format allows reading data from a memory buffer directly into LDS without passing through VGPRs." Without passing through VGPRs would mean that no vector memory is touched and, thus, no hazard can happen within vector memory, right?

https://github.com/llvm/llvm-project/pull/137170