[llvm] [RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (PR #141663)

[Craig Topper via llvm-commits]

================
@@ -94,7 +94,15 @@ static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
       Res.emplace_back(RISCV::LUI, Hi20);
 
     if (Lo12 || Hi20 == 0) {
-      unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI;
+      unsigned AddiOpc = RISCV::ADDI;
+      if (IsRV64 && Hi20) {
+        // Use ADDIW rather than ADDI only when necessary for correctness. As
+        // noted in RISCVOptWInstrs, this helps reduce test differences vs
+        // RV32 without being a pessimization.
+        int64_t LuiRes = SignExtend64<32>(Hi20 << 12);
+        if (LuiRes + Lo12 != SignExtend64<32>(LuiRes + Lo12))
----------------
topperc wrote:

Can this just be

```
if (!isInt<32>(LuiRes + Lo12))
```

https://github.com/llvm/llvm-project/pull/141663