[llvm] ARM: Fix losing subregisters in convertToThreeAddress (PR #141662)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue May 27 12:56:08 PDT 2025
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/141662
No test since there appears to be disabled by default and there
is no test coverage using -enable-arm-3-addr-conv
>From 9a8bb50a324c5388b50f4ee33d334347f0d68c7a Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Mon, 3 Feb 2025 14:00:38 +0700
Subject: [PATCH] ARM: Fix losing subregisters in convertToThreeAddress
No test since there appears to be disabled by default and there
is no test coverage using -enable-arm-3-addr-conv
---
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 69bc84a6733c0..beac0610ca4d7 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -227,7 +227,7 @@ ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
return nullptr;
UpdateMI = BuildMI(MF, MI.getDebugLoc(),
get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
- .addReg(BaseReg)
+ .addReg(BaseReg, 0, Base.getSubReg())
.addImm(Amt)
.add(predOps(Pred))
.add(condCodeOp());
@@ -236,8 +236,8 @@ ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
UpdateMI = BuildMI(MF, MI.getDebugLoc(),
get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
- .addReg(BaseReg)
- .addReg(OffReg)
+ .addReg(BaseReg, 0, Base.getSubReg())
+ .addReg(OffReg, 0, Offset.getSubReg())
.addReg(0)
.addImm(SOOpc)
.add(predOps(Pred))
@@ -245,8 +245,8 @@ ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
} else
UpdateMI = BuildMI(MF, MI.getDebugLoc(),
get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
- .addReg(BaseReg)
- .addReg(OffReg)
+ .addReg(BaseReg, 0, Base.getSubReg())
+ .addReg(OffReg, 0, Offset.getSubReg())
.add(predOps(Pred))
.add(condCodeOp());
break;
@@ -258,15 +258,15 @@ ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
// Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
UpdateMI = BuildMI(MF, MI.getDebugLoc(),
get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
- .addReg(BaseReg)
+ .addReg(BaseReg, 0, Base.getSubReg())
.addImm(Amt)
.add(predOps(Pred))
.add(condCodeOp());
else
UpdateMI = BuildMI(MF, MI.getDebugLoc(),
get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
- .addReg(BaseReg)
- .addReg(OffReg)
+ .addReg(BaseReg, 0, Base.getSubReg())
+ .addReg(OffReg, 0, Offset.getSubReg())
.add(predOps(Pred))
.add(condCodeOp());
break;
@@ -278,13 +278,13 @@ ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
if (isLoad)
MemMI =
BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
- .addReg(WBReg)
+ .addReg(WBReg, 0, WB.getSubReg())
.addImm(0)
.addImm(Pred);
else
MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
.addReg(MI.getOperand(1).getReg())
- .addReg(WBReg)
+ .addReg(WBReg, 0, WB.getSubReg())
.addReg(0)
.addImm(0)
.addImm(Pred);
@@ -294,13 +294,13 @@ ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
if (isLoad)
MemMI =
BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
- .addReg(BaseReg)
+ .addReg(BaseReg, 0, Base.getSubReg())
.addImm(0)
.addImm(Pred);
else
MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
.addReg(MI.getOperand(1).getReg())
- .addReg(BaseReg)
+ .addReg(BaseReg, 0, Base.getSubReg())
.addReg(0)
.addImm(0)
.addImm(Pred);
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