[llvm] [AArch64][SelectionDAG] Add type legalization for partial reduce wide adds (PR #141075)

[Sander de Smalen via llvm-commits]

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@@ -29530,6 +29537,7 @@ AArch64TargetLowering::LowerPARTIAL_REDUCE_MLA(SDValue Op,
   SDValue LHS = Op.getOperand(1);
   SDValue RHS = Op.getOperand(2);
   EVT ResultVT = Op.getValueType();
+
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sdesmalen-arm wrote:

nit: unnecessary newline.

https://github.com/llvm/llvm-project/pull/141075