[llvm] [RISCV][FPEnv] Lowering of fpenv intrinsics (PR #141498)
Serge Pavlov via llvm-commits
llvm-commits at lists.llvm.org
Tue May 27 09:17:24 PDT 2025
https://github.com/spavloff updated https://github.com/llvm/llvm-project/pull/141498
>From 178b8bb2e8f438e4fedcc7b490b9e0dcdb85d99b Mon Sep 17 00:00:00 2001
From: Serge Pavlov <sepavloff at gmail.com>
Date: Mon, 26 May 2025 15:09:58 +0700
Subject: [PATCH 1/3] [RISCV][FPEnv] Lowering of fpenv intrinsics
The change implements custom lowering of `get_fpenv`, `set_fpenv` and
`reset_fpenv` for RISCV target.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 ++
llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 11 +++++++
llvm/test/CodeGen/RISCV/fpenv32.ll | 33 +++++++++++++++++++++
llvm/test/CodeGen/RISCV/fpenv64.ll | 33 +++++++++++++++++++++
4 files changed, 80 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/fpenv32.ll
create mode 100644 llvm/test/CodeGen/RISCV/fpenv64.ll
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0a849f49116ee..b4f8038041e78 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -649,6 +649,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::GET_ROUNDING, XLenVT, Custom);
setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
+ setOperationAction(ISD::GET_FPENV, XLenVT, Legal);
+ setOperationAction(ISD::SET_FPENV, XLenVT, Legal);
+ setOperationAction(ISD::RESET_FPENV, MVT::Other, Legal);
}
setOperationAction({ISD::GlobalAddress, ISD::BlockAddress, ISD::ConstantPool,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 84a75666e5f36..9edfe34e0b67b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -736,6 +736,17 @@ def : LdPat<load, LW_INX, f32>;
def : StPat<store, SW_INX, GPRF32, f32>;
} // Predicates = [HasStdExtZfinx]
+/// Floating-point environment
+multiclass FPEnvironmentOps<Predicate HasFloatExt> {
+ let Predicates = [HasFloatExt] in {
+ def : Pat<(XLenVT (get_fpenv)), (CSRRS SysRegFCSR.Encoding, (XLenVT X0))>;
+ def : Pat<(set_fpenv (XLenVT GPR:$rs)), (CSRRW SysRegFCSR.Encoding, GPR:$rs)>;
+ def : Pat<(reset_fpenv), (CSRRW SysRegFCSR.Encoding, (XLenVT X0))>;
+ }
+}
+defm : FPEnvironmentOps<HasStdExtF>;
+defm : FPEnvironmentOps<HasStdExtZfinx>;
+
let Predicates = [HasStdExtF, IsRV32] in {
// Moves (no conversion)
def : Pat<(bitconvert (i32 GPR:$rs1)), (FMV_W_X GPR:$rs1)>;
diff --git a/llvm/test/CodeGen/RISCV/fpenv32.ll b/llvm/test/CodeGen/RISCV/fpenv32.ll
new file mode 100644
index 0000000000000..4d4976d391f80
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/fpenv32.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s | FileCheck %s
+
+define i32 @func_get_fpenv() {
+; CHECK-LABEL: func_get_fpenv:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: frcsr a0
+; CHECK-NEXT: ret
+entry:
+ %fpenv = call i32 @llvm.get.fpenv.i32()
+ ret i32 %fpenv
+}
+
+define void @func_set_fpenv(i32 %fpenv) {
+; CHECK-LABEL: func_set_fpenv:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fscsr a0
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.set.fpenv.i32(i32 %fpenv)
+ ret void
+}
+
+define void @func_reset_fpenv() {
+; CHECK-LABEL: func_reset_fpenv:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fscsr zero
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.reset.fpenv()
+ ret void
+}
diff --git a/llvm/test/CodeGen/RISCV/fpenv64.ll b/llvm/test/CodeGen/RISCV/fpenv64.ll
new file mode 100644
index 0000000000000..3a7a455c3eed1
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/fpenv64.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s | FileCheck %s
+
+define i64 @func_get_fpenv() {
+; CHECK-LABEL: func_get_fpenv:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: frcsr a0
+; CHECK-NEXT: ret
+entry:
+ %fpenv = call i64 @llvm.get.fpenv.i64()
+ ret i64 %fpenv
+}
+
+define void @func_set_fpenv(i64 %fpenv) {
+; CHECK-LABEL: func_set_fpenv:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fscsr a0
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.set.fpenv.i64(i64 %fpenv)
+ ret void
+}
+
+define void @func_reset_fpenv() {
+; CHECK-LABEL: func_reset_fpenv:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fscsr zero
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.reset.fpenv()
+ ret void
+}
>From f3cc23e9b08d9869f7de5c33c9a64521727e4ec0 Mon Sep 17 00:00:00 2001
From: Serge Pavlov <sepavloff at gmail.com>
Date: Tue, 27 May 2025 18:29:58 +0700
Subject: [PATCH 2/3] Address review comments
---
llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 12 +++-----
llvm/test/CodeGen/RISCV/fpenv.ll | 37 ++++++++++++++++++++++--
llvm/test/CodeGen/RISCV/fpenv32.ll | 33 ---------------------
llvm/test/CodeGen/RISCV/fpenv64.ll | 33 ---------------------
4 files changed, 38 insertions(+), 77 deletions(-)
delete mode 100644 llvm/test/CodeGen/RISCV/fpenv32.ll
delete mode 100644 llvm/test/CodeGen/RISCV/fpenv64.ll
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 9edfe34e0b67b..b4b77b639080b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -737,15 +737,11 @@ def : StPat<store, SW_INX, GPRF32, f32>;
} // Predicates = [HasStdExtZfinx]
/// Floating-point environment
-multiclass FPEnvironmentOps<Predicate HasFloatExt> {
- let Predicates = [HasFloatExt] in {
- def : Pat<(XLenVT (get_fpenv)), (CSRRS SysRegFCSR.Encoding, (XLenVT X0))>;
- def : Pat<(set_fpenv (XLenVT GPR:$rs)), (CSRRW SysRegFCSR.Encoding, GPR:$rs)>;
- def : Pat<(reset_fpenv), (CSRRW SysRegFCSR.Encoding, (XLenVT X0))>;
- }
+let Predicates = [HasStdExtFOrZfinx] in {
+def : Pat<(XLenVT (get_fpenv)), (CSRRS SysRegFCSR.Encoding, (XLenVT X0))>;
+def : Pat<(set_fpenv (XLenVT GPR:$rs)), (CSRRW SysRegFCSR.Encoding, GPR:$rs)>;
+def : Pat<(reset_fpenv), (CSRRW SysRegFCSR.Encoding, (XLenVT X0))>;
}
-defm : FPEnvironmentOps<HasStdExtF>;
-defm : FPEnvironmentOps<HasStdExtZfinx>;
let Predicates = [HasStdExtF, IsRV32] in {
// Moves (no conversion)
diff --git a/llvm/test/CodeGen/RISCV/fpenv.ll b/llvm/test/CodeGen/RISCV/fpenv.ll
index 11e104a290e1b..28efcad4d03b6 100644
--- a/llvm/test/CodeGen/RISCV/fpenv.ll
+++ b/llvm/test/CodeGen/RISCV/fpenv.ll
@@ -1,6 +1,7 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefix=RV32IF %s
-; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefix=RV64IF %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs | FileCheck %s
define i32 @func_01() {
; RV32IF-LABEL: func_01:
@@ -212,6 +213,36 @@ define void @func_07() {
ret void
}
+define iXLen @func_get_fpenv() {
+; CHECK-LABEL: func_get_fpenv:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: frcsr a0
+; CHECK-NEXT: ret
+entry:
+ %fpenv = call iXLen @llvm.get.fpenv.iXLen()
+ ret iXLen %fpenv
+}
+
+define void @func_set_fpenv(iXLen %fpenv) {
+; CHECK-LABEL: func_set_fpenv:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fscsr a0
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.set.fpenv.iXLen(iXLen %fpenv)
+ ret void
+}
+
+define void @func_reset_fpenv() {
+; CHECK-LABEL: func_reset_fpenv:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fscsr zero
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.reset.fpenv()
+ ret void
+}
+
attributes #0 = { strictfp }
declare void @llvm.set.rounding(i32)
diff --git a/llvm/test/CodeGen/RISCV/fpenv32.ll b/llvm/test/CodeGen/RISCV/fpenv32.ll
deleted file mode 100644
index 4d4976d391f80..0000000000000
--- a/llvm/test/CodeGen/RISCV/fpenv32.ll
+++ /dev/null
@@ -1,33 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s | FileCheck %s
-
-define i32 @func_get_fpenv() {
-; CHECK-LABEL: func_get_fpenv:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: frcsr a0
-; CHECK-NEXT: ret
-entry:
- %fpenv = call i32 @llvm.get.fpenv.i32()
- ret i32 %fpenv
-}
-
-define void @func_set_fpenv(i32 %fpenv) {
-; CHECK-LABEL: func_set_fpenv:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: fscsr a0
-; CHECK-NEXT: ret
-entry:
- call void @llvm.set.fpenv.i32(i32 %fpenv)
- ret void
-}
-
-define void @func_reset_fpenv() {
-; CHECK-LABEL: func_reset_fpenv:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: fscsr zero
-; CHECK-NEXT: ret
-entry:
- call void @llvm.reset.fpenv()
- ret void
-}
diff --git a/llvm/test/CodeGen/RISCV/fpenv64.ll b/llvm/test/CodeGen/RISCV/fpenv64.ll
deleted file mode 100644
index 3a7a455c3eed1..0000000000000
--- a/llvm/test/CodeGen/RISCV/fpenv64.ll
+++ /dev/null
@@ -1,33 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s | FileCheck %s
-
-define i64 @func_get_fpenv() {
-; CHECK-LABEL: func_get_fpenv:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: frcsr a0
-; CHECK-NEXT: ret
-entry:
- %fpenv = call i64 @llvm.get.fpenv.i64()
- ret i64 %fpenv
-}
-
-define void @func_set_fpenv(i64 %fpenv) {
-; CHECK-LABEL: func_set_fpenv:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: fscsr a0
-; CHECK-NEXT: ret
-entry:
- call void @llvm.set.fpenv.i64(i64 %fpenv)
- ret void
-}
-
-define void @func_reset_fpenv() {
-; CHECK-LABEL: func_reset_fpenv:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: fscsr zero
-; CHECK-NEXT: ret
-entry:
- call void @llvm.reset.fpenv()
- ret void
-}
>From 31f476c7be64ca65c83c576472c5bedd62b6a624 Mon Sep 17 00:00:00 2001
From: Serge Pavlov <sepavloff at gmail.com>
Date: Tue, 27 May 2025 16:12:28 +0000
Subject: [PATCH 3/3] Move tests to a separate file to avoid bloating fpenv.ll
---
llvm/test/CodeGen/RISCV/fpenv-xlen.ll | 35 +++++++++++++++++++++++++
llvm/test/CodeGen/RISCV/fpenv.ll | 37 +++------------------------
2 files changed, 38 insertions(+), 34 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/fpenv-xlen.ll
diff --git a/llvm/test/CodeGen/RISCV/fpenv-xlen.ll b/llvm/test/CodeGen/RISCV/fpenv-xlen.ll
new file mode 100644
index 0000000000000..90d6ace923c3d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/fpenv-xlen.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs | FileCheck %s
+
+define iXLen @func_get_fpenv() {
+; CHECK-LABEL: func_get_fpenv:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: frcsr a0
+; CHECK-NEXT: ret
+entry:
+ %fpenv = call iXLen @llvm.get.fpenv.iXLen()
+ ret iXLen %fpenv
+}
+
+define void @func_set_fpenv(iXLen %fpenv) {
+; CHECK-LABEL: func_set_fpenv:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fscsr a0
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.set.fpenv.iXLen(iXLen %fpenv)
+ ret void
+}
+
+define void @func_reset_fpenv() {
+; CHECK-LABEL: func_reset_fpenv:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fscsr zero
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.reset.fpenv()
+ ret void
+}
diff --git a/llvm/test/CodeGen/RISCV/fpenv.ll b/llvm/test/CodeGen/RISCV/fpenv.ll
index 28efcad4d03b6..11e104a290e1b 100644
--- a/llvm/test/CodeGen/RISCV/fpenv.ll
+++ b/llvm/test/CodeGen/RISCV/fpenv.ll
@@ -1,7 +1,6 @@
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs | FileCheck %s
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs | FileCheck %s
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs | FileCheck %s
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefix=RV64IF %s
define i32 @func_01() {
; RV32IF-LABEL: func_01:
@@ -213,36 +212,6 @@ define void @func_07() {
ret void
}
-define iXLen @func_get_fpenv() {
-; CHECK-LABEL: func_get_fpenv:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: frcsr a0
-; CHECK-NEXT: ret
-entry:
- %fpenv = call iXLen @llvm.get.fpenv.iXLen()
- ret iXLen %fpenv
-}
-
-define void @func_set_fpenv(iXLen %fpenv) {
-; CHECK-LABEL: func_set_fpenv:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: fscsr a0
-; CHECK-NEXT: ret
-entry:
- call void @llvm.set.fpenv.iXLen(iXLen %fpenv)
- ret void
-}
-
-define void @func_reset_fpenv() {
-; CHECK-LABEL: func_reset_fpenv:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: fscsr zero
-; CHECK-NEXT: ret
-entry:
- call void @llvm.reset.fpenv()
- ret void
-}
-
attributes #0 = { strictfp }
declare void @llvm.set.rounding(i32)
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