[llvm] [AArch64][SME] Disable hazard padding when there is only PPRs and GPRs (PR #137817)

[Sander de Smalen via llvm-commits]

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@@ -5074,7 +5083,11 @@ void AArch64FrameLowering::orderFrameObjects(
       if (AFI.hasStackHazardSlotIndex()) {
         std::optional<int> FI = getLdStFrameID(MI, MFI);
         if (FI && *FI >= 0 && *FI < (int)FrameObjects.size()) {
-          if (MFI.getStackID(*FI) == TargetStackID::ScalableVector ||
+          // Note: PPR accesses should be treated as GPR accesses for the
+          // purposes of stack hazards as PPR ld/sts are handled on the CPU.
+          if ((MFI.getStackID(*FI) == TargetStackID::ScalableVector &&
+               (ZPRPPRSPills ||
+                !AArch64::PPRRegClass.contains(MI.getOperand(0).getReg()))) ||
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sdesmalen-arm wrote:

I'm not sure if it's safe to just assume `MI.getOperand(0)` is always a register (especially for stores)

https://github.com/llvm/llvm-project/pull/137817