[llvm] [AArch64][SelectionDAG] Add type legalization for partial reduce wide adds (PR #141075)

[Nicholas Guy via llvm-commits]

================
@@ -29530,6 +29537,35 @@ AArch64TargetLowering::LowerPARTIAL_REDUCE_MLA(SDValue Op,
   SDValue LHS = Op.getOperand(1);
   SDValue RHS = Op.getOperand(2);
   EVT ResultVT = Op.getValueType();
+
+  // Recognise Op as a wide add, if it is then we leave it as-is
+  // Base: nxv2i64, Subdivision: nxv4i32
+  auto IsEVTSubdivision = [](EVT Base, EVT Subdivision) -> bool {
+    assert(Base.isVector() && Subdivision.isVector());
+    assert(Base.isScalableVector() == Subdivision.isScalableVector());
+
+    ElementCount BaseCount = Base.getVectorElementCount();
+    ElementCount SubCount = Subdivision.getVectorElementCount();
+    if (BaseCount * 2 != SubCount)
+      return false;
+
+    uint64_t BaseScalarSize = Base.getScalarSizeInBits();
+    uint64_t SubScalarSize = Subdivision.getScalarSizeInBits();
+    if (BaseScalarSize != SubScalarSize * 2)
+      return false;
+
+    return true;
+  };
+  if (IsEVTSubdivision(ResultVT, LHS.getValueType())) {
----------------
NickGuy-Arm wrote:

The motivating AArch64 instructions for this work are `UADDW`/`UADDW2` (https://developer.arm.com/documentation/ddi0602/2025-03/SIMD-FP-Instructions/UADDW--UADDW2--Unsigned-add-wide-?lang=en) and their signed equivalents `SADDW`/`SADDW2`. As well as the scalable forms; `UADDWB`/`UADDWT` and `SADDWB`/`SADDWT`.

I'll add a comment mentioning this when I get around to addressing the rest of the comments on this PR.

https://github.com/llvm/llvm-project/pull/141075