[llvm] [SelectionDAG][AArch64] Add dot product lowering in NEON for PARTIAL_REDUCE_*MLA ISD nodes (PR #140075)

[Nicholas Guy via llvm-commits]

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@@ -27569,6 +27576,12 @@ void AArch64TargetLowering::ReplaceNodeResults(
     if (SDValue Res = LowerVECTOR_COMPRESS(SDValue(N, 0), DAG))
       Results.push_back(Res);
     return;
+  case ISD::PARTIAL_REDUCE_UMLA:
+  case ISD::PARTIAL_REDUCE_SMLA: {
+    if (SDValue Res = LowerPARTIAL_REDUCE_MLA(SDValue(N, 0), DAG))
+      Results.push_back(Res);
+    return;
+  }
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NickGuy-Arm wrote:

It definitely was at one point in history, to support the v16i8 -> v4i64 cases. But as we're now handling that differently (by splitting the accumulator into v2i64) this code is never hit with the current test cases. Removed.

https://github.com/llvm/llvm-project/pull/140075