[llvm] [SelectionDAG][AArch64] Add dot product lowering in NEON for PARTIAL_REDUCE_*MLA ISD nodes (PR #140075)

[Nicholas Guy via llvm-commits]

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@@ -1451,8 +1451,16 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     for (MVT VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
       setOperationAction(ISD::ADD, VT, Custom);
     // FADDP custom lowering
-    for (MVT VT : { MVT::v16f16, MVT::v8f32, MVT::v4f64 })
+    for (MVT VT : {MVT::v16f16, MVT::v8f32, MVT::v4f64})
       setOperationAction(ISD::FADD, VT, Custom);
+
+    if (EnablePartialReduceNodes && Subtarget->hasDotProd()) {
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NickGuy-Arm wrote:

It is not, partial reduction intrinsics are currently lowered down a generic path. The `EnablePartialReduceNodes` flag guards the new lowering path, which is intended to become the default when it is deemed complete.
I believe the `EnablePartialReduceNodes` does influence whether the intrinsic is lowered to the ISD::PARTIAL_REDUCE_* nodes, however.

https://github.com/llvm/llvm-project/pull/140075