[llvm] [LoongArch] Fix assertion failure in performORCombine (PR #141586)

[via llvm-commits]

https://github.com/heiher created https://github.com/llvm/llvm-project/pull/141586

Fixes #141583

>From 00944f9d2b8503028b3cc663e38bbccec12823ab Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui at loongson.cn>
Date: Tue, 27 May 2025 20:07:24 +0800
Subject: [PATCH] [LoongArch] Fix assertion failure in performORCombine

Fixes #141583
---
 llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp |  2 +-
 llvm/test/CodeGen/LoongArch/bstrins_w.ll            | 12 ++++++++++++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 9f5c94ddea44f..7a9ec9f5e96b3 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -4410,7 +4410,7 @@ static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
     LLVM_DEBUG(dbgs() << "Perform OR combine: match pattern 5\n");
     return DAG.getNode(
         LoongArchISD::BSTRINS, DL, ValTy, N0.getOperand(0),
-        DAG.getConstant(CN1->getSExtValue() >> MaskIdx0, DL, ValTy),
+        DAG.getSignedConstant(CN1->getSExtValue() >> MaskIdx0, DL, ValTy),
         DAG.getConstant(ValBits == 32 ? (MaskIdx0 + (MaskLen0 & 31) - 1)
                                       : (MaskIdx0 + MaskLen0 - 1),
                         DL, GRLenVT),
diff --git a/llvm/test/CodeGen/LoongArch/bstrins_w.ll b/llvm/test/CodeGen/LoongArch/bstrins_w.ll
index c59f15bd64112..0fea0470394d2 100644
--- a/llvm/test/CodeGen/LoongArch/bstrins_w.ll
+++ b/llvm/test/CodeGen/LoongArch/bstrins_w.ll
@@ -207,6 +207,18 @@ define i32 @pat8(i32 %c) nounwind {
   ret i32 %or
 }
 
+define i32 @pat9(i32 %a) {
+; CHECK-LABEL: pat9:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lu12i.w $a1, -8
+; CHECK-NEXT:    ori $a1, $a1, 564
+; CHECK-NEXT:    bstrins.w $a0, $a1, 31, 16
+; CHECK-NEXT:    ret
+  %and = and i32 %a, 65535       ; 0x0000ffff
+  %or = or i32 %and, -2110521344 ; 0x82340000
+  ret i32 %or
+}
+
 ;; Test that bstrins.w is not generated because constant OR operand
 ;; doesn't fit into bits cleared by constant AND operand.
 define i32 @no_bstrins_w(i32 %a) nounwind {