[llvm] [AArch64][SelectionDAG] Add type legalization for partial reduce wide adds (PR #141075)

[Sander de Smalen via llvm-commits]

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@@ -1870,6 +1870,13 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv16i8, Legal);
 
     setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv16i8, Custom);
+
+    // Wide add types
+    if (Subtarget->hasSVE2() || Subtarget->hasSME()) {
+      setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv4i32, Custom);
+      setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv8i16, Custom);
+      setPartialReduceMLAAction(MVT::nxv8i16, MVT::nxv16i8, Custom);
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sdesmalen-arm wrote:

You can mark these as legal and handle all cases with patterns (see my other suggestion). This would remove the need for the code you have in `LowerPARTIAL_REDUCE_MLA`.

https://github.com/llvm/llvm-project/pull/141075