[llvm] [WIP][SDAG] Add partial_reduce_sumla node (PR #141267)

[Paul Walker via llvm-commits]

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@@ -1874,8 +1874,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
   if (EnablePartialReduceNodes && Subtarget->isSVEorStreamingSVEAvailable()) {
     // Mark known legal pairs as 'Legal' (these will expand to UDOT or SDOT).
     // Other pairs will default to 'Expand'.
-    setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv8i16, Legal);
-    setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv16i8, Legal);
+    setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv8i16, Custom);
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paulwalker-arm wrote:

Just throwing this out there but perhaps change it to `setReduceAction(Opcode, ResultType, OperandType)`? to make it easier to add more reductions in the future. This might also be a way to relax the result type requirements  of the current `VECREDUCE_***` nodes.

https://github.com/llvm/llvm-project/pull/141267