[llvm] 8fe33a0 - [NFC] Fix evaluation order dependency in call arguments (#141366)

[via llvm-commits]

Author: Michael Jabbour
Date: 2025-05-27T09:37:52+01:00
New Revision: 8fe33a05b94d716830f7ad119d2afcb06e09cc4d

URL: https://github.com/llvm/llvm-project/commit/8fe33a05b94d716830f7ad119d2afcb06e09cc4d
DIFF: https://github.com/llvm/llvm-project/commit/8fe33a05b94d716830f7ad119d2afcb06e09cc4d.diff

LOG: [NFC] Fix evaluation order dependency in call arguments (#141366)

The code in `ARMAsmParser::parseDirectiveReq` passes both
`parseRegister(Reg, SRegLoc, ERegLoc)` and `SRegLoc` as arguments to
`check()`. Since function arguments are indeterminately sequenced per
C++17 [expr.call]/5, a compiler can evaluate `SRegLoc` before
`parseRegister()` executes. This means `check()` receives a null
location instead of the actual parsed source location for error
reporting.

The fix separates the calls to establish explicit sequencing, ensuring
`check()` receives the correct source location.

This issue was detected by [the CFamily analyzer for
SonarQube](https://www.sonarsource.com/knowledge/languages/cpp/). I'm
happy to provide any additional information or clarification as needed.

Added: 
    

Modified: 
    llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 8c7a65a0355a0..19c417b2c6e9b 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -11787,9 +11787,8 @@ bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
   Parser.Lex(); // Eat the '.req' token.
   MCRegister Reg;
   SMLoc SRegLoc, ERegLoc;
-  if (check(parseRegister(Reg, SRegLoc, ERegLoc), SRegLoc,
-            "register name expected") ||
-      parseEOL())
+  const bool parseResult = parseRegister(Reg, SRegLoc, ERegLoc);
+  if (check(parseResult, SRegLoc, "register name expected") || parseEOL())
     return true;
 
   if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg)