[llvm] [RISCV] Add compress pattern for Xqcilb QC_E_J/JAL to JAL (PR #141561)

[Sudharsan Veeravalli via llvm-commits]

https://github.com/svs-quic created https://github.com/llvm/llvm-project/pull/141561

None

>From d13d6bfada36acf0509d4e560e8851af315c8e5c Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: Tue, 27 May 2025 13:44:15 +0530
Subject: [PATCH] [RISCV] Add compress pattern for Xqcilb QC_E_J/JAL to JAL

---
 llvm/lib/Target/RISCV/RISCVInstrInfo.td     |  3 ++-
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td |  4 ++++
 llvm/test/MC/RISCV/xqcilb-valid.s           | 14 ++++++++++++++
 3 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 9058934557b54..de424b3be852b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -379,7 +379,8 @@ def Simm21Lsb0JALAsmOperand : BareSImmNLsb0AsmOperand<21> {
 }
 
 // A 21-bit signed immediate where the least significant bit is zero.
-def simm21_lsb0_jal : Operand<OtherVT> {
+def simm21_lsb0_jal : Operand<OtherVT>,
+                      ImmLeaf<XLenVT, [{return isShiftedInt<20, 1>(Imm);}]>  {
   let ParserMatchClass = Simm21Lsb0JALAsmOperand;
   let PrintMethod = "printBranchOperand";
   let EncoderMethod = "getImmOpValueAsrN<1>";
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index c4d6d2d704526..f52d21c5299d2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1514,6 +1514,10 @@ def : CompressPat<(QC_E_J bare_simm12_lsb0:$offset),
                   (C_J bare_simm12_lsb0:$offset)>;
 def : CompressPat<(QC_E_JAL bare_simm12_lsb0:$offset),
                   (C_JAL bare_simm12_lsb0:$offset)>;
+def : CompressPat<(QC_E_JAL simm21_lsb0_jal:$offset),
+                  (JAL X1, simm21_lsb0_jal:$offset)>;
+def : CompressPat<(QC_E_J simm21_lsb0_jal:$offset),
+                  (JAL X0, simm21_lsb0_jal:$offset)>;
 } // isCompressOnly = true, Predicates = [HasVendorXqcilb, IsRV32]
 
 let Predicates = [HasVendorXqcili, IsRV32] in {
diff --git a/llvm/test/MC/RISCV/xqcilb-valid.s b/llvm/test/MC/RISCV/xqcilb-valid.s
index 4653bfe958772..3d5b3891ddff6 100644
--- a/llvm/test/MC/RISCV/xqcilb-valid.s
+++ b/llvm/test/MC/RISCV/xqcilb-valid.s
@@ -35,3 +35,17 @@ qc.e.jal 0xffffff8c
 # CHECK-OBJ-ALIAS: j 0x40e
 # CHECK-ENC: encoding: [0x01,0xa1]
 qc.e.j 1024
+
+# CHECK-NOALIAS: jal ra, 3000
+# CHECK-ALIAS: jal 3000
+# CHECK-OBJ-NOALIAS: jal ra, 0xbc8
+# CHECK-OBJ-ALIAS: jal 0xbc8
+# CHECK-ENC: encoding: [0xef,0x00,0x90,0x3b]
+qc.e.jal 3000
+
+# CHECK-NOALIAS: jal zero, -3000
+# CHECK-ALIAS: j -3000
+# CHECK-OBJ-NOALIAS: jal zero, 0xfffff45c
+# CHECK-OBJ-ALIAS: j 0xfffff45c
+# CHECK-ENC: encoding: [0x6f,0xf0,0x8f,0xc4]
+qc.e.j -3000