[llvm] [SelectionDAG][AArch64] Add dot product lowering in NEON for PARTIAL_REDUCE_*MLA ISD nodes (PR #140075)

[Sander de Smalen via llvm-commits]

================
@@ -1451,8 +1451,16 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     for (MVT VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
       setOperationAction(ISD::ADD, VT, Custom);
     // FADDP custom lowering
-    for (MVT VT : { MVT::v16f16, MVT::v8f32, MVT::v4f64 })
+    for (MVT VT : {MVT::v16f16, MVT::v8f32, MVT::v4f64})
       setOperationAction(ISD::FADD, VT, Custom);
+
+    if (EnablePartialReduceNodes && Subtarget->hasDotProd()) {
+      setPartialReduceMLAAction(MVT::v2i64, MVT::v8i16, Legal);
----------------
sdesmalen-arm wrote:

One more thing; I don't think this one is legal (the neon udot/sdot instructions only support i8 -> i32).

I guess this case is missing test coverage, because the following would fail to compile:

```
define <2 x i64> @foo(<2 x i64> %acc, <8 x i16> %input){
entry:
    %input.wide = zext <8 x i16> %input to <8 x i64>
    %partial.reduce = tail call <2 x i64> @llvm.experimental.vector.partial.reduce.add(<2 x i64> %acc, <8 x i64> %input.wide)
    ret <2 x i64> %partial.reduce
}
```

https://github.com/llvm/llvm-project/pull/140075