[llvm] [AArch64][GlobalISel] Add push_mul_through_s/zext (PR #141551)

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git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
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diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index ee935aa60..26e99ac93 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -248,7 +248,8 @@ bool matchExtAddvToUdotAddv(MachineInstr &MI, MachineRegisterInfo &MRI,
     return false;
 
   // Detect mul(ext, ext) with symetric ext's. If I1Opc is G_ZEXT or G_SEXT then
-  // the ext's must match the same opcode. It is set to the ext opcode on output.
+  // the ext's must match the same opcode. It is set to the ext opcode on
+  // output.
   auto tryMatchingMulOfExt = [&MRI](MachineInstr *MI, Register &Out1,
                                     Register &Out2, unsigned &I1Opc) {
     // If result of this has more than 1 use, then there is no point in creating
@@ -579,9 +580,9 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
   MI.eraseFromParent();
 }
 
-// Pushes ADD/SUB/MUL through extend instructions to decrease the number of extend
-// instruction at the end by allowing selection of {s|u}addl sooner
-// i32 add(i32 ext i8, i32 ext i8) => i32 ext(i16 add(i16 ext i8, i16 ext i8))
+// Pushes ADD/SUB/MUL through extend instructions to decrease the number of
+// extend instruction at the end by allowing selection of {s|u}addl sooner i32
+// add(i32 ext i8, i32 ext i8) => i32 ext(i16 add(i16 ext i8, i16 ext i8))
 bool matchPushAddSubExt(MachineInstr &MI, MachineRegisterInfo &MRI,
                         Register DstReg, Register SrcReg1, Register SrcReg2) {
   assert((MI.getOpcode() == TargetOpcode::G_ADD ||

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https://github.com/llvm/llvm-project/pull/141551