[llvm] c4848fa - [RISCV] Remove the declarations for xandesvpackfph LLVM IR intrinsics. NFC.
Jim Lin via llvm-commits
llvm-commits at lists.llvm.org
Mon May 26 22:05:39 PDT 2025
Author: Jim Lin
Date: 2025-05-27T12:53:38+08:00
New Revision: c4848fa1fffd5ddf8a5a85b3cf6ae2381be36a2c
URL: https://github.com/llvm/llvm-project/commit/c4848fa1fffd5ddf8a5a85b3cf6ae2381be36a2c
DIFF: https://github.com/llvm/llvm-project/commit/c4848fa1fffd5ddf8a5a85b3cf6ae2381be36a2c.diff
LOG: [RISCV] Remove the declarations for xandesvpackfph LLVM IR intrinsics. NFC.
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/xandesvpackfph-vfpmadb.ll
llvm/test/CodeGen/RISCV/rvv/xandesvpackfph-vfpmadt.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/xandesvpackfph-vfpmadb.ll b/llvm/test/CodeGen/RISCV/rvv/xandesvpackfph-vfpmadb.ll
index feceacd90e5f0..bddd7719d728f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/xandesvpackfph-vfpmadb.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/xandesvpackfph-vfpmadb.ll
@@ -4,12 +4,6 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+xandesvpackfph \
; RUN: -verify-machineinstrs -target-abi=lp64f | FileCheck %s
-declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32(
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- float,
- iXLen, iXLen);
-
define <vscale x 1 x half> @intrinsic_vfpmadb_vf_nxv1f16_nxv1f16_f32(<vscale x 1 x half> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv1f16_nxv1f16_f32:
; CHECK: # %bb.0: # %entry
@@ -27,13 +21,6 @@ entry:
ret <vscale x 1 x half> %a
}
-declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32(
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- float,
- <vscale x 1 x i1>,
- iXLen, iXLen, iXLen);
-
define <vscale x 1 x half> @intrinsic_vfpmadb_mask_vf_nxv1f16_nxv1f16_f32(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv1f16_nxv1f16_f32:
; CHECK: # %bb.0: # %entry
@@ -53,12 +40,6 @@ entry:
ret <vscale x 1 x half> %a
}
-declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32(
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- float,
- iXLen, iXLen);
-
define <vscale x 2 x half> @intrinsic_vfpmadb_vf_nxv2f16_nxv2f16_f32(<vscale x 2 x half> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv2f16_nxv2f16_f32:
; CHECK: # %bb.0: # %entry
@@ -76,13 +57,6 @@ entry:
ret <vscale x 2 x half> %a
}
-declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32(
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- float,
- <vscale x 2 x i1>,
- iXLen, iXLen, iXLen);
-
define <vscale x 2 x half> @intrinsic_vfpmadb_mask_vf_nxv2f16_nxv2f16_f32(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv2f16_nxv2f16_f32:
; CHECK: # %bb.0: # %entry
@@ -102,12 +76,6 @@ entry:
ret <vscale x 2 x half> %a
}
-declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32(
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- float,
- iXLen, iXLen);
-
define <vscale x 4 x half> @intrinsic_vfpmadb_vf_nxv4f16_nxv4f16_f32(<vscale x 4 x half> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv4f16_nxv4f16_f32:
; CHECK: # %bb.0: # %entry
@@ -125,13 +93,6 @@ entry:
ret <vscale x 4 x half> %a
}
-declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32(
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- float,
- <vscale x 4 x i1>,
- iXLen, iXLen, iXLen);
-
define <vscale x 4 x half> @intrinsic_vfpmadb_mask_vf_nxv4f16_nxv4f16_f32(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv4f16_nxv4f16_f32:
; CHECK: # %bb.0: # %entry
@@ -151,12 +112,6 @@ entry:
ret <vscale x 4 x half> %a
}
-declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32(
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- float,
- iXLen, iXLen);
-
define <vscale x 8 x half> @intrinsic_vfpmadb_vf_nxv8f16_nxv8f16_f32(<vscale x 8 x half> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv8f16_nxv8f16_f32:
; CHECK: # %bb.0: # %entry
@@ -174,13 +129,6 @@ entry:
ret <vscale x 8 x half> %a
}
-declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.mask.nxv8f16.f32(
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- float,
- <vscale x 8 x i1>,
- iXLen, iXLen, iXLen);
-
define <vscale x 8 x half> @intrinsic_vfpmadb_mask_vf_nxv8f16_nxv8f16_f32(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv8f16_nxv8f16_f32:
; CHECK: # %bb.0: # %entry
@@ -200,12 +148,6 @@ entry:
ret <vscale x 8 x half> %a
}
-declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32(
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- float,
- iXLen, iXLen);
-
define <vscale x 16 x half> @intrinsic_vfpmadb_vf_nxv16f16_nxv16f16_f32(<vscale x 16 x half> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv16f16_nxv16f16_f32:
; CHECK: # %bb.0: # %entry
@@ -223,13 +165,6 @@ entry:
ret <vscale x 16 x half> %a
}
-declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.mask.nxv16f16.f32(
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- float,
- <vscale x 16 x i1>,
- iXLen, iXLen, iXLen);
-
define <vscale x 16 x half> @intrinsic_vfpmadb_mask_vf_nxv16f16_nxv16f16_f32(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv16f16_nxv16f16_f32:
; CHECK: # %bb.0: # %entry
@@ -249,12 +184,6 @@ entry:
ret <vscale x 16 x half> %a
}
-declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32(
- <vscale x 32 x half>,
- <vscale x 32 x half>,
- float,
- iXLen, iXLen);
-
define <vscale x 32 x half> @intrinsic_vfpmadb_vf_nxv32f16_nxv32f16_f32(<vscale x 32 x half> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv32f16_nxv32f16_f32:
; CHECK: # %bb.0: # %entry
@@ -272,13 +201,6 @@ entry:
ret <vscale x 32 x half> %a
}
-declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.mask.nxv32f16.f32(
- <vscale x 32 x half>,
- <vscale x 32 x half>,
- float,
- <vscale x 32 x i1>,
- iXLen, iXLen, iXLen);
-
define <vscale x 32 x half> @intrinsic_vfpmadb_mask_vf_nxv32f16_nxv32f16_f32(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv32f16_nxv32f16_f32:
; CHECK: # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/RISCV/rvv/xandesvpackfph-vfpmadt.ll b/llvm/test/CodeGen/RISCV/rvv/xandesvpackfph-vfpmadt.ll
index e9d78d2d8b5f5..c920c710f6125 100644
--- a/llvm/test/CodeGen/RISCV/rvv/xandesvpackfph-vfpmadt.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/xandesvpackfph-vfpmadt.ll
@@ -4,12 +4,6 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+xandesvpackfph \
; RUN: -verify-machineinstrs -target-abi=lp64f | FileCheck %s
-declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32(
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- float,
- iXLen, iXLen);
-
define <vscale x 1 x half> @intrinsic_vfpmadt_vf_nxv1f16_nxv1f16_f32(<vscale x 1 x half> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfpmadt_vf_nxv1f16_nxv1f16_f32:
; CHECK: # %bb.0: # %entry
@@ -27,13 +21,6 @@ entry:
ret <vscale x 1 x half> %a
}
-declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32(
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- float,
- <vscale x 1 x i1>,
- iXLen, iXLen, iXLen);
-
define <vscale x 1 x half> @intrinsic_vfpmadt_mask_vf_nxv1f16_nxv1f16_f32(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfpmadt_mask_vf_nxv1f16_nxv1f16_f32:
; CHECK: # %bb.0: # %entry
@@ -53,12 +40,6 @@ entry:
ret <vscale x 1 x half> %a
}
-declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32(
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- float,
- iXLen, iXLen);
-
define <vscale x 2 x half> @intrinsic_vfpmadt_vf_nxv2f16_nxv2f16_f32(<vscale x 2 x half> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfpmadt_vf_nxv2f16_nxv2f16_f32:
; CHECK: # %bb.0: # %entry
@@ -76,13 +57,6 @@ entry:
ret <vscale x 2 x half> %a
}
-declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32(
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- float,
- <vscale x 2 x i1>,
- iXLen, iXLen, iXLen);
-
define <vscale x 2 x half> @intrinsic_vfpmadt_mask_vf_nxv2f16_nxv2f16_f32(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfpmadt_mask_vf_nxv2f16_nxv2f16_f32:
; CHECK: # %bb.0: # %entry
@@ -102,12 +76,6 @@ entry:
ret <vscale x 2 x half> %a
}
-declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32(
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- float,
- iXLen, iXLen);
-
define <vscale x 4 x half> @intrinsic_vfpmadt_vf_nxv4f16_nxv4f16_f32(<vscale x 4 x half> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfpmadt_vf_nxv4f16_nxv4f16_f32:
; CHECK: # %bb.0: # %entry
@@ -125,13 +93,6 @@ entry:
ret <vscale x 4 x half> %a
}
-declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32(
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- float,
- <vscale x 4 x i1>,
- iXLen, iXLen, iXLen);
-
define <vscale x 4 x half> @intrinsic_vfpmadt_mask_vf_nxv4f16_nxv4f16_f32(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfpmadt_mask_vf_nxv4f16_nxv4f16_f32:
; CHECK: # %bb.0: # %entry
@@ -151,12 +112,6 @@ entry:
ret <vscale x 4 x half> %a
}
-declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32(
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- float,
- iXLen, iXLen);
-
define <vscale x 8 x half> @intrinsic_vfpmadt_vf_nxv8f16_nxv8f16_f32(<vscale x 8 x half> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfpmadt_vf_nxv8f16_nxv8f16_f32:
; CHECK: # %bb.0: # %entry
@@ -174,13 +129,6 @@ entry:
ret <vscale x 8 x half> %a
}
-declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.mask.nxv8f16.f32(
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- float,
- <vscale x 8 x i1>,
- iXLen, iXLen, iXLen);
-
define <vscale x 8 x half> @intrinsic_vfpmadt_mask_vf_nxv8f16_nxv8f16_f32(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfpmadt_mask_vf_nxv8f16_nxv8f16_f32:
; CHECK: # %bb.0: # %entry
@@ -200,12 +148,6 @@ entry:
ret <vscale x 8 x half> %a
}
-declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32(
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- float,
- iXLen, iXLen);
-
define <vscale x 16 x half> @intrinsic_vfpmadt_vf_nxv16f16_nxv16f16_f32(<vscale x 16 x half> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfpmadt_vf_nxv16f16_nxv16f16_f32:
; CHECK: # %bb.0: # %entry
@@ -223,13 +165,6 @@ entry:
ret <vscale x 16 x half> %a
}
-declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.mask.nxv16f16.f32(
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- float,
- <vscale x 16 x i1>,
- iXLen, iXLen, iXLen);
-
define <vscale x 16 x half> @intrinsic_vfpmadt_mask_vf_nxv16f16_nxv16f16_f32(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfpmadt_mask_vf_nxv16f16_nxv16f16_f32:
; CHECK: # %bb.0: # %entry
@@ -249,12 +184,6 @@ entry:
ret <vscale x 16 x half> %a
}
-declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32(
- <vscale x 32 x half>,
- <vscale x 32 x half>,
- float,
- iXLen, iXLen);
-
define <vscale x 32 x half> @intrinsic_vfpmadt_vf_nxv32f16_nxv32f16_f32(<vscale x 32 x half> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfpmadt_vf_nxv32f16_nxv32f16_f32:
; CHECK: # %bb.0: # %entry
@@ -272,13 +201,6 @@ entry:
ret <vscale x 32 x half> %a
}
-declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.mask.nxv32f16.f32(
- <vscale x 32 x half>,
- <vscale x 32 x half>,
- float,
- <vscale x 32 x i1>,
- iXLen, iXLen, iXLen);
-
define <vscale x 32 x half> @intrinsic_vfpmadt_mask_vf_nxv32f16_nxv32f16_f32(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfpmadt_mask_vf_nxv32f16_nxv32f16_f32:
; CHECK: # %bb.0: # %entry
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