[llvm] [AMDGPU] Support bottom-up postRA scheduing. (PR #135295)

[Carl Ritson via llvm-commits]

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@@ -417,7 +450,41 @@ void GCNHazardRecognizer::AdvanceCycle() {
 }
 
 void GCNHazardRecognizer::RecedeCycle() {
-  llvm_unreachable("hazard recognizer does not support bottom-up scheduling.");
+  // If no instruction was issued this cycle, pop the oldest placeholder.
+  if (!CurrCycleInstr) {
+    if (!EmittedInstrs.empty())
+      EmittedInstrs.pop_back();
+    return;
+  }
+
+  // If this is a bundle header, handle the entire bundle here.
+  if (CurrCycleInstr->isBundle()) {
+    processBundleBottomUp();
+    return;
+  }
+
+  unsigned NumWaitStates = TII.getNumWaitStates(*CurrCycleInstr);
+  if (!NumWaitStates) {
+    CurrCycleInstr = nullptr;
+    return;
+  }
+
+  // Add current instruction to the emitted list.
+  EmittedInstrs.push_back(CurrCycleInstr);
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perlfu wrote:

This sequence of code doesn't make sense.
1. It pushes `CurrCycleInstr` onto the end of `EmittedInstrs`
2. Removes values from the _end_ of `EmittedInstrs`.  This will start by disposing of `CurrCycleInstr`, completely negating the previous operation.
3. Resizes `EmittedInstrs` to `getMaxLookAhead()`.  In most cases `EmittedInstrs` will be 0 or 1 elements in size by this point.  Hence this will expand it with empty elements.

https://github.com/llvm/llvm-project/pull/135295