[llvm] [AMDGPU] Support bottom-up postRA scheduing. (PR #135295)

[Carl Ritson via llvm-commits]

https://github.com/perlfu requested changes to this pull request.

I don't think this change is actually doing what you expect.
Because none of the additional code is having any impact if hazard recognition using `EmittedInstrs` is never used.
If the goal is to allow enabling of bottom up scheduling post-RA on GFX11+ then the only required change is
```
void GCNHazardRecognizer::RecedeCycle() {
  if (IsHazardRecognizerMode || ST.getGeneration() < GFX11)
    llvm_unreachable("hazard recognizer does not support bottom-up scheduling.");
 }
```

I expect if you do only the above you'll find the generated ISA is exactly the same as this change.

To support architectures that rely on the `EmittedInstrs` vector then its state needs to be properly maintained and tests covering targets which rely on its state need to be provided.

https://github.com/llvm/llvm-project/pull/135295