[llvm] [RISCV][FPEnv] Lowering of fpenv intrinsics (PR #141498)

[Jim Lin via llvm-commits]

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@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck %s
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tclin914 wrote:

The codegen of RV32 and RV64 looks almost the same. Can we use sed + iXLen for both RV32 and RV64 like `float-intrinsics.ll ` ?

https://github.com/llvm/llvm-project/pull/141498