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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions h,cpp -- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/lib/Target/PowerPC/PPCInstrInfo.h llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp llvm/lib/Target/PowerPC/PPCRegisterInfo.h
``````````
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<details>
<summary>
View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index 1c7d0f2e9..87a49d907 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -103,69 +103,151 @@ enum PPCMachineCombinerPattern : unsigned {
// Define list of load and store spill opcodes.
#define NoInstr PPC::INSTRUCTION_LIST_END
#define Pwr8LoadOpcodes \
- { \
- PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
- PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \
- PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, NoInstr, NoInstr, \
- PPC::EVLDD, PPC::RESTORE_QUADWORD \
- }
+ {PPC::LWZ, \
+ PPC::LD, \
+ PPC::LFD, \
+ PPC::LFS, \
+ PPC::RESTORE_CR, \
+ PPC::RESTORE_CRBIT, \
+ PPC::LVX, \
+ PPC::LXVD2X, \
+ PPC::LXSDX, \
+ PPC::LXSSPX, \
+ PPC::SPILLTOVSR_LD, \
+ NoInstr, \
+ NoInstr, \
+ NoInstr, \
+ NoInstr, \
+ NoInstr, \
+ PPC::EVLDD, \
+ PPC::RESTORE_QUADWORD}
#define Pwr9LoadOpcodes \
- { \
- PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
- PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
- PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, \
- NoInstr, NoInstr, NoInstr, PPC::RESTORE_QUADWORD \
- }
+ {PPC::LWZ, \
+ PPC::LD, \
+ PPC::LFD, \
+ PPC::LFS, \
+ PPC::RESTORE_CR, \
+ PPC::RESTORE_CRBIT, \
+ PPC::LVX, \
+ PPC::LXV, \
+ PPC::DFLOADf64, \
+ PPC::DFLOADf32, \
+ PPC::SPILLTOVSR_LD, \
+ NoInstr, \
+ NoInstr, \
+ NoInstr, \
+ NoInstr, \
+ NoInstr, \
+ NoInstr, \
+ PPC::RESTORE_QUADWORD}
#define Pwr10LoadOpcodes \
- { \
- PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
- PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
- PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \
- PPC::RESTORE_UACC, NoInstr, NoInstr, NoInstr, PPC::RESTORE_QUADWORD \
- }
+ {PPC::LWZ, \
+ PPC::LD, \
+ PPC::LFD, \
+ PPC::LFS, \
+ PPC::RESTORE_CR, \
+ PPC::RESTORE_CRBIT, \
+ PPC::LVX, \
+ PPC::LXV, \
+ PPC::DFLOADf64, \
+ PPC::DFLOADf32, \
+ PPC::SPILLTOVSR_LD, \
+ PPC::LXVP, \
+ PPC::RESTORE_ACC, \
+ PPC::RESTORE_UACC, \
+ NoInstr, \
+ NoInstr, \
+ NoInstr, \
+ PPC::RESTORE_QUADWORD}
#define FutureLoadOpcodes \
- { \
- PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
- PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
- PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \
- PPC::RESTORE_UACC, PPC::RESTORE_WACC, PPC::RESTORE_DMR, NoInstr, \
- PPC::RESTORE_QUADWORD \
- }
+ {PPC::LWZ, \
+ PPC::LD, \
+ PPC::LFD, \
+ PPC::LFS, \
+ PPC::RESTORE_CR, \
+ PPC::RESTORE_CRBIT, \
+ PPC::LVX, \
+ PPC::LXV, \
+ PPC::DFLOADf64, \
+ PPC::DFLOADf32, \
+ PPC::SPILLTOVSR_LD, \
+ PPC::LXVP, \
+ PPC::RESTORE_ACC, \
+ PPC::RESTORE_UACC, \
+ PPC::RESTORE_WACC, \
+ PPC::RESTORE_DMR, \
+ NoInstr, \
+ PPC::RESTORE_QUADWORD}
#define Pwr8StoreOpcodes \
- { \
- PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
- PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, \
- PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, NoInstr, \
- PPC::EVSTDD, PPC::SPILL_QUADWORD \
- }
+ {PPC::STW, \
+ PPC::STD, \
+ PPC::STFD, \
+ PPC::STFS, \
+ PPC::SPILL_CR, \
+ PPC::SPILL_CRBIT, \
+ PPC::STVX, \
+ PPC::STXVD2X, \
+ PPC::STXSDX, \
+ PPC::STXSSPX, \
+ PPC::SPILLTOVSR_ST, \
+ NoInstr, \
+ NoInstr, \
+ NoInstr, \
+ NoInstr, \
+ NoInstr, \
+ PPC::EVSTDD, \
+ PPC::SPILL_QUADWORD}
#define Pwr9StoreOpcodes \
- { \
- PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
- PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
- PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, NoInstr, \
- NoInstr, PPC::SPILL_QUADWORD \
- }
+ {PPC::STW, \
+ PPC::STD, \
+ PPC::STFD, \
+ PPC::STFS, \
+ PPC::SPILL_CR, \
+ PPC::SPILL_CRBIT, \
+ PPC::STVX, \
+ PPC::STXV, \
+ PPC::DFSTOREf64, \
+ PPC::DFSTOREf32, \
+ PPC::SPILLTOVSR_ST, \
+ NoInstr, \
+ NoInstr, \
+ NoInstr, \
+ NoInstr, \
+ NoInstr, \
+ NoInstr, \
+ PPC::SPILL_QUADWORD}
#define Pwr10StoreOpcodes \
- { \
- PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
- PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
- PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \
- NoInstr, NoInstr, NoInstr, PPC::SPILL_QUADWORD \
- }
+ {PPC::STW, \
+ PPC::STD, \
+ PPC::STFD, \
+ PPC::STFS, \
+ PPC::SPILL_CR, \
+ PPC::SPILL_CRBIT, \
+ PPC::STVX, \
+ PPC::STXV, \
+ PPC::DFSTOREf64, \
+ PPC::DFSTOREf32, \
+ PPC::SPILLTOVSR_ST, \
+ PPC::STXVP, \
+ PPC::SPILL_ACC, \
+ PPC::SPILL_UACC, \
+ NoInstr, \
+ NoInstr, \
+ NoInstr, \
+ PPC::SPILL_QUADWORD}
#define FutureStoreOpcodes \
- { \
- PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
- PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
- PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \
- PPC::SPILL_WACC, PPC::SPILL_DMR, NoInstr, PPC::SPILL_QUADWORD \
- }
+ {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, \
+ PPC::SPILL_CR, PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, \
+ PPC::DFSTOREf64, PPC::DFSTOREf32, PPC::SPILLTOVSR_ST, PPC::STXVP, \
+ PPC::SPILL_ACC, PPC::SPILL_UACC, PPC::SPILL_WACC, PPC::SPILL_DMR, \
+ NoInstr, PPC::SPILL_QUADWORD}
// Initialize arrays for load and store spill opcodes on supported subtargets.
#define StoreOpcodesForSpill \
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index ed760b5d5..45183af0b 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1511,7 +1511,7 @@ void PPCRegisterInfo::lowerQuadwordRestore(MachineBasicBlock::iterator II,
/// lowerDMRSpilling - Generate the code for spilling the DMR register.
void PPCRegisterInfo::lowerDMRSpilling(MachineBasicBlock::iterator II,
- unsigned FrameIndex) const {
+ unsigned FrameIndex) const {
MachineInstr &MI = *II; // SPILL_DMR <SrcReg>, <offset>
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
@@ -1557,7 +1557,7 @@ void PPCRegisterInfo::lowerDMRSpilling(MachineBasicBlock::iterator II,
/// lowerDMRRestore - Generate the code to restore the DMR register.
void PPCRegisterInfo::lowerDMRRestore(MachineBasicBlock::iterator II,
- unsigned FrameIndex) const {
+ unsigned FrameIndex) const {
MachineInstr &MI = *II; // <DestReg> = RESTORE_WACC <offset>
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
@@ -1584,14 +1584,12 @@ void PPCRegisterInfo::lowerDMRRestore(MachineBasicBlock::iterator II,
FrameIndex, IsLittleEndian ? 0 : 96);
// Kill virtual registers (killedRegState::Killed).
- BuildMI(MBB, II, DL,
- TII.get(PPC::DMXXINSTDMR512_HI),
+ BuildMI(MBB, II, DL, TII.get(PPC::DMXXINSTDMR512_HI),
TargetRegisterInfo::getSubReg(DestReg, PPC::sub_wacc_hi))
.addReg(VSRpReg2, RegState::Kill)
.addReg(VSRpReg3, RegState::Kill);
- BuildMI(MBB, II, DL,
- TII.get(PPC::DMXXINSTDMR512),
+ BuildMI(MBB, II, DL, TII.get(PPC::DMXXINSTDMR512),
TargetRegisterInfo::getSubReg(DestReg, PPC::sub_wacc_lo))
.addReg(VSRpReg0, RegState::Kill)
.addReg(VSRpReg1, RegState::Kill);
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
index 7b6cab72e..4b66ece53 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -152,9 +152,9 @@ public:
unsigned FrameIndex) const;
void lowerDMRSpilling(MachineBasicBlock::iterator II,
- unsigned FrameIndex) const;
- void lowerDMRRestore(MachineBasicBlock::iterator II,
unsigned FrameIndex) const;
+ void lowerDMRRestore(MachineBasicBlock::iterator II,
+ unsigned FrameIndex) const;
static void emitAccCopyInfo(MachineBasicBlock &MBB, MCRegister DestReg,
MCRegister SrcReg);
``````````
</details>
https://github.com/llvm/llvm-project/pull/141530