[llvm] [IR] Consolidate OneNthElements IIT descriptors. NFCI (PR #141492)
via llvm-commits
llvm-commits at lists.llvm.org
Mon May 26 06:40:56 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
@llvm/pr-subscribers-llvm-selectiondag
Author: Luke Lau (lukel97)
<details>
<summary>Changes</summary>
This replaces LLVMHalfElementsVectorType and LLVMOne{3,4,5,6,7,8}ElementsVectorType with one parameterized IIT descriptor.
The type signature is encoded as the vector type to match followed by the divisor N, and inside IITDescriptor this is stored as two 16 bit parts, similarly to LLVMVectorOfAnyPointersToElt.
This also allows us to use a foreach to delcare the [de]interleave intrinsics.
Stacked on #<!-- -->139893
---
Patch is 790.54 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/141492.diff
10 Files Affected:
- (modified) llvm/docs/LangRef.rst (+5-5)
- (modified) llvm/include/llvm/IR/Intrinsics.h (+10-14)
- (modified) llvm/include/llvm/IR/Intrinsics.td (+20-75)
- (modified) llvm/include/llvm/IR/IntrinsicsAArch64.td (+5-5)
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (+18)
- (modified) llvm/lib/IR/Intrinsics.cpp (+11-43)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll (+293-288)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll (+1620-133)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll (+672-81)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll (+9979-3877)
``````````diff
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index 7fbac14112af3..8c0a046d3a7e9 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -20209,7 +20209,7 @@ Arguments:
The argument to this intrinsic must be a vector.
-'``llvm.vector.deinterleave2/3/5/7``' Intrinsic
+'``llvm.vector.deinterleave2/3/4/5/6/7/8``' Intrinsic
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Syntax:
@@ -20227,8 +20227,8 @@ This is an overloaded intrinsic.
Overview:
"""""""""
-The '``llvm.vector.deinterleave2/3/5/7``' intrinsics deinterleave adjacent lanes
-into 2, 3, 5, and 7 separate vectors, respectively, and return them as the
+The '``llvm.vector.deinterleave2/3/4/5/6/7/8``' intrinsics deinterleave adjacent lanes
+into 2 through to 8 separate vectors, respectively, and return them as the
result.
This intrinsic works for both fixed and scalable vectors. While this intrinsic
@@ -20250,7 +20250,7 @@ Arguments:
The argument is a vector whose type corresponds to the logical concatenation of
the aggregated result types.
-'``llvm.vector.interleave2/3/5/7``' Intrinsic
+'``llvm.vector.interleave2/3/4/5/6/7/8``' Intrinsic
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Syntax:
@@ -20268,7 +20268,7 @@ This is an overloaded intrinsic.
Overview:
"""""""""
-The '``llvm.vector.interleave2/3/5/7``' intrinsic constructs a vector
+The '``llvm.vector.interleave2/3/4/5/6/7/8``' intrinsic constructs a vector
by interleaving all the input vectors.
This intrinsic works for both fixed and scalable vectors. While this intrinsic
diff --git a/llvm/include/llvm/IR/Intrinsics.h b/llvm/include/llvm/IR/Intrinsics.h
index 6fb1bf9359b9a..7aa6cbe93c132 100644
--- a/llvm/include/llvm/IR/Intrinsics.h
+++ b/llvm/include/llvm/IR/Intrinsics.h
@@ -151,10 +151,7 @@ namespace Intrinsic {
Argument,
ExtendArgument,
TruncArgument,
- HalfVecArgument,
- OneThirdVecArgument,
- OneFifthVecArgument,
- OneSeventhVecArgument,
+ OneNthEltsVecArgument,
SameVecWidthArgument,
VecOfAnyPtrsToElt,
VecElementArgument,
@@ -166,9 +163,6 @@ namespace Intrinsic {
AArch64Svcount,
} Kind;
- // These three have to be contiguous.
- static_assert(OneFifthVecArgument == OneThirdVecArgument + 1 &&
- OneSeventhVecArgument == OneFifthVecArgument + 1);
union {
unsigned Integer_Width;
unsigned Float_Width;
@@ -187,18 +181,14 @@ namespace Intrinsic {
unsigned getArgumentNumber() const {
assert(Kind == Argument || Kind == ExtendArgument ||
- Kind == TruncArgument || Kind == HalfVecArgument ||
- Kind == OneThirdVecArgument || Kind == OneFifthVecArgument ||
- Kind == OneSeventhVecArgument || Kind == SameVecWidthArgument ||
+ Kind == TruncArgument || Kind == SameVecWidthArgument ||
Kind == VecElementArgument || Kind == Subdivide2Argument ||
Kind == Subdivide4Argument || Kind == VecOfBitcastsToInt);
return Argument_Info >> 3;
}
ArgKind getArgumentKind() const {
assert(Kind == Argument || Kind == ExtendArgument ||
- Kind == TruncArgument || Kind == HalfVecArgument ||
- Kind == OneThirdVecArgument || Kind == OneFifthVecArgument ||
- Kind == OneSeventhVecArgument || Kind == SameVecWidthArgument ||
+ Kind == TruncArgument || Kind == SameVecWidthArgument ||
Kind == VecElementArgument || Kind == Subdivide2Argument ||
Kind == Subdivide4Argument || Kind == VecOfBitcastsToInt);
return (ArgKind)(Argument_Info & 7);
@@ -210,8 +200,14 @@ namespace Intrinsic {
assert(Kind == VecOfAnyPtrsToElt);
return Argument_Info >> 16;
}
+ // OneNthEltsVecArguments uses both a divisor N and a reference argument for
+ // the full-width vector to match
+ unsigned getVectorDivisor() const {
+ assert(Kind == OneNthEltsVecArgument);
+ return Argument_Info >> 16;
+ }
unsigned getRefArgNumber() const {
- assert(Kind == VecOfAnyPtrsToElt);
+ assert(Kind == VecOfAnyPtrsToElt || Kind == OneNthEltsVecArgument);
return Argument_Info & 0xFFFF;
}
diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index d5481c6b81f9f..0ac7288ebdf8a 100644
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -306,7 +306,7 @@ def IIT_TRUNC_ARG : IIT_Base<26>;
def IIT_ANYPTR : IIT_Base<27>;
def IIT_V1 : IIT_Vec<1, 28>;
def IIT_VARARG : IIT_VT<isVoid, 29>;
-def IIT_HALF_VEC_ARG : IIT_Base<30>;
+def IIT_ONE_NTH_ELTS_VEC_ARG : IIT_Base<30>;
def IIT_SAME_VEC_WIDTH_ARG : IIT_Base<31>;
def IIT_VEC_OF_ANYPTRS_TO_ELT : IIT_Base<34>;
def IIT_I128 : IIT_Int<128, 35>;
@@ -335,11 +335,8 @@ def IIT_I4 : IIT_Int<4, 58>;
def IIT_AARCH64_SVCOUNT : IIT_VT<aarch64svcount, 59>;
def IIT_V6 : IIT_Vec<6, 60>;
def IIT_V10 : IIT_Vec<10, 61>;
-def IIT_ONE_THIRD_VEC_ARG : IIT_Base<62>;
-def IIT_ONE_FIFTH_VEC_ARG : IIT_Base<63>;
-def IIT_ONE_SEVENTH_VEC_ARG : IIT_Base<64>;
-def IIT_V2048: IIT_Vec<2048, 65>;
-def IIT_V4096: IIT_Vec<4096, 66>;
+def IIT_V2048: IIT_Vec<2048, 62>;
+def IIT_V4096: IIT_Vec<4096, 63>;
}
defvar IIT_all_FixedTypes = !filter(iit, IIT_all,
@@ -476,18 +473,15 @@ class LLVMVectorOfAnyPointersToElt<int num>
class LLVMVectorElementType<int num> : LLVMMatchType<num, IIT_VEC_ELEMENT>;
// Match the type of another intrinsic parameter that is expected to be a
-// vector type, but change the element count to be half as many.
-class LLVMHalfElementsVectorType<int num>
- : LLVMMatchType<num, IIT_HALF_VEC_ARG>;
-
-class LLVMOneThirdElementsVectorType<int num>
- : LLVMMatchType<num, IIT_ONE_THIRD_VEC_ARG>;
-
-class LLVMOneFifthElementsVectorType<int num>
- : LLVMMatchType<num, IIT_ONE_FIFTH_VEC_ARG>;
-
-class LLVMOneSeventhElementsVectorType<int num>
- : LLVMMatchType<num, IIT_ONE_SEVENTH_VEC_ARG>;
+// vector type, but change the element count to be 1/n of it.
+class LLVMOneNthElementsVectorType<int idx, int n>
+ : LLVMMatchType<idx, IIT_ONE_NTH_ELTS_VEC_ARG> {
+ let Sig = [
+ IIT_ONE_NTH_ELTS_VEC_ARG.Number,
+ EncNextArgN<idx>.ret,
+ n,
+ ];
+}
// Match the type of another intrinsic parameter that is expected to be a
// vector type (i.e. <N x iM>) but with each element subdivided to
@@ -2758,64 +2752,15 @@ def int_vector_extract : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[llvm_anyvector_ty, llvm_i64_ty],
[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>]>;
+foreach n = 2...8 in {
+ def int_vector_interleave#n : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ !listsplat(LLVMOneNthElementsVectorType<0, n>, n),
+ [IntrNoMem]>;
-def int_vector_interleave2 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
- [LLVMHalfElementsVectorType<0>,
- LLVMHalfElementsVectorType<0>],
- [IntrNoMem]>;
-
-def int_vector_deinterleave2 : DefaultAttrsIntrinsic<[LLVMHalfElementsVectorType<0>,
- LLVMHalfElementsVectorType<0>],
- [llvm_anyvector_ty],
- [IntrNoMem]>;
-
-def int_vector_interleave3 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
- [LLVMOneThirdElementsVectorType<0>,
- LLVMOneThirdElementsVectorType<0>,
- LLVMOneThirdElementsVectorType<0>],
- [IntrNoMem]>;
-
-def int_vector_deinterleave3 : DefaultAttrsIntrinsic<[LLVMOneThirdElementsVectorType<0>,
- LLVMOneThirdElementsVectorType<0>,
- LLVMOneThirdElementsVectorType<0>],
- [llvm_anyvector_ty],
- [IntrNoMem]>;
-
-def int_vector_interleave5 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
- [LLVMOneFifthElementsVectorType<0>,
- LLVMOneFifthElementsVectorType<0>,
- LLVMOneFifthElementsVectorType<0>,
- LLVMOneFifthElementsVectorType<0>,
- LLVMOneFifthElementsVectorType<0>],
- [IntrNoMem]>;
-
-def int_vector_deinterleave5 : DefaultAttrsIntrinsic<[LLVMOneFifthElementsVectorType<0>,
- LLVMOneFifthElementsVectorType<0>,
- LLVMOneFifthElementsVectorType<0>,
- LLVMOneFifthElementsVectorType<0>,
- LLVMOneFifthElementsVectorType<0>],
- [llvm_anyvector_ty],
- [IntrNoMem]>;
-
-def int_vector_interleave7 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
- [LLVMOneSeventhElementsVectorType<0>,
- LLVMOneSeventhElementsVectorType<0>,
- LLVMOneSeventhElementsVectorType<0>,
- LLVMOneSeventhElementsVectorType<0>,
- LLVMOneSeventhElementsVectorType<0>,
- LLVMOneSeventhElementsVectorType<0>,
- LLVMOneSeventhElementsVectorType<0>],
- [IntrNoMem]>;
-
-def int_vector_deinterleave7 : DefaultAttrsIntrinsic<[LLVMOneSeventhElementsVectorType<0>,
- LLVMOneSeventhElementsVectorType<0>,
- LLVMOneSeventhElementsVectorType<0>,
- LLVMOneSeventhElementsVectorType<0>,
- LLVMOneSeventhElementsVectorType<0>,
- LLVMOneSeventhElementsVectorType<0>,
- LLVMOneSeventhElementsVectorType<0>],
- [llvm_anyvector_ty],
- [IntrNoMem]>;
+ def int_vector_deinterleave#n : DefaultAttrsIntrinsic<!listsplat(LLVMOneNthElementsVectorType<0, n>, n),
+ [llvm_anyvector_ty],
+ [IntrNoMem]>;
+}
//===-------------- Intrinsics to perform partial reduction ---------------===//
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index 67fd91f0896eb..0ec5f5163118e 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -186,7 +186,7 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
[IntrNoMem]>;
class AdvSIMD_2VectorArg_Tied_Narrow_Intrinsic
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
- [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty],
+ [LLVMOneNthElementsVectorType<0, 2>, llvm_anyvector_ty],
[IntrNoMem]>;
class AdvSIMD_2VectorArg_Lane_Intrinsic
: DefaultAttrsIntrinsic<[llvm_anyint_ty],
@@ -207,11 +207,11 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
[IntrNoMem]>;
class AdvSIMD_3VectorArg_Tied_Narrow_Intrinsic
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
- [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty,
+ [LLVMOneNthElementsVectorType<0, 2>, llvm_anyvector_ty,
LLVMMatchType<1>], [IntrNoMem]>;
class AdvSIMD_3VectorArg_Scalar_Tied_Narrow_Intrinsic
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
- [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, llvm_i32_ty],
+ [LLVMOneNthElementsVectorType<0, 2>, llvm_anyvector_ty, llvm_i32_ty],
[IntrNoMem]>;
class AdvSIMD_CvtFxToFP_Intrinsic
: DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty],
@@ -1330,7 +1330,7 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
[IntrNoMem, ImmArg<ArgIndex<0>>]>;
class AdvSIMD_SVE_PUNPKHI_Intrinsic
- : DefaultAttrsIntrinsic<[LLVMHalfElementsVectorType<0>],
+ : DefaultAttrsIntrinsic<[LLVMOneNthElementsVectorType<0, 2>],
[llvm_anyvector_ty],
[IntrNoMem]>;
@@ -4229,4 +4229,4 @@ let TargetPrefix = "aarch64" in {
def int_aarch64_sme_fp8_fvdot_lane_za16_vg1x2 : SME_FP8_ZA_LANE_VGx2_Intrinsic;
def int_aarch64_sme_fp8_fvdotb_lane_za32_vg1x4 : SME_FP8_ZA_LANE_VGx2_Intrinsic;
def int_aarch64_sme_fp8_fvdott_lane_za32_vg1x4 : SME_FP8_ZA_LANE_VGx2_Intrinsic;
-}
\ No newline at end of file
+}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 434484b671bf2..ca195cb37de8a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -8198,24 +8198,42 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
case Intrinsic::vector_interleave3:
visitVectorInterleave(I, 3);
return;
+ case Intrinsic::vector_interleave4:
+ visitVectorInterleave(I, 4);
+ return;
case Intrinsic::vector_interleave5:
visitVectorInterleave(I, 5);
return;
+ case Intrinsic::vector_interleave6:
+ visitVectorInterleave(I, 6);
+ return;
case Intrinsic::vector_interleave7:
visitVectorInterleave(I, 7);
return;
+ case Intrinsic::vector_interleave8:
+ visitVectorInterleave(I, 8);
+ return;
case Intrinsic::vector_deinterleave2:
visitVectorDeinterleave(I, 2);
return;
case Intrinsic::vector_deinterleave3:
visitVectorDeinterleave(I, 3);
return;
+ case Intrinsic::vector_deinterleave4:
+ visitVectorDeinterleave(I, 4);
+ return;
case Intrinsic::vector_deinterleave5:
visitVectorDeinterleave(I, 5);
return;
+ case Intrinsic::vector_deinterleave6:
+ visitVectorDeinterleave(I, 6);
+ return;
case Intrinsic::vector_deinterleave7:
visitVectorDeinterleave(I, 7);
return;
+ case Intrinsic::vector_deinterleave8:
+ visitVectorDeinterleave(I, 8);
+ return;
case Intrinsic::experimental_vector_compress:
setValue(&I, DAG.getNode(ISD::VECTOR_COMPRESS, sdl,
getValue(I.getArgOperand(0)).getValueType(),
diff --git a/llvm/lib/IR/Intrinsics.cpp b/llvm/lib/IR/Intrinsics.cpp
index dabb5fe006b3c..e631419d5e1c2 100644
--- a/llvm/lib/IR/Intrinsics.cpp
+++ b/llvm/lib/IR/Intrinsics.cpp
@@ -366,28 +366,11 @@ DecodeIITType(unsigned &NextElt, ArrayRef<unsigned char> Infos,
IITDescriptor::get(IITDescriptor::TruncArgument, ArgInfo));
return;
}
- case IIT_HALF_VEC_ARG: {
- unsigned ArgInfo = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
- OutputTable.push_back(
- IITDescriptor::get(IITDescriptor::HalfVecArgument, ArgInfo));
- return;
- }
- case IIT_ONE_THIRD_VEC_ARG: {
- unsigned ArgInfo = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
- OutputTable.push_back(
- IITDescriptor::get(IITDescriptor::OneThirdVecArgument, ArgInfo));
- return;
- }
- case IIT_ONE_FIFTH_VEC_ARG: {
- unsigned ArgInfo = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
- OutputTable.push_back(
- IITDescriptor::get(IITDescriptor::OneFifthVecArgument, ArgInfo));
- return;
- }
- case IIT_ONE_SEVENTH_VEC_ARG: {
- unsigned ArgInfo = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
+ case IIT_ONE_NTH_ELTS_VEC_ARG: {
+ unsigned short ArgNo = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
+ unsigned short N = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
OutputTable.push_back(
- IITDescriptor::get(IITDescriptor::OneSeventhVecArgument, ArgInfo));
+ IITDescriptor::get(IITDescriptor::OneNthEltsVecArgument, N, ArgNo));
return;
}
case IIT_SAME_VEC_WIDTH_ARG: {
@@ -580,15 +563,9 @@ static Type *DecodeFixedType(ArrayRef<Intrinsic::IITDescriptor> &Infos,
int SubDivs = D.Kind == IITDescriptor::Subdivide2Argument ? 1 : 2;
return VectorType::getSubdividedVectorType(VTy, SubDivs);
}
- case IITDescriptor::HalfVecArgument:
- return VectorType::getHalfElementsVectorType(
- cast<VectorType>(Tys[D.getArgumentNumber()]));
- case IITDescriptor::OneThirdVecArgument:
- case IITDescriptor::OneFifthVecArgument:
- case IITDescriptor::OneSeventhVecArgument:
+ case IITDescriptor::OneNthEltsVecArgument:
return VectorType::getOneNthElementsVectorType(
- cast<VectorType>(Tys[D.getArgumentNumber()]),
- 3 + (D.Kind - IITDescriptor::OneThirdVecArgument) * 2);
+ cast<VectorType>(Tys[D.getRefArgNumber()]), D.getVectorDivisor());
case IITDescriptor::SameVecWidthArgument: {
Type *EltTy = DecodeFixedType(Infos, Tys, Context);
Type *Ty = Tys[D.getArgumentNumber()];
@@ -966,23 +943,14 @@ matchIntrinsicType(Type *Ty, ArrayRef<Intrinsic::IITDescriptor> &Infos,
return Ty != NewTy;
}
- case IITDescriptor::HalfVecArgument:
+ case IITDescriptor::OneNthEltsVecArgument:
// If this is a forward reference, defer the check for later.
- if (D.getArgumentNumber() >= ArgTys.size())
- return IsDeferredCheck || DeferCheck(Ty);
- return !isa<VectorType>(ArgTys[D.getArgumentNumber()]) ||
- VectorType::getHalfElementsVectorType(
- cast<VectorType>(ArgTys[D.getArgumentNumber()])) != Ty;
- case IITDescriptor::OneThirdVecArgument:
- case IITDescriptor::OneFifthVecArgument:
- case IITDescriptor::OneSeventhVecArgument:
- // If this is a forward reference, defer the check for later.
- if (D.getArgumentNumber() >= ArgTys.size())
+ if (D.getRefArgNumber() >= ArgTys.size())
return IsDeferredCheck || DeferCheck(Ty);
- return !isa<VectorType>(ArgTys[D.getArgumentNumber()]) ||
+ return !isa<VectorType>(ArgTys[D.getRefArgNumber()]) ||
VectorType::getOneNthElementsVectorType(
- cast<VectorType>(ArgTys[D.getArgumentNumber()]),
- 3 + (D.Kind - IITDescriptor::OneThirdVecArgument) * 2) != Ty;
+ cast<VectorType>(ArgTys[D.getRefArgNumber()]),
+ D.getVectorDivisor()) != Ty;
case IITDescriptor::SameVecWidthArgument: {
if (D.getArgumentNumber() >= ArgTys.size()) {
// Defer check and subsequent check for the vector element type.
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
index f6b5a35aa06d6..aab2f08277831 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh | FileCheck %s --check-prefixes=CHECK,V,RV32
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh | FileCheck %s --check-prefixes=CHECK,V,RV64
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+experimental-xrivosvizip | FileCheck %s --check-prefixes=CHECK,ZIP
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+m,+zvfh | FileCheck %s --check-prefixes=CHECK,V,RV32
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+m,+zvfh | FileCheck %s --check-prefixes=CHECK,V,RV64
+; RUN: llc < %s -mtr...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/141492
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