[llvm] 8a198f8 - [AMDGPU] si-peephole-sdwa: Remove dead code from createSDWAversion (#141462)

via llvm-commits llvm-commits at lists.llvm.org
Mon May 26 06:28:07 PDT 2025


Author: Frederik Harwath
Date: 2025-05-26T15:28:03+02:00
New Revision: 8a198f89bfa0fb8225a3ffc90df8c7b9b722aeff

URL: https://github.com/llvm/llvm-project/commit/8a198f89bfa0fb8225a3ffc90df8c7b9b722aeff
DIFF: https://github.com/llvm/llvm-project/commit/8a198f89bfa0fb8225a3ffc90df8c7b9b722aeff.diff

LOG: [AMDGPU] si-peephole-sdwa: Remove dead code from createSDWAversion (#141462)

In an earlier state of this code, it was possible for an existing SDWA
MI to reach the code in the "createSDWAversion" function. This is no
longer possible; see assert at the top of the function.

Remove code that tries to handle operands on pre-existing SDWA
instructions from the function.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
index 1e305c2efc8a0..eb18677780803 100644
--- a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
@@ -1273,65 +1273,22 @@ MachineInstr *SIPeepholeSDWA::createSDWAVersion(MachineInstr &MI) {
     }
   }
 
-  // Copy dst_sel if present, initialize otherwise if needed
-  if (AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::dst_sel)) {
-    MachineOperand *DstSel = TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel);
-    if (DstSel) {
-      SDWAInst.add(*DstSel);
-    } else {
-      SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD);
-    }
-  }
+  // Initialize SDWA specific operands
+  if (AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::dst_sel))
+    SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD);
 
-  // Copy dst_unused if present, initialize otherwise if needed
-  if (AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::dst_unused)) {
-    MachineOperand *DstUnused = TII->getNamedOperand(MI, AMDGPU::OpName::dst_unused);
-    if (DstUnused) {
-      SDWAInst.add(*DstUnused);
-    } else {
-      SDWAInst.addImm(AMDGPU::SDWA::DstUnused::UNUSED_PAD);
-    }
-  }
+  if (AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::dst_unused))
+    SDWAInst.addImm(AMDGPU::SDWA::DstUnused::UNUSED_PAD);
 
-  // Copy src0_sel if present, initialize otherwise
   assert(AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::src0_sel));
-  MachineOperand *Src0Sel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel);
-  if (Src0Sel) {
-    SDWAInst.add(*Src0Sel);
-  } else {
-    SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD);
-  }
+  SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD);
 
-  // Copy src1_sel if present, initialize otherwise if needed
   if (Src1) {
     assert(AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::src1_sel));
-    MachineOperand *Src1Sel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel);
-    if (Src1Sel) {
-      SDWAInst.add(*Src1Sel);
-    } else {
-      SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD);
-    }
+    SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD);
   }
 
   // Check for a preserved register that needs to be copied.
-  auto *DstUnused = TII->getNamedOperand(MI, AMDGPU::OpName::dst_unused);
-  if (DstUnused &&
-      DstUnused->getImm() == AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) {
-    // We expect, if we are here, that the instruction was already in it's SDWA form,
-    // with a tied operand.
-    assert(Dst && Dst->isTied());
-    assert(Opcode == static_cast<unsigned int>(SDWAOpcode));
-    // We also expect a vdst, since sdst can't preserve.
-    auto PreserveDstIdx = AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::vdst);
-    assert(PreserveDstIdx != -1);
-
-    auto TiedIdx = MI.findTiedOperandIdx(PreserveDstIdx);
-    auto Tied = MI.getOperand(TiedIdx);
-
-    SDWAInst.add(Tied);
-    SDWAInst->tieOperands(PreserveDstIdx, SDWAInst->getNumOperands() - 1);
-  }
-
   MachineInstr *Ret = SDWAInst.getInstr();
   TII->fixImplicitOperands(*Ret);
   return Ret;


        


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