[llvm] [AArch64] Fix #94909: Optimize vector fmul(sitofp(x), 0.5) -> scvtf(x, 2) (PR #141480)

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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 54511d620..688931cd2 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -19252,7 +19252,8 @@ static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG,
 
 /// Try to extract a log2 exponent from a uniform constant FP splat.
 /// Returns -1 if the value is not a power-of-two float.
-static int getUniformFPSplatLog2(const BuildVectorSDNode *BV, unsigned MaxExponent) {
+static int getUniformFPSplatLog2(const BuildVectorSDNode *BV,
+                                 unsigned MaxExponent) {
   SDValue FirstElt = BV->getOperand(0);
   if (!isa<ConstantFPSDNode>(FirstElt))
     return -1;
@@ -19302,8 +19303,7 @@ static int getUniformFPSplatLog2(const BuildVectorSDNode *BV, unsigned MaxExpone
 
   // Extract exponent
   unsigned ExponentShift = MantissaBits;
-  APInt ExponentMask = APInt::getBitsSet(Bits.getBitWidth(),
-                                         ExponentShift,
+  APInt ExponentMask = APInt::getBitsSet(Bits.getBitWidth(), ExponentShift,
                                          ExponentShift + ExponentBits);
   int Exponent = (Bits & ExponentMask).lshr(ExponentShift).getZExtValue();
   int Log2 = ExponentBias - Exponent;
@@ -19319,13 +19319,13 @@ static int getUniformFPSplatLog2(const BuildVectorSDNode *BV, unsigned MaxExpone
 static SDValue performFMulCombine(SDNode *N, SelectionDAG &DAG,
                                   TargetLowering::DAGCombinerInfo &DCI,
                                   const AArch64Subtarget *Subtarget) {
-                                    
+
   if (!Subtarget->hasNEON())
     return SDValue();
 
   // N is the FMUL node.
   if (N->getOpcode() != ISD::FMUL)
-      return SDValue();
+    return SDValue();
 
   // SINT_TO_FP or UINT_TO_FP
   SDValue Op = N->getOperand(0);
@@ -19363,7 +19363,7 @@ static SDValue performFMulCombine(SDNode *N, SelectionDAG &DAG,
   // Check if IntrinsicC is within the valid range [1, FloatBits].
   // The 's' value must be in [1, FloatBits].
   if (IntrinsicC <= 0 || IntrinsicC > FloatBits)
-      return SDValue();
+    return SDValue();
 
   MVT ResTy;
   unsigned NumLanes = Op.getValueType().getVectorNumElements();

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https://github.com/llvm/llvm-project/pull/141480