[llvm] [AMDGPU] Cluster export instruction in PostRA Scheduler (PR #141399)

[Carl Ritson via llvm-commits]

https://github.com/perlfu updated https://github.com/llvm/llvm-project/pull/141399

>From 0d548269354d1f2806d4027727f30e8c3b2f5ea0 Mon Sep 17 00:00:00 2001
From: Carl Ritson <carl.ritson at amd.com>
Date: Sun, 25 May 2025 16:52:49 +0900
Subject: [PATCH 1/2] [AMDGPU] Cluster export instruction in PostRA Scheduler

DAG mutation needs to be applied post-RA to maintain order
established during pre-RA scheduler.
---
 llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index e24d8481408ad..7479703ce353a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1129,6 +1129,7 @@ GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
        getOptLevel() >= CodeGenOptLevel::Less) &&
       EnableVOPD)
     DAG->addMutation(createVOPDPairingMutation());
+  DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
   return DAG;
 }
 //===----------------------------------------------------------------------===//

>From fba6127e4133f2a3ab3bfb4d7cf51d69ff49f413 Mon Sep 17 00:00:00 2001
From: Carl Ritson <carl.ritson at amd.com>
Date: Sun, 25 May 2025 17:16:22 +0900
Subject: [PATCH 2/2] - Test changes

---
 llvm/test/CodeGen/AMDGPU/export-cluster-postra.mir | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/export-cluster-postra.mir b/llvm/test/CodeGen/AMDGPU/export-cluster-postra.mir
index 089fc220ff9ed..5dfec45245a83 100644
--- a/llvm/test/CodeGen/AMDGPU/export-cluster-postra.mir
+++ b/llvm/test/CodeGen/AMDGPU/export-cluster-postra.mir
@@ -23,12 +23,12 @@ body: |
     ; CHECK-NEXT: }
     ; CHECK-NEXT: $vgpr6 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, killed $vgpr6, 0, 1065353216, 0, 0, implicit $mode, implicit $exec
     ; CHECK-NEXT: $vgpr5 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, killed $vgpr5, 0, 1065353216, 0, 0, implicit $mode, implicit $exec
-    ; CHECK-NEXT: EXP 0, killed $vgpr0, killed $vgpr6, undef $vgpr0, undef $vgpr0, -1, 0, 3, implicit $exec
-    ; CHECK-NEXT: EXP 1, killed $vgpr1, killed $vgpr5, undef $vgpr0, undef $vgpr0, -1, 0, 3, implicit $exec
     ; CHECK-NEXT: $vgpr7 = nnan nsz arcp contract afn reassoc nofpexcept V_MUL_F32_e32 killed $sgpr0, $vgpr2, implicit $mode, implicit $exec
     ; CHECK-NEXT: $vgpr2 = nnan nsz arcp contract afn reassoc nofpexcept V_ADD_F32_e64 0, killed $vgpr2, 0, killed $sgpr1, 1, 0, implicit $mode, implicit $exec
     ; CHECK-NEXT: $vgpr3 = nofpexcept V_CVT_PKRTZ_F16_F32_e32 killed $vgpr7, killed $vgpr3, implicit $mode, implicit $exec
     ; CHECK-NEXT: $vgpr2 = nofpexcept V_CVT_PKRTZ_F16_F32_e32 killed $vgpr4, killed $vgpr2, implicit $mode, implicit $exec
+    ; CHECK-NEXT: EXP 0, killed $vgpr0, killed $vgpr6, undef $vgpr0, undef $vgpr0, -1, 0, 3, implicit $exec
+    ; CHECK-NEXT: EXP 1, killed $vgpr1, killed $vgpr5, undef $vgpr0, undef $vgpr0, -1, 0, 3, implicit $exec
     ; CHECK-NEXT: EXP_DONE 2, killed $vgpr3, killed $vgpr2, undef $vgpr0, undef $vgpr0, -1, 0, 3, implicit $exec
     BUNDLE implicit-def $sgpr0, implicit-def $sgpr1, implicit $sgpr8_sgpr9_sgpr10_sgpr11 {
       $sgpr0 = S_BUFFER_LOAD_DWORD_IMM $sgpr8_sgpr9_sgpr10_sgpr11, 20, 0 :: (dereferenceable invariant load (s32))