[llvm] [NVPTX] Add intrinsics for the bmsk instruction (PR #139299)

[Durgadoss R via llvm-commits]

================
@@ -598,6 +598,32 @@ operand %b clamped to the range [0, 32]. The N lowest bits are then
 zero-extended the case of the '``zext``' variants, or sign-extended the case of
 the '``sext``' variants. If N is 0, the result is 0.
 
+'``llvm.nvvm.bmsk.{wrap,clamp}``' Intrinsic
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+
+.. code-block:: llvm
+
+    declare i32 @llvm.nvvm.bmsk.wrap(i32 %a, i32 %b)
+    declare i32 @llvm.nvvm.bmsk.clamp(i32 %a, i32 %b)
+
+Overview:
+"""""""""
+
+The '``llvm.nvvm.bmsk.{wrap,clamp}``' family of intrinsics creates a bit mask
+given a starting bit position and a bit width.
+
+Semantics:
+""""""""""
+
+The '``llvm.nvvm.bmsk.{wrap,clamp}``' family of intrinsics returns a value with
+all bits set to 0 except for %b bits starting at bit position %a. For the
+'``wrap``' variants, the values of %a and %b modulo 32 are used. For the
+'``clamp``' variants, the values of %a and %b are clamped to the range [0, 32],
+which in practice is equivalent to using them as is.
----------------
durga4github wrote:

LGTM,

We could add a link to the corresponding page in the PTX ISA.

https://github.com/llvm/llvm-project/pull/139299