[llvm] 5b91756 - [RISCV][Peephole] Checking regclass compatibility in VMV (#138844)

[via llvm-commits]

Author: Piyou Chen
Date: 2025-05-12T13:00:51+08:00
New Revision: 5b91756c0ca7ef4d75c33c2617bfd0f9719907dc

URL: https://github.com/llvm/llvm-project/commit/5b91756c0ca7ef4d75c33c2617bfd0f9719907dc
DIFF: https://github.com/llvm/llvm-project/commit/5b91756c0ca7ef4d75c33c2617bfd0f9719907dc.diff

LOG: [RISCV][Peephole] Checking regclass compatibility in VMV (#138844)

Without checking the regclass compatibility, this pass may generate bad
machine code.

```
*** Bad machine code: Illegal virtual register for instruction ***
- function:    main
- basic block: %bb.0 entry (0x9209848)
- instruction: %3:vrnov0 = PseudoVXOR_VV_MF2_MASK %0:vr(tied-def 0), %0:vr, %0:vr, %4:vmv0, 0, 5, 0
- operand 1:   %0:vr(tied-def 0)
Expected a VRNoV0 register, but got a VR register
```

---------

Co-authored-by: Luke Lau <luke_lau at icloud.com>

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
    llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index 41f8e1a5ef14d..721b0bf425e95 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -583,6 +583,8 @@ bool RISCVVectorPeephole::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
       SrcPolicy.setImm(SrcPolicy.getImm() | RISCVVType::TAIL_AGNOSTIC);
   }
 
+  MRI->constrainRegClass(MI.getOperand(2).getReg(),
+                         MRI->getRegClass(MI.getOperand(0).getReg()));
   MRI->replaceRegWith(MI.getOperand(0).getReg(), MI.getOperand(2).getReg());
   MRI->clearKillFlags(MI.getOperand(2).getReg());
   MI.eraseFromParent();
@@ -653,6 +655,8 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
     Policy |= RISCVVType::TAIL_AGNOSTIC;
   Src->getOperand(RISCVII::getVecPolicyOpNum(Src->getDesc())).setImm(Policy);
 
+  MRI->constrainRegClass(Src->getOperand(0).getReg(),
+                         MRI->getRegClass(MI.getOperand(0).getReg()));
   MRI->replaceRegWith(MI.getOperand(0).getReg(), Src->getOperand(0).getReg());
   MI.eraseFromParent();
 

diff  --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
index a2acb004642d6..f545ecc5e53d7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
@@ -105,3 +105,33 @@ body: |
     %3:vr = COPY %0
 ...
 ---
+name: 
diff _regclass
+body: |
+  bb.0.entry:
+    liveins: $v8
+    ; CHECK-LABEL: name: 
diff _regclass
+    ; CHECK: liveins: $v8
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 $noreg, 0, 0, 5 /* e32 */, 1 /* ta, mu */
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY $v8
+    ; CHECK-NEXT: [[PseudoVADD_VV_M1_MASK:%[0-9]+]]:vrnov0 = PseudoVADD_VV_M1_MASK [[PseudoVMV_V_I_MF2_]], $noreg, $noreg, [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */
+    %0:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
+    %1:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %0, 0, 5 /* e32 */, 0 /* tu, mu */
+    %2:vmv0 = COPY $v8
+    %3:vrnov0 = PseudoVADD_VV_M1_MASK %1, $noreg, $noreg, %2, 0, 5 /* e32 */, 0 /* tu, mu */
+...
+---
+name: 
diff _regclass_passthru
+body: |
+  bb.0.entry:
+    liveins: $v8
+    ; CHECK-LABEL: name: 
diff _regclass_passthru
+    ; CHECK: liveins: $v8
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 $noreg, 0, 0, 5 /* e32 */, 1 /* ta, mu */
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY $v8
+    ; CHECK-NEXT: [[PseudoVLSE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLSE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], $noreg, $noreg, [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4)
+    %2:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
+    %3:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %2, 0, 5 /* e32 */, 0 /* tu, mu */
+    %7:vmv0 = COPY $v8
+    %6:vrnov0 = PseudoVLSE32_V_MF2_MASK %3, $noreg, $noreg, %7, 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4)