[llvm] aeb5a58 - [RISCV][NFC] Move VLDSX0Pred to RISCVInstrPredicates.td (#137938)

[via llvm-commits]

Author: Pengcheng Wang
Date: 2025-05-12T12:05:50+08:00
New Revision: aeb5a58d24f02f09abd35bfde5a294b7d2c8ffdc

URL: https://github.com/llvm/llvm-project/commit/aeb5a58d24f02f09abd35bfde5a294b7d2c8ffdc
DIFF: https://github.com/llvm/llvm-project/commit/aeb5a58d24f02f09abd35bfde5a294b7d2c8ffdc.diff

LOG: [RISCV][NFC] Move VLDSX0Pred to RISCVInstrPredicates.td (#137938)

`VLDSX0Pred` is used for scheduling vector zero-stride load/store.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrPredicates.td
    llvm/lib/Target/RISCV/RISCVScheduleV.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
index 715ba3abb02ab..348de5d48c50c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
@@ -10,6 +10,10 @@
 //
 //===----------------------------------------------------------------------===//
 
+// This predicate is true when the rs2 operand of vlse or vsse is x0, false
+// otherwise.
+def VLDSX0Pred : MCSchedPredicate<CheckRegOperand<3, X0>>;
+
 // Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
 def isSEXT_W
     : TIIPredicate<"isSEXT_W",

diff  --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index 0204ab4c98286..6c7658c7d93d8 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -9,10 +9,6 @@
 //===----------------------------------------------------------------------===//
 /// Define scheduler resources associated with def operands.
 
-// This predicate is true when the rs2 operand of vlse or vsse is x0, false
-// otherwise.
-def VLDSX0Pred : MCSchedPredicate<CheckRegOperand<3, X0>>;
-
 defvar SchedMxList = ["MF8", "MF4", "MF2", "M1", "M2", "M4", "M8"];
 // Used for widening and narrowing instructions as it doesn't contain M8.
 defvar SchedMxListW = !listremove(SchedMxList, ["M8"]);