[llvm] 2e1809f - [SPARC][IAS] Add definitions for UA 2005 instructions
via llvm-commits
llvm-commits at lists.llvm.org
Sun May 11 17:45:53 PDT 2025
Author: Koakuma
Date: 2025-05-12T07:45:49+07:00
New Revision: 2e1809f94aa0f1c1fa0281d1351c0e0ea0bf06e3
URL: https://github.com/llvm/llvm-project/commit/2e1809f94aa0f1c1fa0281d1351c0e0ea0bf06e3
DIFF: https://github.com/llvm/llvm-project/commit/2e1809f94aa0f1c1fa0281d1351c0e0ea0bf06e3.diff
LOG: [SPARC][IAS] Add definitions for UA 2005 instructions
Reviewers: rorth, s-barannikov, brad0
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/138400
Added:
llvm/lib/Target/Sparc/SparcInstrUAOSA.td
llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
llvm/test/MC/Sparc/sparc-ua2005.s
Modified:
llvm/lib/Target/Sparc/Sparc.td
llvm/lib/Target/Sparc/SparcInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index 2083c0e763b82..0d66a03fd941d 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -49,6 +49,9 @@ def FeatureVIS2
def FeatureVIS3
: SubtargetFeature<"vis3", "IsVIS3", "true",
"Enable Visual Instruction Set extensions III">;
+def FeatureUA2005
+ : SubtargetFeature<"ua2005", "IsUA2005", "true",
+ "Enable UltraSPARC Architecture 2005 extensions">;
def FeatureLeon
: SubtargetFeature<"leon", "IsLeon", "true",
"Enable LEON extensions">;
@@ -152,13 +155,15 @@ def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
FeatureVIS2],
[TuneSlowRDPC]>;
def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
- FeatureVIS2]>;
+ FeatureVIS2, FeatureUA2005]>;
def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc,
- FeatureVIS, FeatureVIS2]>;
+ FeatureVIS, FeatureVIS2, FeatureUA2005]>;
def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,
- FeatureVIS, FeatureVIS2, FeatureVIS3]>;
+ FeatureVIS, FeatureVIS2, FeatureVIS3,
+ FeatureUA2005]>;
def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
- FeatureVIS, FeatureVIS2, FeatureVIS3]>;
+ FeatureVIS, FeatureVIS2, FeatureVIS3,
+ FeatureUA2005]>;
// LEON 2 FT generic
def : Processor<"leon2", LEON2Itineraries,
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index fd9e36732ea4e..9102d35b1c4dc 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -47,6 +47,10 @@ def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
AssemblerPredicate<(all_of FeatureVIS3)>;
+// HasUA2005 - This is true when the target processor has UA 2005 extensions.
+def HasUA2005 : Predicate<"Subtarget->isUA2005()">,
+ AssemblerPredicate<(all_of FeatureUA2005)>;
+
// HasHardQuad - This is true when the target processor supports quad floating
// point instructions.
def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
@@ -1971,4 +1975,5 @@ def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),
include "SparcInstr64Bit.td"
include "SparcInstrVIS.td"
+include "SparcInstrUAOSA.td"
include "SparcInstrAliases.td"
diff --git a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
new file mode 100644
index 0000000000000..b00995a960968
--- /dev/null
+++ b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
@@ -0,0 +1,28 @@
+//=== SparcInstrUAOSA.td - UltraSPARC/Oracle SPARC Architecture extensions ===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains instruction formats, definitions and patterns needed for
+// UA 2005 instructions on SPARC.
+//===----------------------------------------------------------------------===//
+
+class UA2005RegWin<string asmstr, bits<5> fcn>
+ : F3_1<2, 0b110001, (outs), (ins), asmstr, []> {
+ let rd = fcn;
+ let rs1 = 0;
+ let rs2 = 0;
+}
+
+// UltraSPARC Architecture 2005 Instructions
+let Predicates = [HasUA2005] in {
+let hasSideEffects = 1 in {
+def ALLCLEAN : UA2005RegWin<"allclean", 0b00010>;
+def INVALW : UA2005RegWin<"invalw", 0b00101>;
+def NORMALW : UA2005RegWin<"normalw", 0b00100>;
+def OTHERW : UA2005RegWin<"otherw", 0b00011>;
+}
+} // Predicates = [HasUA2005]
diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
new file mode 100644
index 0000000000000..4a2de98e03fe3
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
@@ -0,0 +1,12 @@
+# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+ua2005 | FileCheck %s
+
+## UA 2005 instructions.
+
+# CHECK: allclean
+0x85,0x88,0x00,0x00
+# CHECK: invalw
+0x8b,0x88,0x00,0x00
+# CHECK: otherw
+0x87,0x88,0x00,0x00
+# CHECK: normalw
+0x89,0x88,0x00,0x00
diff --git a/llvm/test/MC/Sparc/sparc-ua2005.s b/llvm/test/MC/Sparc/sparc-ua2005.s
new file mode 100644
index 0000000000000..b07c99a20033b
--- /dev/null
+++ b/llvm/test/MC/Sparc/sparc-ua2005.s
@@ -0,0 +1,17 @@
+! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-UA2005 --implicit-check-not=error:
+! RUN: llvm-mc %s -triple=sparcv9 -mattr=+ua2005 -show-encoding | FileCheck %s --check-prefixes=UA2005
+
+!! UA 2005 instructions.
+
+! NO-UA2005: error: instruction requires a CPU feature not currently enabled
+! UA2005: allclean ! encoding: [0x85,0x88,0x00,0x00]
+allclean
+! NO-UA2005: error: instruction requires a CPU feature not currently enabled
+! UA2005: invalw ! encoding: [0x8b,0x88,0x00,0x00]
+invalw
+! NO-UA2005: error: instruction requires a CPU feature not currently enabled
+! UA2005: otherw ! encoding: [0x87,0x88,0x00,0x00]
+otherw
+! NO-UA2005: error: instruction requires a CPU feature not currently enabled
+! UA2005: normalw ! encoding: [0x89,0x88,0x00,0x00]
+normalw
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