[llvm] [RISCV][MC] Add aliases for beq/bne with x0 as the first argument => beqz/bnez (PR #139086)

[Alex Bradbury via llvm-commits]

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@@ -965,8 +965,12 @@ def : InstAlias<"sgtu $rd, $rs, $rt", (SLTU GPR:$rd, GPR:$rt, GPR:$rs), 0>;
 
 def : InstAlias<"beqz $rs, $offset",
                 (BEQ GPR:$rs,      X0, bare_simm13_lsb0:$offset)>;
+def : InstAlias<"beqz $rs, $offset",
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asb wrote:

That's a good question. Firstly it's worth noting that we do have test coverage that will catch if the order of the aliases is switched for some reason. Tracing through how it's ordered today:
* AsmMatcherEmitter adds `MatchableInfo` generated from the `InstAlias` to the `Matchables` vector in the order they are returned from `getAllDerivedDefinitions`. This isn't explicitly documented as being the source order in the .td, but appears to be so (and I imagine other things would break if that were changed).
* The `Matchables` are then sorted using a stable sort.
* Looking at `beqz` as an example, neither definition is less than the other according to the comparison function (same number of operands, operands compare the same. It compares two operands MCK_GPR == MCK_GPR, MCK_BareSImm13Lsb0 == MCK_BareSImm13Lsb0 (i.e. it is comparing the alias rather than the transformed instruction). And ultimately the lessthan comparison function just returns fals, so the aliases remain in source order in the matching table.

https://github.com/llvm/llvm-project/pull/139086