[llvm] [M68k] TableGen-erate SDNode descriptions (PR #139449)
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Sun May 11 06:25:08 PDT 2025
https://github.com/s-barannikov created https://github.com/llvm/llvm-project/pull/139449
This consolidates node definitions into one place and enables automatic node verification.
Part of #119709.
>From 20e3006ecff21d5d8074156cdd7d63aecb04320e Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Sat, 16 Nov 2024 03:11:23 +0300
Subject: [PATCH] [M68k] TableGen-erate SDNode descriptions
This consolidates node definitions into one place and enables automatic
node verification.
Part of #119709.
---
llvm/lib/Target/M68k/CMakeLists.txt | 2 +
llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp | 2 +-
llvm/lib/Target/M68k/M68kISelLowering.cpp | 59 +--------------
llvm/lib/Target/M68k/M68kISelLowering.h | 73 -------------------
llvm/lib/Target/M68k/M68kInstrInfo.td | 33 ++++++++-
llvm/lib/Target/M68k/M68kSelectionDAGInfo.cpp | 19 +++++
llvm/lib/Target/M68k/M68kSelectionDAGInfo.h | 28 +++++++
llvm/lib/Target/M68k/M68kSubtarget.cpp | 13 +++-
llvm/lib/Target/M68k/M68kSubtarget.h | 12 +--
9 files changed, 99 insertions(+), 142 deletions(-)
create mode 100644 llvm/lib/Target/M68k/M68kSelectionDAGInfo.cpp
create mode 100644 llvm/lib/Target/M68k/M68kSelectionDAGInfo.h
diff --git a/llvm/lib/Target/M68k/CMakeLists.txt b/llvm/lib/Target/M68k/CMakeLists.txt
index 1661dccece3dd..7005df4fb8a82 100644
--- a/llvm/lib/Target/M68k/CMakeLists.txt
+++ b/llvm/lib/Target/M68k/CMakeLists.txt
@@ -6,6 +6,7 @@ tablegen(LLVM M68kGenGlobalISel.inc -gen-global-isel)
tablegen(LLVM M68kGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM M68kGenRegisterBank.inc -gen-register-bank)
tablegen(LLVM M68kGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM M68kGenSDNodeInfo.inc -gen-sd-node-info)
tablegen(LLVM M68kGenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM M68kGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM M68kGenMCPseudoLowering.inc -gen-pseudo-lowering)
@@ -32,6 +33,7 @@ add_llvm_target(M68kCodeGen
M68kMachineFunction.cpp
M68kMCInstLower.cpp
M68kRegisterInfo.cpp
+ M68kSelectionDAGInfo.cpp
M68kSubtarget.cpp
M68kTargetMachine.cpp
M68kTargetObjectFile.cpp
diff --git a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
index 53c144c8fa79a..9c3d61ec60e00 100644
--- a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
+++ b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
@@ -15,8 +15,8 @@
#include "M68kMachineFunction.h"
#include "M68kRegisterInfo.h"
+#include "M68kSelectionDAGInfo.h"
#include "M68kTargetMachine.h"
-
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp
index 616b1f622619c..9d3ab606ab8cd 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -15,6 +15,7 @@
#include "M68kISelLowering.h"
#include "M68kCallingConv.h"
#include "M68kMachineFunction.h"
+#include "M68kSelectionDAGInfo.h"
#include "M68kSubtarget.h"
#include "M68kTargetMachine.h"
#include "M68kTargetObjectFile.h"
@@ -3641,64 +3642,6 @@ SDValue M68kTargetLowering::PerformDAGCombine(SDNode *N,
return SDValue();
}
-//===----------------------------------------------------------------------===//
-// M68kISD Node Names
-//===----------------------------------------------------------------------===//
-const char *M68kTargetLowering::getTargetNodeName(unsigned Opcode) const {
- switch (Opcode) {
- case M68kISD::CALL:
- return "M68kISD::CALL";
- case M68kISD::TAIL_CALL:
- return "M68kISD::TAIL_CALL";
- case M68kISD::RET:
- return "M68kISD::RET";
- case M68kISD::TC_RETURN:
- return "M68kISD::TC_RETURN";
- case M68kISD::ADD:
- return "M68kISD::ADD";
- case M68kISD::SUB:
- return "M68kISD::SUB";
- case M68kISD::ADDX:
- return "M68kISD::ADDX";
- case M68kISD::SUBX:
- return "M68kISD::SUBX";
- case M68kISD::SMUL:
- return "M68kISD::SMUL";
- case M68kISD::UMUL:
- return "M68kISD::UMUL";
- case M68kISD::OR:
- return "M68kISD::OR";
- case M68kISD::XOR:
- return "M68kISD::XOR";
- case M68kISD::AND:
- return "M68kISD::AND";
- case M68kISD::CMP:
- return "M68kISD::CMP";
- case M68kISD::BTST:
- return "M68kISD::BTST";
- case M68kISD::SELECT:
- return "M68kISD::SELECT";
- case M68kISD::CMOV:
- return "M68kISD::CMOV";
- case M68kISD::BRCOND:
- return "M68kISD::BRCOND";
- case M68kISD::SETCC:
- return "M68kISD::SETCC";
- case M68kISD::SETCC_CARRY:
- return "M68kISD::SETCC_CARRY";
- case M68kISD::GLOBAL_BASE_REG:
- return "M68kISD::GLOBAL_BASE_REG";
- case M68kISD::Wrapper:
- return "M68kISD::Wrapper";
- case M68kISD::WrapperPC:
- return "M68kISD::WrapperPC";
- case M68kISD::SEG_ALLOCA:
- return "M68kISD::SEG_ALLOCA";
- default:
- return NULL;
- }
-}
-
CCAssignFn *M68kTargetLowering::getCCAssignFn(CallingConv::ID CC, bool Return,
bool IsVarArg) const {
if (Return)
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.h b/llvm/lib/Target/M68k/M68kISelLowering.h
index b646f7d7fb2ba..3774f93c851e8 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.h
+++ b/llvm/lib/Target/M68k/M68kISelLowering.h
@@ -25,77 +25,6 @@
#include <deque>
namespace llvm {
-namespace M68kISD {
-
-/// M68k Specific DAG nodes
-enum NodeType {
- /// Start the numbering from where ISD NodeType finishes.
- FIRST_NUMBER = ISD::BUILTIN_OP_END,
-
- CALL,
- RET,
- TAIL_CALL,
- TC_RETURN,
-
- /// M68k compare and logical compare instructions. Subtracts the source
- /// operand from the destination data register and sets the condition
- /// codes according to the result. Immediate always goes first.
- CMP,
-
- /// M68k bit-test instructions.
- BTST,
-
- /// M68k Select
- SELECT,
-
- /// M68k SetCC. Operand 0 is condition code, and operand 1 is the CCR
- /// operand, usually produced by a CMP instruction.
- SETCC,
-
- // Same as SETCC except it's materialized with a subx and the value is all
- // one's or all zero's.
- SETCC_CARRY, // R = carry_bit ? ~0 : 0
-
- /// M68k conditional moves. Operand 0 and operand 1 are the two values
- /// to select from. Operand 2 is the condition code, and operand 3 is the
- /// flag operand produced by a CMP or TEST instruction. It also writes a
- /// flag result.
- CMOV,
-
- /// M68k conditional branches. Operand 0 is the chain operand, operand 1
- /// is the block to branch if condition is true, operand 2 is the
- /// condition code, and operand 3 is the flag operand produced by a CMP
- /// or TEST instruction.
- BRCOND,
-
- // Arithmetic operations with CCR results.
- ADD,
- SUB,
- ADDX,
- SUBX,
- SMUL,
- UMUL,
- OR,
- XOR,
- AND,
-
- // GlobalBaseReg,
- GLOBAL_BASE_REG,
-
- /// A wrapper node for TargetConstantPool,
- /// TargetExternalSymbol, and TargetGlobalAddress.
- Wrapper,
-
- /// Special wrapper used under M68k PIC mode for PC
- /// relative displacements.
- WrapperPC,
-
- // For allocating variable amounts of stack space when using
- // segmented stacks. Check if the current stacklet has enough space, and
- // falls back to heap allocation if not.
- SEG_ALLOCA,
-};
-} // namespace M68kISD
/// Define some predicates that are used for node matching.
namespace M68k {
@@ -124,8 +53,6 @@ class M68kTargetLowering : public TargetLowering {
static const M68kTargetLowering *create(const M68kTargetMachine &TM,
const M68kSubtarget &STI);
- const char *getTargetNodeName(unsigned Opcode) const override;
-
/// Return the value type to use for ISD::SETCC.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
EVT VT) const override;
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.td b/llvm/lib/Target/M68k/M68kInstrInfo.td
index dca774e94b9b5..e9213f20c68e7 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.td
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.td
@@ -112,9 +112,18 @@ def MxRet : SDNode<"M68kISD::RET", MxSDT_Ret,
def MxTCRet : SDNode<"M68kISD::TC_RETURN", MxSDT_TCRet,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
+def MxGlobalBaseReg : SDNode<"M68kISD::GLOBAL_BASE_REG",
+ SDTypeProfile<1, 0, [SDTCisVT<0, iPTR>]>>;
+
+// A wrapper node for TargetConstantPool,
+// TargetExternalSymbol, and TargetGlobalAddress.
def MxWrapper : SDNode<"M68kISD::Wrapper", MxSDT_Wrapper>;
+
+// Special wrapper used under M68k PIC mode for PC
+// relative displacements.
def MxWrapperPC : SDNode<"M68kISD::WrapperPC", MxSDT_Wrapper>;
+// Arithmetic operations with CCR results.
def MxAdd : SDNode<"M68kISD::ADD", MxSDT_BiArithCCROut, [SDNPCommutative]>;
def MxSub : SDNode<"M68kISD::SUB", MxSDT_BiArithCCROut>;
def MxOr : SDNode<"M68kISD::OR", MxSDT_BiArithCCROut, [SDNPCommutative]>;
@@ -127,15 +136,37 @@ def MxSubX : SDNode<"M68kISD::SUBX", MxSDT_BiArithCCRInOut>;
def MxSMul : SDNode<"M68kISD::SMUL", MxSDT_BiArithCCROut, [SDNPCommutative]>;
def MxUMul : SDNode<"M68kISD::UMUL", MxSDT_BiArithCCROut, [SDNPCommutative]>;
+// M68k compare and logical compare instructions. Subtracts the source
+// operand from the destination data register and sets the condition
+// codes according to the result. Immediate always goes first.
def MxCmp : SDNode<"M68kISD::CMP", MxSDT_CmpTest>;
+
+// M68k bit-test instructions.
def MxBtst : SDNode<"M68kISD::BTST", MxSDT_CmpTest>;
+// M68k conditional moves. Operand 0 and operand 1 are the two values
+// to select from. Operand 2 is the condition code, and operand 3 is the
+// flag operand produced by a CMP or TEST instruction. It also writes a
+// flag result.
def MxCmov : SDNode<"M68kISD::CMOV", MxSDT_Cmov>;
+
+// M68k conditional branches. Operand 0 is the chain operand, operand 1
+// is the block to branch if condition is true, operand 2 is the
+// condition code, and operand 3 is the flag operand produced by a CMP
+// or TEST instruction.
def MxBrCond : SDNode<"M68kISD::BRCOND", MxSDT_BrCond, [SDNPHasChain]>;
+
+// M68k SetCC. Operand 0 is condition code, and operand 1 is the CCR
+// operand, usually produced by a CMP instruction.
def MxSetCC : SDNode<"M68kISD::SETCC", MxSDT_SetCC>;
-def MxSetCC_C : SDNode<"M68kISD::SETCC_CARRY", MxSDT_SetCC_C>;
+// Same as SETCC except it's materialized with a subx and the value is all
+// one's or all zero's.
+def MxSetCC_C : SDNode<"M68kISD::SETCC_CARRY", MxSDT_SetCC_C>;
+// For allocating variable amounts of stack space when using
+// segmented stacks. Check if the current stacklet has enough space, and
+// falls back to heap allocation if not.
def MxSegAlloca : SDNode<"M68kISD::SEG_ALLOCA", MxSDT_SEG_ALLOCA,
[SDNPHasChain]>;
diff --git a/llvm/lib/Target/M68k/M68kSelectionDAGInfo.cpp b/llvm/lib/Target/M68k/M68kSelectionDAGInfo.cpp
new file mode 100644
index 0000000000000..dd1bfdf00af8c
--- /dev/null
+++ b/llvm/lib/Target/M68k/M68kSelectionDAGInfo.cpp
@@ -0,0 +1,19 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "M68kSelectionDAGInfo.h"
+
+#define GET_SDNODE_DESC
+#include "M68kGenSDNodeInfo.inc"
+
+using namespace llvm;
+
+M68kSelectionDAGInfo::M68kSelectionDAGInfo()
+ : SelectionDAGGenTargetInfo(M68kGenSDNodeInfo) {}
+
+M68kSelectionDAGInfo::~M68kSelectionDAGInfo() = default;
diff --git a/llvm/lib/Target/M68k/M68kSelectionDAGInfo.h b/llvm/lib/Target/M68k/M68kSelectionDAGInfo.h
new file mode 100644
index 0000000000000..87a8c08d2591e
--- /dev/null
+++ b/llvm/lib/Target/M68k/M68kSelectionDAGInfo.h
@@ -0,0 +1,28 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_M68K_M68KSELECTIONDAGINFO_H
+#define LLVM_LIB_TARGET_M68K_M68KSELECTIONDAGINFO_H
+
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+
+#define GET_SDNODE_ENUM
+#include "M68kGenSDNodeInfo.inc"
+
+namespace llvm {
+
+class M68kSelectionDAGInfo : public SelectionDAGGenTargetInfo {
+public:
+ M68kSelectionDAGInfo();
+
+ ~M68kSelectionDAGInfo() override;
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_M68K_M68KSELECTIONDAGINFO_H
diff --git a/llvm/lib/Target/M68k/M68kSubtarget.cpp b/llvm/lib/Target/M68k/M68kSubtarget.cpp
index 53ec574ae5596..59d865ff1f4a9 100644
--- a/llvm/lib/Target/M68k/M68kSubtarget.cpp
+++ b/llvm/lib/Target/M68k/M68kSubtarget.cpp
@@ -15,12 +15,11 @@
#include "GISel/M68kCallLowering.h"
#include "GISel/M68kLegalizerInfo.h"
#include "GISel/M68kRegisterBankInfo.h"
-
#include "M68k.h"
#include "M68kMachineFunction.h"
#include "M68kRegisterInfo.h"
+#include "M68kSelectionDAGInfo.h"
#include "M68kTargetMachine.h"
-
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
@@ -50,10 +49,12 @@ void M68kSubtarget::anchor() {}
M68kSubtarget::M68kSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
const M68kTargetMachine &TM)
- : M68kGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TM(TM), TSInfo(),
+ : M68kGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TM(TM),
InstrInfo(initializeSubtargetDependencies(CPU, TT, FS, TM)),
FrameLowering(*this, this->getStackAlignment()), TLInfo(TM, *this),
TargetTriple(TT) {
+ TSInfo = std::make_unique<M68kSelectionDAGInfo>();
+
CallLoweringInfo.reset(new M68kCallLowering(*getTargetLowering()));
Legalizer.reset(new M68kLegalizerInfo(*this));
@@ -62,6 +63,12 @@ M68kSubtarget::M68kSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
InstSelector.reset(createM68kInstructionSelector(TM, *this, *RBI));
}
+M68kSubtarget::~M68kSubtarget() = default;
+
+const SelectionDAGTargetInfo *M68kSubtarget::getSelectionDAGInfo() const {
+ return TSInfo.get();
+}
+
const CallLowering *M68kSubtarget::getCallLowering() const {
return CallLoweringInfo.get();
}
diff --git a/llvm/lib/Target/M68k/M68kSubtarget.h b/llvm/lib/Target/M68k/M68kSubtarget.h
index c08a9786fb27b..16ca7d2e6d0fd 100644
--- a/llvm/lib/Target/M68k/M68kSubtarget.h
+++ b/llvm/lib/Target/M68k/M68kSubtarget.h
@@ -22,7 +22,6 @@
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/RegisterBankInfo.h"
-#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/MC/MCInstrItineraries.h"
@@ -63,7 +62,6 @@ class M68kSubtarget : public M68kGenSubtargetInfo {
const M68kTargetMachine &TM;
- SelectionDAGTargetInfo TSInfo;
M68kInstrInfo InstrInfo;
M68kFrameLowering FrameLowering;
M68kTargetLowering TLInfo;
@@ -80,6 +78,8 @@ class M68kSubtarget : public M68kGenSubtargetInfo {
M68kSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
const M68kTargetMachine &_TM);
+ ~M68kSubtarget() override;
+
/// Parses features string setting specified subtarget options. Definition
/// of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
@@ -148,10 +148,6 @@ class M68kSubtarget : public M68kGenSubtargetInfo {
StringRef FS,
const M68kTargetMachine &TM);
- const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
- return &TSInfo;
- }
-
const M68kInstrInfo *getInstrInfo() const override { return &InstrInfo; }
const M68kFrameLowering *getFrameLowering() const override {
@@ -171,6 +167,9 @@ class M68kSubtarget : public M68kGenSubtargetInfo {
}
protected:
+ // SelectionDAGISel related APIs.
+ std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
+
// GlobalISel related APIs.
std::unique_ptr<CallLowering> CallLoweringInfo;
std::unique_ptr<InstructionSelector> InstSelector;
@@ -178,6 +177,7 @@ class M68kSubtarget : public M68kGenSubtargetInfo {
std::unique_ptr<RegisterBankInfo> RegBankInfo;
public:
+ const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
const CallLowering *getCallLowering() const override;
InstructionSelector *getInstructionSelector() const override;
const LegalizerInfo *getLegalizerInfo() const override;
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