[llvm] c11aba9 - [AVR] TableGen-erate SDNode descriptions (NFC) (#139407)
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Sun May 11 05:43:35 PDT 2025
Author: Sergei Barannikov
Date: 2025-05-11T15:43:31+03:00
New Revision: c11aba93d639fdd3ec02cb89079d180a9885ad90
URL: https://github.com/llvm/llvm-project/commit/c11aba93d639fdd3ec02cb89079d180a9885ad90
DIFF: https://github.com/llvm/llvm-project/commit/c11aba93d639fdd3ec02cb89079d180a9885ad90.diff
LOG: [AVR] TableGen-erate SDNode descriptions (NFC) (#139407)
This consolidates node definitions into one place and enables automatic
node verification.
Part of #119709.
Added:
llvm/lib/Target/AVR/AVRSelectionDAGInfo.cpp
Modified:
llvm/lib/Target/AVR/AVRISelLowering.cpp
llvm/lib/Target/AVR/AVRISelLowering.h
llvm/lib/Target/AVR/AVRInstrInfo.td
llvm/lib/Target/AVR/AVRSelectionDAGInfo.h
llvm/lib/Target/AVR/CMakeLists.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index c73ff83d29789..eca682895e24f 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -220,40 +220,6 @@ AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
setMinimumJumpTableEntries(UINT_MAX);
}
-const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
-#define NODE(name) \
- case AVRISD::name: \
- return #name
-
- switch (Opcode) {
- default:
- return nullptr;
- NODE(RET_GLUE);
- NODE(RETI_GLUE);
- NODE(CALL);
- NODE(WRAPPER);
- NODE(LSL);
- NODE(LSLW);
- NODE(LSR);
- NODE(LSRW);
- NODE(ROL);
- NODE(ROR);
- NODE(ASR);
- NODE(ASRW);
- NODE(LSLLOOP);
- NODE(LSRLOOP);
- NODE(ROLLOOP);
- NODE(RORLOOP);
- NODE(ASRLOOP);
- NODE(BRCOND);
- NODE(CMP);
- NODE(CMPC);
- NODE(TST);
- NODE(SELECT_CC);
-#undef NODE
- }
-}
-
EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
EVT VT) const {
assert(!VT.isVector() && "No AVR SetCC type for vectors!");
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.h b/llvm/lib/Target/AVR/AVRISelLowering.h
index cd45444e2bc3a..2ae22b2d8af6c 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.h
+++ b/llvm/lib/Target/AVR/AVRISelLowering.h
@@ -19,64 +19,6 @@
namespace llvm {
-namespace AVRISD {
-
-/// AVR Specific DAG Nodes
-enum NodeType {
- /// Start the numbering where the builtin ops leave off.
- FIRST_NUMBER = ISD::BUILTIN_OP_END,
- /// Return from subroutine.
- RET_GLUE,
- /// Return from ISR.
- RETI_GLUE,
- /// Represents an abstract call instruction,
- /// which includes a bunch of information.
- CALL,
- /// A wrapper node for TargetConstantPool,
- /// TargetExternalSymbol, and TargetGlobalAddress.
- WRAPPER,
- LSL, ///< Logical shift left.
- LSLBN, ///< Byte logical shift left N bits.
- LSLWN, ///< Word logical shift left N bits.
- LSLHI, ///< Higher 8-bit of word logical shift left.
- LSLW, ///< Wide logical shift left.
- LSR, ///< Logical shift right.
- LSRBN, ///< Byte logical shift right N bits.
- LSRWN, ///< Word logical shift right N bits.
- LSRLO, ///< Lower 8-bit of word logical shift right.
- LSRW, ///< Wide logical shift right.
- ASR, ///< Arithmetic shift right.
- ASRBN, ///< Byte arithmetic shift right N bits.
- ASRWN, ///< Word arithmetic shift right N bits.
- ASRLO, ///< Lower 8-bit of word arithmetic shift right.
- ASRW, ///< Wide arithmetic shift right.
- ROR, ///< Bit rotate right.
- ROL, ///< Bit rotate left.
- LSLLOOP, ///< A loop of single logical shift left instructions.
- LSRLOOP, ///< A loop of single logical shift right instructions.
- ROLLOOP, ///< A loop of single left bit rotate instructions.
- RORLOOP, ///< A loop of single right bit rotate instructions.
- ASRLOOP, ///< A loop of single arithmetic shift right instructions.
- /// AVR conditional branches. Operand 0 is the chain operand, operand 1
- /// is the block to branch if condition is true, operand 2 is the
- /// condition code, and operand 3 is the flag operand produced by a CMP
- /// or TEST instruction.
- BRCOND,
- /// Compare instruction.
- CMP,
- /// Compare with carry instruction.
- CMPC,
- /// Test for zero or minus instruction.
- TST,
- /// Swap Rd[7:4] <-> Rd[3:0].
- SWAP,
- /// Operand 0 and operand 1 are selection variable, operand 2
- /// is condition code and operand 3 is flag operand.
- SELECT_CC
-};
-
-} // end of namespace AVRISD
-
class AVRSubtarget;
class AVRTargetMachine;
@@ -95,8 +37,6 @@ class AVRTargetLowering : public TargetLowering {
return MVT::i8;
}
- const char *getTargetNodeName(unsigned Opcode) const override;
-
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td b/llvm/lib/Target/AVR/AVRInstrInfo.td
index b00938ca64221..958e1383acef2 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -32,46 +32,67 @@ def SDT_AVRSelectCC
// AVR Specific Node Definitions
//===----------------------------------------------------------------------===//
+// Return from subroutine.
def AVRretglue : SDNode<"AVRISD::RET_GLUE", SDTNone,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
+
+// Return from ISR.
def AVRretiglue : SDNode<"AVRISD::RETI_GLUE", SDTNone,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
+
def AVRcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AVRCallSeqStart,
[SDNPHasChain, SDNPOutGlue]>;
def AVRcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AVRCallSeqEnd,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
+// Represents an abstract call instruction,
+// which includes a bunch of information.
def AVRcall : SDNode<"AVRISD::CALL", SDT_AVRCall,
[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>;
+// A wrapper node for TargetConstantPool,
+// TargetExternalSymbol, and TargetGlobalAddress.
def AVRWrapper : SDNode<"AVRISD::WRAPPER", SDT_AVRWrapper>;
+// AVR conditional branches. Operand 0 is the chain operand, operand 1
+// is the block to branch if condition is true, operand 2 is the
+// condition code, and operand 3 is the flag operand produced by a CMP
+// or TEST instruction.
def AVRbrcond
: SDNode<"AVRISD::BRCOND", SDT_AVRBrcond, [SDNPHasChain, SDNPInGlue]>;
+
+// Compare instruction.
def AVRcmp : SDNode<"AVRISD::CMP", SDT_AVRCmp, [SDNPOutGlue]>;
+
+// Compare with carry instruction.
def AVRcmpc : SDNode<"AVRISD::CMPC", SDT_AVRCmp, [SDNPInGlue, SDNPOutGlue]>;
+
+// Test for zero or minus instruction.
def AVRtst : SDNode<"AVRISD::TST", SDT_AVRTst, [SDNPOutGlue]>;
+
+// Operand 0 and operand 1 are selection variable, operand 2
+// is condition code and operand 3 is flag operand.
def AVRselectcc : SDNode<"AVRISD::SELECT_CC", SDT_AVRSelectCC, [SDNPInGlue]>;
// Shift nodes.
-def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>;
-def AVRlsr : SDNode<"AVRISD::LSR", SDTIntUnaryOp>;
-def AVRrol : SDNode<"AVRISD::ROL", SDTIntUnaryOp>;
-def AVRror : SDNode<"AVRISD::ROR", SDTIntUnaryOp>;
-def AVRasr : SDNode<"AVRISD::ASR", SDTIntUnaryOp>;
-def AVRlslhi : SDNode<"AVRISD::LSLHI", SDTIntUnaryOp>;
-def AVRlsrlo : SDNode<"AVRISD::LSRLO", SDTIntUnaryOp>;
-def AVRasrlo : SDNode<"AVRISD::ASRLO", SDTIntUnaryOp>;
-def AVRlslbn : SDNode<"AVRISD::LSLBN", SDTIntBinOp>;
-def AVRlsrbn : SDNode<"AVRISD::LSRBN", SDTIntBinOp>;
-def AVRasrbn : SDNode<"AVRISD::ASRBN", SDTIntBinOp>;
-def AVRlslwn : SDNode<"AVRISD::LSLWN", SDTIntBinOp>;
-def AVRlsrwn : SDNode<"AVRISD::LSRWN", SDTIntBinOp>;
-def AVRasrwn : SDNode<"AVRISD::ASRWN", SDTIntBinOp>;
-def AVRlslw : SDNode<"AVRISD::LSLW", SDTIntShiftPairOp>;
-def AVRlsrw : SDNode<"AVRISD::LSRW", SDTIntShiftPairOp>;
-def AVRasrw : SDNode<"AVRISD::ASRW", SDTIntShiftPairOp>;
+def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>; // Logical shift left.
+def AVRlsr : SDNode<"AVRISD::LSR", SDTIntUnaryOp>; // Logical shift right.
+def AVRrol : SDNode<"AVRISD::ROL", SDTIntUnaryOp>; // Bit rotate left.
+def AVRror : SDNode<"AVRISD::ROR", SDTIntUnaryOp>; // Bit rotate right.
+def AVRasr : SDNode<"AVRISD::ASR", SDTIntUnaryOp>; // Arithmetic shift right.
+def AVRlslhi : SDNode<"AVRISD::LSLHI", SDTIntUnaryOp>; // Higher 8-bit of word logical shift left.
+def AVRlsrlo : SDNode<"AVRISD::LSRLO", SDTIntUnaryOp>; // Lower 8-bit of word logical shift right.
+def AVRasrlo : SDNode<"AVRISD::ASRLO", SDTIntUnaryOp>; // Lower 8-bit of word arithmetic shift right.
+def AVRlslbn : SDNode<"AVRISD::LSLBN", SDTIntBinOp>; // Byte logical shift left N bits.
+def AVRlsrbn : SDNode<"AVRISD::LSRBN", SDTIntBinOp>; // Byte logical shift right N bits.
+def AVRasrbn : SDNode<"AVRISD::ASRBN", SDTIntBinOp>; // Byte arithmetic shift right N bits.
+def AVRlslwn : SDNode<"AVRISD::LSLWN", SDTIntBinOp>; // Higher 8-bit of word logical shift left.
+def AVRlsrwn : SDNode<"AVRISD::LSRWN", SDTIntBinOp>; // Word logical shift right N bits.
+def AVRasrwn : SDNode<"AVRISD::ASRWN", SDTIntBinOp>; // Word arithmetic shift right N bits.
+def AVRlslw : SDNode<"AVRISD::LSLW", SDTIntShiftPairOp>; // Wide logical shift left.
+def AVRlsrw : SDNode<"AVRISD::LSRW", SDTIntShiftPairOp>; // Wide logical shift right.
+def AVRasrw : SDNode<"AVRISD::ASRW", SDTIntShiftPairOp>; // Wide arithmetic shift right.
// Pseudo shift nodes for non-constant shift amounts.
def AVRlslLoop : SDNode<"AVRISD::LSLLOOP", SDTIntShiftOp>;
diff --git a/llvm/lib/Target/AVR/AVRSelectionDAGInfo.cpp b/llvm/lib/Target/AVR/AVRSelectionDAGInfo.cpp
new file mode 100644
index 0000000000000..5a685ab65b777
--- /dev/null
+++ b/llvm/lib/Target/AVR/AVRSelectionDAGInfo.cpp
@@ -0,0 +1,19 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "AVRSelectionDAGInfo.h"
+
+#define GET_SDNODE_DESC
+#include "AVRGenSDNodeInfo.inc"
+
+using namespace llvm;
+
+AVRSelectionDAGInfo::AVRSelectionDAGInfo()
+ : SelectionDAGGenTargetInfo(AVRGenSDNodeInfo) {}
+
+AVRSelectionDAGInfo::~AVRSelectionDAGInfo() = default;
diff --git a/llvm/lib/Target/AVR/AVRSelectionDAGInfo.h b/llvm/lib/Target/AVR/AVRSelectionDAGInfo.h
index 3e7bd57f10cf0..0edac1ef45f2f 100644
--- a/llvm/lib/Target/AVR/AVRSelectionDAGInfo.h
+++ b/llvm/lib/Target/AVR/AVRSelectionDAGInfo.h
@@ -15,11 +15,17 @@
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+#define GET_SDNODE_ENUM
+#include "AVRGenSDNodeInfo.inc"
+
namespace llvm {
/// Holds information about the AVR instruction selection DAG.
-class AVRSelectionDAGInfo : public SelectionDAGTargetInfo {
+class AVRSelectionDAGInfo : public SelectionDAGGenTargetInfo {
public:
+ AVRSelectionDAGInfo();
+
+ ~AVRSelectionDAGInfo() override;
};
} // end namespace llvm
diff --git a/llvm/lib/Target/AVR/CMakeLists.txt b/llvm/lib/Target/AVR/CMakeLists.txt
index 817ba739d8418..781dac02c7083 100644
--- a/llvm/lib/Target/AVR/CMakeLists.txt
+++ b/llvm/lib/Target/AVR/CMakeLists.txt
@@ -10,6 +10,7 @@ tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM AVRGenSDNodeInfo.inc -gen-sd-node-info)
tablegen(LLVM AVRGenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(AVRCommonTableGen)
@@ -23,6 +24,7 @@ add_llvm_target(AVRCodeGen
AVRISelLowering.cpp
AVRMCInstLower.cpp
AVRRegisterInfo.cpp
+ AVRSelectionDAGInfo.cpp
AVRShiftExpand.cpp
AVRSubtarget.cpp
AVRTargetMachine.cpp
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