[llvm] [X86][Codegen] add sched for lnlp (PR #139446)
via llvm-commits
llvm-commits at lists.llvm.org
Sun May 11 04:48:43 PDT 2025
https://github.com/mahesh-attarde created https://github.com/llvm/llvm-project/pull/139446
With this patch, we introduce scheduling model for Lunarlake P-core.
>From f96a6948bf842005b357ddd1718c47984f50e732 Mon Sep 17 00:00:00 2001
From: mattarde <mattarde at intel.com>
Date: Sun, 11 May 2025 04:41:35 -0700
Subject: [PATCH] add sched for lnlp
---
llvm/lib/Target/X86/X86.td | 5 +-
llvm/lib/Target/X86/X86SchedLunarlakeP.td | 2409 ++++++++++++++
.../X86/LunarlakeP/independent-load-stores.s | 149 +
.../LunarlakeP/partially-overlapping-groups.s | 21 +
.../llvm-mca/X86/LunarlakeP/resources-aes.s | 69 +
.../llvm-mca/X86/LunarlakeP/resources-avx1.s | 2429 ++++++++++++++
.../llvm-mca/X86/LunarlakeP/resources-avx2.s | 1093 +++++++
.../X86/LunarlakeP/resources-avxgfni.s | 83 +
.../X86/LunarlakeP/resources-avxvnni.s | 97 +
.../llvm-mca/X86/LunarlakeP/resources-bmi2.s | 153 +
.../X86/LunarlakeP/resources-clflushopt.s | 45 +
.../llvm-mca/X86/LunarlakeP/resources-clwb.s | 45 +
.../llvm-mca/X86/LunarlakeP/resources-cmov.s | 335 ++
.../X86/LunarlakeP/resources-cmpxchg.s | 54 +
.../llvm-mca/X86/LunarlakeP/resources-f16c.s | 69 +
.../llvm-mca/X86/LunarlakeP/resources-fma.s | 713 ++++
.../X86/LunarlakeP/resources-fsgsbase.s | 69 +
.../llvm-mca/X86/LunarlakeP/resources-gfni.s | 62 +
.../llvm-mca/X86/LunarlakeP/resources-lea.s | 449 +++
.../llvm-mca/X86/LunarlakeP/resources-lzcnt.s | 62 +
.../llvm-mca/X86/LunarlakeP/resources-mmx.s | 405 +++
.../llvm-mca/X86/LunarlakeP/resources-movbe.s | 62 +
.../X86/LunarlakeP/resources-pclmul.s | 48 +
.../X86/LunarlakeP/resources-popcnt.s | 62 +
.../X86/LunarlakeP/resources-prefetchw.s | 48 +
.../X86/LunarlakeP/resources-rdrand.s | 51 +
.../X86/LunarlakeP/resources-rdseed.s | 51 +
.../llvm-mca/X86/LunarlakeP/resources-sse1.s | 473 +++
.../llvm-mca/X86/LunarlakeP/resources-sse2.s | 972 ++++++
.../llvm-mca/X86/LunarlakeP/resources-sse3.s | 116 +
.../llvm-mca/X86/LunarlakeP/resources-sse41.s | 378 +++
.../llvm-mca/X86/LunarlakeP/resources-sse42.s | 111 +
.../llvm-mca/X86/LunarlakeP/resources-ssse3.s | 265 ++
.../llvm-mca/X86/LunarlakeP/resources-vaes.s | 69 +
.../X86/LunarlakeP/resources-vpclmulqdq.s | 48 +
.../X86/LunarlakeP/resources-x86_32.s | 90 +
.../X86/LunarlakeP/resources-x86_64.s | 2887 +++++++++++++++++
.../llvm-mca/X86/LunarlakeP/resources-x87.s | 533 +++
.../llvm-mca/X86/LunarlakeP/resources-xsave.s | 61 +
.../llvm-mca/X86/LunarlakeP/zero-idioms.s | 503 +++
40 files changed, 15643 insertions(+), 1 deletion(-)
create mode 100644 llvm/lib/Target/X86/X86SchedLunarlakeP.td
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/independent-load-stores.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/partially-overlapping-groups.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-aes.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avx1.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avx2.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avxgfni.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avxvnni.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-bmi2.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-clflushopt.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-clwb.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-cmov.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-cmpxchg.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-f16c.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-fma.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-fsgsbase.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-gfni.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-lea.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-lzcnt.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-mmx.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-movbe.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-pclmul.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-popcnt.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-prefetchw.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-rdrand.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-rdseed.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse1.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse2.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse3.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse41.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse42.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-ssse3.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-vaes.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-vpclmulqdq.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-x86_32.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-x86_64.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-x87.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-xsave.s
create mode 100644 llvm/test/tools/llvm-mca/X86/LunarlakeP/zero-idioms.s
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 2d635835e3ff7..a31bde85e4d02 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -811,6 +811,7 @@ include "X86SchedSkylakeClient.td"
include "X86SchedSkylakeServer.td"
include "X86SchedIceLake.td"
include "X86SchedAlderlakeP.td"
+include "X86SchedLunarlakeP.td"
include "X86SchedSapphireRapids.td"
//===----------------------------------------------------------------------===//
@@ -1862,10 +1863,12 @@ def : ProcModel<"meteorlake", AlderlakePModel,
ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
def : ProcModel<"arrowlake", AlderlakePModel,
ProcessorFeatures.SRFFeatures, ProcessorFeatures.ADLTuning>;
-foreach P = ["arrowlake-s", "arrowlake_s", "lunarlake"] in {
+foreach P = ["arrowlake-s", "arrowlake_s"] in {
def : ProcModel<P, AlderlakePModel,
ProcessorFeatures.ARLSFeatures, ProcessorFeatures.ADLTuning>;
}
+def : ProcModel<"lunarlake", LunarlakePModel, ProcessorFeatures.ARLSFeatures,
+ ProcessorFeatures.ADLTuning>;
def : ProcModel<"pantherlake", AlderlakePModel,
ProcessorFeatures.PTLFeatures, ProcessorFeatures.ADLTuning>;
def : ProcModel<"clearwaterforest", AlderlakePModel,
diff --git a/llvm/lib/Target/X86/X86SchedLunarlakeP.td b/llvm/lib/Target/X86/X86SchedLunarlakeP.td
new file mode 100644
index 0000000000000..e82d7ab805077
--- /dev/null
+++ b/llvm/lib/Target/X86/X86SchedLunarlakeP.td
@@ -0,0 +1,2409 @@
+//=----- X86SchedLunarlakeP.td - X86 LunarlakeP Scheduling *- tablegen -----*=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the machine model for LunarlakeP to support instruction
+// scheduling and other instruction cost heuristics.
+//
+//===----------------------------------------------------------------------===//
+def LunarlakePModel : SchedMachineModel {
+ // LunarlakeP can allocate 8 uops per cycle.
+ // Max micro-ops that may be scheduled per cycle.
+ // Based on Allocator Width
+ let IssueWidth = 8;
+ // Max micro-ops that can be buffered.
+ // Based on size of ROB
+ let MicroOpBufferSize = 792;
+ // INT LOAD takes 4 cycles
+ let LoadLatency = 4;
+ let MispredictPenalty = 14;
+ // Latency for microcoded instructions or instructions without latency info.
+ int MaxLatency = 100;
+ // Based on the LSD (loop-stream detector) queue size (ST).
+ // LSD is 200 uops per logical processor in single threaded mode
+ // For SMT 100 uops/thread, LionCove removed SMT in HW.
+ let LoopMicroOpBufferSize = 200;
+ // This flag is set to allow the scheduler to assign a default model to
+ // unrecognized opcodes.
+ let CompleteModel = 0;
+}
+
+let SchedModel = LunarlakePModel in {
+
+// LunarlakeP can issue micro-ops to 18 different ports in one cycle.
+// Lion Cove architectural spec uses port naming that is not sequential
+// for better comprehension we opt for sequential naming since this ports
+// serve logical information for schedule only.
+// 6 INT ALU Ports {P0 to P5}
+def LNLPPort00 : ProcResource<1>;
+def LNLPPort01 : ProcResource<1>;
+def LNLPPort02 : ProcResource<1>;
+def LNLPPort03 : ProcResource<1>;
+def LNLPPort04 : ProcResource<1>;
+def LNLPPort05 : ProcResource<1>;
+// 4 VEC ALU Ports {V0 to V3}
+def LNLPVPort00 : ProcResource<1>;
+def LNLPVPort01 : ProcResource<1>;
+def LNLPVPort02 : ProcResource<1>;
+def LNLPVPort03 : ProcResource<1>;
+// 2 Store Data Ports {P10 to P11}
+def LNLPPort10 : ProcResource<1>;
+def LNLPPort11 : ProcResource<1>;
+// 6 MEM Ports 6 AGU shared with 3 LD, 3 ST
+// AGU LD {P20 to P22}
+def LNLPPort20 : ProcResource<1>;
+def LNLPPort21 : ProcResource<1>;
+def LNLPPort22 : ProcResource<1>;
+// AGU ST {P25 to P27}
+def LNLPPort25 : ProcResource<1>;
+def LNLPPort26 : ProcResource<1>;
+def LNLPPort27 : ProcResource<1>;
+
+// Workaround to represent invalid ports. WriteRes shouldn't use this resource.
+def LNLPPortInvalid :ProcResource<1>;
+
+// Many micro-ops are capable of issuing on multiple ports.
+def LNLPVPort00_01 : ProcResGroup<[LNLPVPort00, LNLPVPort01]>;
+def LNLPVPort02_03 : ProcResGroup<[LNLPVPort02, LNLPVPort03]>;
+def LNLPPort00_02_04 : ProcResGroup<[LNLPPort00, LNLPPort02, LNLPPort04]>;
+def LNLPPort01_03_05 : ProcResGroup<[LNLPPort01, LNLPPort03, LNLPPort05]>;
+def LNLPPort20_21_22 : ProcResGroup<[LNLPPort20, LNLPPort21, LNLPPort22]>;
+def LNLPPort25_26_27 : ProcResGroup<[LNLPPort25, LNLPPort26, LNLPPort27]>;
+
+// INT EU has 112 reservation stations.
+def LNLPPort00_01_02_03_04_05 : ProcResGroup<[LNLPPort00, LNLPPort01, LNLPPort02,
+ LNLPPort03, LNLPPort04, LNLPPort05]>{
+ let BufferSize = 110; // Reduced from 128 in GLC
+}
+
+// VEC EU has 180 reservation stations.
+def LNLPVPort00_01_02_03 : ProcResGroup<[LNLPVPort00, LNLPVPort01, LNLPVPort02,
+ LNLPVPort03]>{
+ let BufferSize = 180; // EU for INT and VEC are seperated
+ // VEC QUEUE SIZE = 60 + VEC EU RS (60+60)
+}
+// STD has 48 reservation stations.
+def LNLPPort10_11 : ProcResGroup<[LNLPPort10, LNLPPort11]> {
+ let BufferSize = 48;
+}
+
+// MEM has 72 reservation stations.
+def LNLPPort20_21_22_25_26_27 : ProcResGroup<[LNLPPort20, LNLPPort21, LNLPPort22,
+ LNLPPort25, LNLPPort26, LNLPPort27]> {
+ let BufferSize = 72;
+}
+
+def LNLPPortAny : ProcResGroup<[LNLPPort00, LNLPPort01, LNLPPort02, LNLPPort03,
+ LNLPPort04, LNLPPort05, LNLPVPort00, LNLPVPort01,
+ LNLPVPort02, LNLPVPort03, LNLPPort10, LNLPPort11,
+ LNLPPort20, LNLPPort21, LNLPPort22, LNLPPort25,
+ LNLPPort26, LNLPPort27]>;
+
+// Integer loads are 4 cycles, so ReadAfterLd registers needn't be available
+// until 4 cycles after the memory operand.
+def : ReadAdvance<ReadAfterLd, 4>;
+
+// TODO: 6 Cycle latency for Vec load comes from ADL
+// Vector loads are 6 cycles, so ReadAfterVec*Ld registers needn't be available
+// until 6 cycles after the memory operand.
+def : ReadAdvance<ReadAfterVecLd, 6>;
+def : ReadAdvance<ReadAfterVecXLd, 6>;
+def : ReadAdvance<ReadAfterVecYLd, 6>;
+
+def : ReadAdvance<ReadInt2Fpu, 0>;
+
+// Many SchedWrites are defined in pairs with and without a folded load.
+// Instructions with folded loads are usually micro-fused, so they only appear
+// as two micro-ops when queued in the reservation station.
+// This multiclass defines the resource usage for variants with and without
+// folded loads.
+multiclass LNLPWriteResPair<X86FoldableSchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts,
+ int Lat, list<int> Res = [1], int UOps = 1,
+ int LoadLat = 4, int LoadUOps = 1> {
+ // Register variant is using a single cycle on ExePort.
+ def : WriteRes<SchedRW, ExePorts> {
+ let Latency = Lat;
+ let ReleaseAtCycles = Res;
+ let NumMicroOps = UOps;
+ }
+
+ // Memory variant also uses a cycle on port 20/21/22 and adds LoadLat cycles to
+ // the latency (default = 4).
+ def : WriteRes<SchedRW.Folded, !listconcat([LNLPPort20_21_22], ExePorts)> {
+ let Latency = !add(Lat, LoadLat);
+ let ReleaseAtCycles = !listconcat([1], Res);
+ let NumMicroOps = !add(UOps, LoadUOps);
+ }
+}
+
+defm : X86WriteResUnsupported<WriteBEXTRLd>;
+
+//===----------------------------------------------------------------------===//
+// The following definitons are infered by smg.
+//===----------------------------------------------------------------------===//
+
+def : WriteRes<WriteADC, [LNLPPort00_02_04]>;
+defm : X86WriteRes<WriteADCLd, [LNLPPort00_01_02_03_04_05, LNLPPort00_02_04], 11, [1, 1], 2>;
+def : WriteRes<WriteAESDecEnc, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 3;
+}
+defm : X86WriteRes<WriteAESDecEncLd, [LNLPVPort00_01, LNLPPort20_21_22], 11, [4, 7], 2>;
+defm : X86WriteResPairUnsupported<WriteAESIMC>;
+defm : X86WriteResPairUnsupported<WriteAESKeyGen>;
+def : WriteRes<WriteALU, [LNLPPort01_03_05]>;
+def : WriteRes<WriteALULd, [LNLPPort01_03_05, LNLPPort20_21_22]> {
+ let Latency = 11;
+}
+defm : X86WriteRes<WriteBEXTR, [LNLPPort01_03_05], 6, [2], 2>;
+def : WriteRes<WriteBLS, [LNLPPort01_03_05]>;
+defm : X86WriteRes<WriteBLSLd, [LNLPPort01_03_05, LNLPPort20_21_22], 5, [1, 4], 2>;
+defm : LNLPWriteResPair<WriteBSF, [LNLPPort01_03_05], 3, [1]>;
+defm : LNLPWriteResPair<WriteBSR, [LNLPPort01_03_05], 3, [1]>;
+def : WriteRes<WriteBSWAP32, [LNLPPort01_03_05]>;
+defm : X86WriteRes<WriteBSWAP64, [LNLPPort01_03_05, LNLPPort01_03_05], 2, [1, 1], 2>;
+defm : LNLPWriteResPair<WriteBZHI, [LNLPPort01_03_05], 3, [1]>;
+def : WriteRes<WriteBitTestSet, [LNLPPort01_03_05]>;
+def : WriteRes<WriteBitTestSetImmLd, [LNLPPort01_03_05]> {
+ let Latency = 11;
+}
+defm : X86WriteRes<WriteBitTestSetRegLd, [LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort00_02_04, LNLPPort01_03_05], 17, [3, 2, 1, 2], 8>;
+def : WriteRes<WriteBitTest, [LNLPPort01_03_05]>;
+defm : X86WriteRes<WriteBitTestImmLd, [LNLPPort01_03_05, LNLPPort20_21_22], 6, [1, 1], 2>;
+defm : X86WriteRes<WriteBitTestRegLd, [LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort20_21_22], 11, [4, 2, 1, 2, 1], 10>;
+
+def : WriteRes<WriteBlend, [LNLPVPort00_01_02_03]>;
+defm : X86WriteRes<WriteBlendLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 7, [1, 6], 2>;
+def : WriteRes<WriteBlendY, [LNLPVPort00_01_02_03]>;
+defm : X86WriteRes<WriteBlendYLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 8, [1, 7], 2>;
+
+defm : LNLPWriteResPair<WriteCLMul, [LNLPVPort02_03], 3, [1], 1, 7>;
+def : WriteRes<WriteCMOV, [LNLPPort00_01_02_03_04_05]>;
+def : WriteRes<WriteCMOVLd, [LNLPPort00_01_02_03_04_05, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 4];
+ let Latency = 5;
+}
+defm : X86WriteRes<WriteCMPXCHG, [LNLPPort00_01_02_03_04_05, LNLPPort00_02_04], 3, [3, 2], 5>;
+defm : X86WriteRes<WriteCMPXCHGRMW, [LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort20_21_22, LNLPPort10_11, LNLPPort20_21_22], 12, [1, 2, 1, 1, 1], 6>;
+
+def : WriteRes<WriteCRC32, [LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : WriteRes<WriteCRC32Ld, [LNLPPort01_03_05, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 4];
+ let Latency = 7;
+}
+
+defm : X86WriteRes<WriteCvtI2PD, [LNLPVPort00_01, LNLPVPort02_03], 5, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtI2PDLd, [LNLPVPort00_01, LNLPPort20_21_22], 11, [1,1], 2>;
+defm : X86WriteRes<WriteCvtI2PDY, [LNLPVPort00_01, LNLPVPort02_03], 7, [4, 3], 2>;
+def : WriteRes<WriteCvtI2PDYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
+def : WriteRes<WriteCvtI2PS, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteCvtI2PSLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+defm : LNLPWriteResPair<WriteCvtI2PSY, [LNLPVPort00_01], 4, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
+defm : X86WriteRes<WriteCvtI2SD, [LNLPPort01_03_05, LNLPVPort00_01], 8, [4, 4], 2>;
+def : WriteRes<WriteCvtI2SDLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+defm : X86WriteRes<WriteCvtI2SS, [LNLPPort01_03_05, LNLPVPort00_01], 8, [4, 4], 2>;
+def : WriteRes<WriteCvtI2SSLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+
+defm : LNLPWriteResPair<WriteCvtPD2I, [LNLPVPort00_01, LNLPVPort02_03], 5, [1, 1], 2, 7>;
+defm : LNLPWriteResPair<WriteCvtPD2IY, [LNLPVPort00_01, LNLPVPort02_03], 7, [1, 1], 2, 8>;
+defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
+defm : LNLPWriteResPair<WriteCvtPD2PS, [LNLPVPort00_01, LNLPVPort02_03], 5, [1, 1], 2, 7>;
+defm : LNLPWriteResPair<WriteCvtPD2PSY, [LNLPVPort00_01, LNLPVPort02_03], 7, [1, 1], 2, 8>;
+defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
+defm : X86WriteRes<WriteCvtPH2PS, [LNLPVPort00_01, LNLPVPort02_03], 5, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtPH2PSLd, [LNLPVPort00_01, LNLPPort20_21_22], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtPH2PSY, [LNLPVPort00_01, LNLPVPort02_03], 7, [4, 3], 2>;
+def : WriteRes<WriteCvtPH2PSYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;
+def : WriteRes<WriteCvtPS2I, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+defm : X86WriteRes<WriteCvtPS2ILd, [LNLPVPort00_01, LNLPPort20_21_22], 10, [4, 6], 2>;
+def : WriteRes<WriteCvtPS2IY, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteCvtPS2IYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
+defm : X86WriteRes<WriteCvtPS2PD, [LNLPVPort00_01, LNLPVPort02_03], 5, [4, 1], 2>;
+def : WriteRes<WriteCvtPS2PDLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+defm : X86WriteRes<WriteCvtPS2PDY, [LNLPVPort00_01, LNLPVPort02_03], 7, [4, 3], 2>;
+def : WriteRes<WriteCvtPS2PDYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
+defm : X86WriteRes<WriteCvtPS2PH, [LNLPVPort00_01, LNLPVPort02_03], 5, [4, 1], 2>;
+defm : X86WriteRes<WriteCvtPS2PHSt, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 5, [4, 1, 1], 2>;
+defm : X86WriteRes<WriteCvtPS2PHY, [LNLPVPort00_01, LNLPVPort02_03], 7, [4, 3], 2>;
+defm : X86WriteRes<WriteCvtPS2PHYSt, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 5, [4, 1, 1], 3>;
+defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
+defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
+defm : X86WriteRes<WriteCvtSD2I, [LNLPVPort00_01], 7, [7], 2>;
+defm : X86WriteRes<WriteCvtSD2ILd, [LNLPVPort00_01, LNLPPort20_21_22], 11, [7, 4], 3>;
+defm : X86WriteRes<WriteCvtSD2SS, [LNLPVPort00_01, LNLPVPort02_03], 5, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtSD2SSLd, [LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22], 11, [4, 1, 6], 3>;
+defm : X86WriteRes<WriteCvtSS2I, [LNLPVPort00_01], 7, [7], 2>;
+defm : X86WriteRes<WriteCvtSS2ILd, [LNLPVPort00_01, LNLPPort20_21_22], 11, [7, 4], 2>;
+defm : X86WriteRes<WriteCvtSS2SD, [LNLPVPort00_01, LNLPVPort02_03], 5, [4, 1], 2>;
+def : WriteRes<WriteCvtSS2SDLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+defm : X86WriteRes<WriteDPPD, [LNLPVPort00_01, LNLPVPort02_03], 8, [2, 1], 3>;
+defm : X86WriteRes<WriteDPPDLd, [LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22], 13, [2, 1, 1], 4>;
+//defm : X86WriteRes<WriteDPPS, [LNLPVPort00_01, LNLPVPort02_03], 99, [7, 5], 5>;
+// FIXME: Incompleted schedwrite.
+//defm : X86WriteResUnsupported<WriteDPPSLd>;
+defm : LNLPWriteResPair<WriteDPPS, [LNLPVPort00_01, LNLPVPort02_03, LNLPVPort02_03, LNLPVPort02_03, LNLPVPort00_01], 11, [2, 1, 1, 1, 1], 5, 7>;
+//defm : X86WriteRes<WriteDPPSY, [LNLPVPort00_01, LNLPVPort02_03], 12, [7, 5], 5>;
+// FIXME: Incompleted schedwrite.
+//defm : X86WriteResUnsupported<WriteDPPSYLd>;
+defm : LNLPWriteResPair<WriteDPPSY, [LNLPVPort00_01, LNLPVPort02_03, LNLPVPort02_03, LNLPVPort02_03, LNLPVPort00_01], 12, [2, 1, 1, 1, 1], 5, 7>;
+
+defm : LNLPWriteResPair<WriteDiv16, [LNLPPort00_01_02_03_04_05, LNLPPort01], 16, [1, 3], 4, 4>;
+defm : LNLPWriteResPair<WriteDiv32, [LNLPPort00_01_02_03_04_05, LNLPPort01], 15, [1, 3], 4, 4>;
+defm : LNLPWriteResPair<WriteDiv64, [LNLPPort01], 18, [3], 3>;
+defm : X86WriteRes<WriteDiv8, [LNLPPort01], 17, [3], 3>;
+defm : X86WriteRes<WriteDiv8Ld, [LNLPPort01], 22, [3], 3>;
+defm : X86WriteRes<WriteEMMS, [LNLPPort01, LNLPVPort00_01, LNLPVPort02_03], 10, [1, 8, 1], 10>;
+def : WriteRes<WriteFAdd, [LNLPVPort02_03]> {
+ let Latency = 2;
+}
+// FIXME: Latency
+defm : X86WriteRes<WriteFAddLd, [LNLPVPort02_03, LNLPPort20_21_22], 10, [1,1], 2>; // 8
+defm : LNLPWriteResPair<WriteFAdd64, [LNLPVPort02_03], 3, [1], 1, 7>;
+defm : LNLPWriteResPair<WriteFAdd64X, [LNLPVPort02_03], 3, [1], 1, 7>;
+defm : LNLPWriteResPair<WriteFAdd64Y, [LNLPVPort02_03], 3, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
+defm : LNLPWriteResPair<WriteFAddX, [LNLPVPort02_03], 3, [1], 1, 7>;
+defm : LNLPWriteResPair<WriteFAddY, [LNLPVPort02_03], 3, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFAddZ>;
+def : WriteRes<WriteFBlend, [LNLPVPort00_01_02_03]>;
+defm : X86WriteRes<WriteFBlendLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 7, [1, 6], 2>;
+def : WriteRes<WriteFBlendY, [LNLPVPort00_01_02_03]>;
+defm : X86WriteRes<WriteFBlendYLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 8, [1, 7], 2>;
+def : WriteRes<WriteFCMOV, [LNLPVPort00_01]> {
+ let Latency = 3;
+}
+def : WriteRes<WriteFCmp, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteFCmpLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes<WriteFCmp64, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteFCmp64Ld, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes<WriteFCmp64X, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteFCmp64XLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes<WriteFCmp64Y, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteFCmp64YLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
+def : WriteRes<WriteFCmpX, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteFCmpXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes<WriteFCmpY, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteFCmpYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported<WriteFCmpZ>;
+def : WriteRes<WriteFCom, [LNLPVPort00_01]>;
+defm : X86WriteRes<WriteFComLd, [LNLPVPort00_01, LNLPPort20_21_22], 8, [1, 1], 2>;
+def : WriteRes<WriteFComX, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+defm : X86WriteRes<WriteFComXLd, [LNLPVPort00_01, LNLPPort20_21_22], 9, [3, 6], 2>;
+def : WriteRes<WriteFDiv, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [7];
+ let Latency = 7;
+}
+def : WriteRes<WriteFDivLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [7, 6];
+ let Latency = 13;
+}
+def : WriteRes<WriteFDiv64, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [10];
+ let Latency = 10;
+}
+def : WriteRes<WriteFDiv64Ld, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [10, 6];
+ let Latency = 16;
+}
+def : WriteRes<WriteFDiv64X, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [10];
+ let Latency = 10;
+}
+def : WriteRes<WriteFDiv64XLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [10, 6];
+ let Latency = 16;
+}
+def : WriteRes<WriteFDiv64Y, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [10];
+ let Latency = 10;
+}
+def : WriteRes<WriteFDiv64YLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [10, 7];
+ let Latency = 17;
+}
+defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
+def : WriteRes<WriteFDivX, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [7];
+ let Latency = 7;
+}
+def : WriteRes<WriteFDivXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [7, 6];
+ let Latency = 13;
+}
+def : WriteRes<WriteFDivY, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [7];
+ let Latency = 7;
+}
+def : WriteRes<WriteFDivYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [7, 7];
+ let Latency = 14;
+}
+defm : X86WriteResPairUnsupported<WriteFDivZ>;
+defm : X86WriteRes<WriteFHAdd, [LNLPVPort02_03], 4, [5], 3>;
+defm : X86WriteRes<WriteFHAddLd, [LNLPVPort02_03, LNLPPort20_21_22], 10, [5, 6], 4>;
+defm : X86WriteRes<WriteFHAddY, [LNLPVPort02_03], 4, [5], 3>;
+defm : X86WriteRes<WriteFHAddYLd, [LNLPVPort02_03, LNLPPort20_21_22], 11, [5, 7], 4>;
+def : WriteRes<WriteFLD0, [LNLPVPort02_03]>;
+defm : X86WriteRes<WriteFLD1, [LNLPVPort02_03], 1, [2], 2>;
+defm : X86WriteRes<WriteFLDC, [LNLPVPort02_03], 1, [2], 2>;
+
+def : WriteRes<WriteFLoad, [LNLPPort20_21_22]> {
+ let Latency = 7;
+}
+def : WriteRes<WriteFLoadX, [LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [6];
+ let Latency = 7;
+}
+def : WriteRes<WriteFLoadY, [LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [7];
+ let Latency = 8;
+}
+def : WriteRes<WriteFLogic, [LNLPVPort00_01_02_03]>;
+def : WriteRes<WriteFLogicLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 6];
+ let Latency = 7;
+}
+def : WriteRes<WriteFLogicY, [LNLPVPort00_01_02_03]>;
+def : WriteRes<WriteFLogicYLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 7];
+ let Latency = 8;
+}
+defm : X86WriteResPairUnsupported<WriteFLogicZ>;
+def : WriteRes<WriteFMA, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteFMALd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes<WriteFMAX, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteFMAXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes<WriteFMAY, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteFMAYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported<WriteFMAZ>;
+def : WriteRes<WriteFMOVMSK, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+
+defm : X86WriteRes<WriteFMaskedLoad, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 8, [1, 1], 2>;
+defm : X86WriteRes<WriteFMaskedLoadY, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 9, [1, 1], 2>;
+defm : X86WriteRes<WriteFMaskedStore32, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 14, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteFMaskedStore32Y, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 14, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteFMaskedStore64, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 14, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteFMaskedStore64Y, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 14, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteFMoveX, [], 1, [], 0>;
+defm : X86WriteRes<WriteFMoveY, [], 1, [], 0>;
+defm : X86WriteResUnsupported<WriteFMoveZ>;
+def : WriteRes<WriteFMul, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : WriteRes<WriteFMulLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 6];
+ let Latency = 9;
+}
+def : WriteRes<WriteFMul64, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : WriteRes<WriteFMul64Ld, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 6];
+ let Latency = 9;
+}
+def : WriteRes<WriteFMul64X, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : WriteRes<WriteFMul64XLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 6];
+ let Latency = 9;
+}
+def : WriteRes<WriteFMul64Y, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : WriteRes<WriteFMul64YLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 7];
+ let Latency = 10;
+}
+defm : X86WriteResPairUnsupported<WriteFMul64Z>;
+def : WriteRes<WriteFMulX, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : WriteRes<WriteFMulXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 6];
+ let Latency = 9;
+}
+def : WriteRes<WriteFMulY, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : WriteRes<WriteFMulYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 7];
+ let Latency = 10;
+}
+defm : X86WriteResPairUnsupported<WriteFMulZ>;
+def : WriteRes<WriteFRcp, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteFRcpLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes<WriteFRcpX, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteFRcpXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes<WriteFRcpY, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteFRcpYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported<WriteFRcpZ>;
+defm : X86WriteRes<WriteFRnd, [LNLPVPort00_01], 8, [8], 2>;
+defm : X86WriteRes<WriteFRndLd, [LNLPVPort00_01, LNLPPort20_21_22], 14, [8, 6], 3>;
+defm : X86WriteRes<WriteFRndY, [LNLPVPort00_01], 8, [8], 2>;
+defm : X86WriteRes<WriteFRndYLd, [LNLPVPort00_01, LNLPPort20_21_22], 15, [8, 7], 3>;
+defm : X86WriteResPairUnsupported<WriteFRndZ>;
+def : WriteRes<WriteFRsqrt, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteFRsqrtLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes<WriteFRsqrtX, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteFRsqrtXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes<WriteFRsqrtY, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteFRsqrtYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
+
+defm : LNLPWriteResPair<WriteFShuffle, [LNLPVPort02_03], 1, [1], 1, 7>;
+defm : LNLPWriteResPair<WriteFShuffle256, [LNLPVPort02_03], 3, [1], 1, 8>;
+defm : LNLPWriteResPair<WriteFShuffleY, [LNLPVPort02_03], 1, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
+def : WriteRes<WriteFSign, [LNLPVPort00_01]>;
+def : WriteRes<WriteFSqrt, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [10];
+ let Latency = 10;
+}
+def : WriteRes<WriteFSqrtLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [10, 6];
+ let Latency = 16;
+}
+def : WriteRes<WriteFSqrt64, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [15];
+ let Latency = 15;
+}
+def : WriteRes<WriteFSqrt64Ld, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [15, 6];
+ let Latency = 21;
+}
+def : WriteRes<WriteFSqrt64X, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [15];
+ let Latency = 15;
+}
+def : WriteRes<WriteFSqrt64XLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [15, 6];
+ let Latency = 21;
+}
+def : WriteRes<WriteFSqrt64Y, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [15];
+ let Latency = 15;
+}
+def : WriteRes<WriteFSqrt64YLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [15, 7];
+ let Latency = 22;
+}
+defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
+def : WriteRes<WriteFSqrt80, [LNLPPortInvalid, LNLPVPort00_01]> {
+ let ReleaseAtCycles = [7, 1];
+ let Latency = 21;
+}
+def : WriteRes<WriteFSqrtX, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [10];
+ let Latency = 10;
+}
+def : WriteRes<WriteFSqrtXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [10, 6];
+ let Latency = 16;
+}
+def : WriteRes<WriteFSqrtY, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [10];
+ let Latency = 10;
+}
+def : WriteRes<WriteFSqrtYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [10, 7];
+ let Latency = 17;
+}
+defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
+defm : X86WriteRes<WriteFStore, [LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1], 2>;
+defm : X86WriteResUnsupported<WriteFStoreNT>;
+defm : X86WriteRes<WriteFStoreNTX, [LNLPPort10_11, LNLPPort25_26_27], 518, [1, 1], 2>;
+defm : X86WriteRes<WriteFStoreNTY, [LNLPPort10_11, LNLPPort25_26_27], 542, [1, 1], 2>;
+defm : X86WriteRes<WriteFStoreX, [LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteFStoreY, [LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1], 2>;
+defm : LNLPWriteResPair<WriteFTest, [LNLPVPort00_01], 3, [1]>;
+defm : LNLPWriteResPair<WriteFTestY, [LNLPVPort00_01], 5, [1], 1, 6>;
+defm : LNLPWriteResPair<WriteFVarBlend, [LNLPVPort00_01_02_03], 1, [1], 1, 7>;
+defm : LNLPWriteResPair<WriteFVarBlendY, [LNLPVPort00_01_02_03], 3, [3], 3, 7>;
+defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
+defm : LNLPWriteResPair<WriteFVarShuffle, [LNLPVPort02_03], 1, [1], 1, 7>;
+defm : LNLPWriteResPair<WriteFVarShuffle256, [LNLPVPort02_03], 3, [1], 1, 8>;
+defm : LNLPWriteResPair<WriteFVarShuffleY, [LNLPVPort02_03], 1, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
+defm : X86WriteRes<WriteFence, [LNLPPort10_11, LNLPPort25_26_27], 2, [1, 1], 2>;
+defm : LNLPWriteResPair<WriteIDiv16, [LNLPPort00_01_02_03_04_05, LNLPPort01_03_05], 16, [1, 3], 4, 4>;
+defm : LNLPWriteResPair<WriteIDiv32, [LNLPPort00_01_02_03_04_05, LNLPPort01_03_05], 15, [1, 3], 4, 4>;
+defm : LNLPWriteResPair<WriteIDiv64, [LNLPPort01_03_05], 18, [3], 3>;
+defm : X86WriteRes<WriteIDiv8, [LNLPPort01_03_05], 17, [3], 3>;
+defm : X86WriteRes<WriteIDiv8Ld, [LNLPPort01_03_05], 22, [3], 3>;
+defm : LNLPWriteResPair<WriteIMul16, [LNLPPort01_03_05, LNLPPort00_02_04], 5, [2, 1], 4>;
+defm : LNLPWriteResPair<WriteIMul16Imm, [LNLPPort01_03_05, LNLPPort00_01_02_03_04_05], 4, [1, 1], 2>;
+defm : LNLPWriteResPair<WriteIMul16Reg, [LNLPPort01_03_05], 3, [1]>;
+defm : LNLPWriteResPair<WriteIMul32, [LNLPPort01_03_05, LNLPPort00_02_04], 4, [1, 1], 3>;
+defm : LNLPWriteResPair<WriteIMul32Imm, [LNLPPort01_03_05, LNLPPort00_01_02_03_04_05], 2, [1, 1]>;
+defm : LNLPWriteResPair<WriteIMul32Reg, [LNLPPort01_03_05], 3, [1]>;
+defm : LNLPWriteResPair<WriteIMul64, [LNLPPort01_03_05, LNLPPort00_02_04], 4, [1, 1], 2>;
+defm : LNLPWriteResPair<WriteIMul64Imm, [LNLPPort01_03_05, LNLPPort00_01_02_03_04_05], 2, [1, 1]>;
+defm : LNLPWriteResPair<WriteIMul64Reg, [LNLPPort01_03_05], 3, [1]>;
+defm : LNLPWriteResPair<WriteIMul8, [LNLPPort01_03_05], 3, [1]>;
+def : WriteRes<WriteIMulH, []> {
+ let Latency = 3; // 4
+}
+def : WriteRes<WriteIMulHLd, []> {
+ let Latency = 3;
+}
+def : WriteRes<WriteJump, [LNLPPort00_02_04]>;
+defm : X86WriteRes<WriteJumpLd, [LNLPPort00_02_04, LNLPPort20_21_22], 6, [1, 1], 2>;
+defm : X86WriteResUnsupported<WriteLAHFSAHF>;
+defm : X86WriteRes<WriteLDMXCSR, [LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPVPort02_03, LNLPPort25_26_27], 7, [1, 1, 1, 1], 4>;
+def : WriteRes<WriteLEA, [LNLPPort01]>;
+defm : LNLPWriteResPair<WriteLZCNT, [LNLPPort01], 3, [1]>;
+def : WriteRes<WriteLoad, [LNLPPort20_21_22]> {
+ let Latency = 4;
+}
+def : WriteRes<WriteMMXMOVMSK, [LNLPVPort00_01]> {
+ let Latency = 3 ;
+}
+defm : LNLPWriteResPair<WriteMPSAD, [LNLPVPort02_03, LNLPVPort02_03], 4, [1, 1], 2, 7>;
+defm : LNLPWriteResPair<WriteMPSADY, [LNLPVPort02_03, LNLPVPort02_03], 4, [1, 1], 2, 8>;
+defm : LNLPWriteResPair<WriteMULX32, [LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort01_03_05], 4, [1, 1, 1], 2>;
+defm : LNLPWriteResPair<WriteMULX64, [LNLPPort01_03_05, LNLPPort01_03_05], 4, [1, 1]>;
+// FIXME: Incompleted schedwrite.
+def : WriteRes<WriteMicrocoded, [LNLPPort00_01_02_03_04_05]> {
+ let Latency = LunarlakePModel.MaxLatency;
+}
+def : WriteRes<WriteMove, [LNLPPort00_01_02_03_04_05]>;
+defm : X86WriteRes<WriteNop, [], 1, [], 0>;
+defm : X86WriteRes<WritePCmpEStrI, [LNLPPort00, LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort01_03_05], 16, [3, 2, 1, 1, 1], 8>;
+defm : X86WriteRes<WritePCmpEStrILd, [LNLPPort00, LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort01_03_05], 31, [3, 1, 1, 1, 1, 1], 8>;
+defm : X86WriteRes<WritePCmpEStrM, [LNLPPort00, LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort01_03_05, LNLPPort01_03_05], 16, [3, 3, 1, 1, 1], 9>;
+defm : X86WriteRes<WritePCmpEStrMLd, [LNLPPort00, LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort01_03_05], 17, [3, 2, 1, 1, 1, 1], 9>;
+defm : LNLPWriteResPair<WritePCmpIStrI, [LNLPPort00], 11, [3], 3, 20>;
+defm : LNLPWriteResPair<WritePCmpIStrM, [LNLPPort00], 11, [3], 3>;
+defm : LNLPWriteResPair<WritePHAdd, [LNLPVPort00_01_02_03, LNLPVPort02_03], 3, [1, 2], 3, 8>;
+defm : LNLPWriteResPair<WritePHAddX, [LNLPVPort00_01_02_03, LNLPVPort02_03], 2, [1, 2], 3, 7>;
+defm : LNLPWriteResPair<WritePHAddY, [LNLPVPort00_01_02_03, LNLPVPort02_03], 2, [1, 2], 3, 8>;
+def : WriteRes<WritePHMINPOS, [LNLPVPort00_01]> {
+ let Latency = 5;
+}
+def : WriteRes<WritePHMINPOSLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let Latency = 11;
+}
+
+// FIXME : uops info is incorrect
+defm : LNLPWriteResPair<WritePMULLD, [LNLPVPort00_01_02_03], 10, [2], 2, 8>;
+defm : LNLPWriteResPair<WritePMULLDY, [LNLPVPort00_01_02_03], 10, [2], 2, 8>;
+defm : X86WriteResPairUnsupported<WritePMULLDZ>;
+defm : LNLPWriteResPair<WritePOPCNT, [LNLPPort01_03_05], 3, [1]>;
+defm : LNLPWriteResPair<WritePSADBW, [LNLPVPort02_03], 3, [1], 1, 8>;
+defm : LNLPWriteResPair<WritePSADBWX, [LNLPVPort02_03], 3, [1], 1, 7>;
+defm : LNLPWriteResPair<WritePSADBWY, [LNLPVPort02_03], 3, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WritePSADBWZ>;
+defm : X86WriteRes<WriteRMW, [LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27], 1, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteRotate, [LNLPPort00_01_02_03_04_05, LNLPPort01_03_05], 2, [1, 2], 3>;
+defm : X86WriteRes<WriteRotateLd, [LNLPPort00_01_02_03_04_05, LNLPPort01_03_05], 12, [1, 2], 3>;
+defm : X86WriteRes<WriteRotateCL, [LNLPPort01_03_05], 2, [2], 2>;
+defm : X86WriteRes<WriteRotateCLLd, [LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort01_03_05], 19, [2, 3, 2], 7>;
+defm : X86WriteRes<WriteSETCC, [LNLPPort01_03_05], 2, [2], 2>;
+defm : X86WriteRes<WriteSETCCStore, [LNLPPort01_03_05, LNLPPort10_11, LNLPPort25_26_27], 13, [2, 1, 1], 4>;
+defm : X86WriteRes<WriteSHDmrcl, [LNLPPort00_01_02_03_04_05,LNLPPort01_03_05 , LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1, 1, 1, 1, 1], 6>;
+defm : X86WriteRes<WriteSHDmri, [LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1, 1, 1, 1], 5>;
+defm : X86WriteRes<WriteSHDrrcl, [LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort01_03_05], 5, [1, 1, 1], 3>;
+def : WriteRes<WriteSHDrri, [LNLPPort01_03_05]> {
+ let Latency = 3;
+}
+defm : X86WriteRes<WriteSTMXCSR, [LNLPPort00_02_04, LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], LunarlakePModel.MaxLatency, [1, 6, 1, 1], 4>;
+def : WriteRes<WriteShift, [LNLPPort01_03_05]>;
+defm : X86WriteRes<WriteShiftLd, [LNLPPort01_03_05, LNLPPort20_21_22], 5, [1, 4], 2>;
+defm : X86WriteRes<WriteShiftCL, [LNLPPort00_02_04], 2, [2], 2>;
+defm : X86WriteRes<WriteShiftCLLd, [LNLPPort00_02_04], 12, [2], 2>;
+defm : LNLPWriteResPair<WriteShuffle, [LNLPVPort02_03], 1, [1], 1, 8>;
+defm : LNLPWriteResPair<WriteShuffle256, [LNLPVPort02_03], 3, [1], 1, 8>;
+defm : LNLPWriteResPair<WriteShuffleX, [LNLPVPort02_03], 1, [1], 1, 7>;
+defm : LNLPWriteResPair<WriteShuffleY, [LNLPVPort02_03], 1, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteShuffleZ>;
+defm : X86WriteRes<WriteStore, [LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteStoreNT, [LNLPPort10_11, LNLPPort25_26_27], 512, [1, 1], 2>;
+def : WriteRes<WriteSystem, [LNLPPort00_01_02_03_04_05]> {
+ let Latency = LunarlakePModel.MaxLatency;
+}
+def : WriteRes<WriteTZCNT, [LNLPPort01_03_05]> {
+ let Latency = 3;
+}
+def : WriteRes<WriteTZCNTLd, [LNLPPort01_03_05, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 4];
+ let Latency = 7;
+}
+def : WriteRes<WriteVPMOV256, [LNLPVPort02_03]> {
+ let Latency = 3;
+}
+defm : X86WriteRes<WriteVPMOV256Ld, [LNLPVPort02_03, LNLPPort20_21_22], 10, [3, 7], 2>;
+defm : X86WriteRes<WriteVarBlend, [LNLPVPort00_01_02_03], 3, [3], 3>;
+defm : X86WriteRes<WriteVarBlendLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 8, [3, 6], 4>;
+defm : X86WriteRes<WriteVarBlendY, [LNLPVPort00_01_02_03], 3, [3], 3>;
+defm : X86WriteRes<WriteVarBlendYLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 9, [3, 7], 4>;
+defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
+defm : LNLPWriteResPair<WriteVarShuffle, [LNLPVPort02_03, LNLPVPort00_01], 3, [1, 1], 2, 8>;
+def : WriteRes<WriteVarShuffle256, [LNLPVPort02_03]> {
+ let Latency = 3;
+}
+def : WriteRes<WriteVarShuffle256Ld, [LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 7];
+ let Latency = 10;
+}
+def : WriteRes<WriteVarShuffleX, [LNLPVPort02_03]>;
+defm : X86WriteRes<WriteVarShuffleXLd, [LNLPVPort02_03, LNLPPort20_21_22], 7, [1, 6], 2>;
+def : WriteRes<WriteVarShuffleY, [LNLPVPort02_03]>;
+defm : X86WriteRes<WriteVarShuffleYLd, [LNLPVPort02_03, LNLPPort20_21_22], 8, [1, 7], 2>;
+defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
+
+def : WriteRes<WriteVarVecShift, [LNLPVPort00_01]>;
+def : WriteRes<WriteVarVecShiftLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 6];
+ let Latency = 7;
+}
+def : WriteRes<WriteVarVecShiftY, [LNLPVPort00_01]>;
+def : WriteRes<WriteVarVecShiftYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 7];
+ let Latency = 8;
+}
+defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
+defm : LNLPWriteResPair<WriteVecALU, [LNLPVPort00], 1, [1], 1, 8>; // 4 ports ?
+def : WriteRes<WriteVecALUX, [LNLPVPort00_01]>;
+def : WriteRes<WriteVecALUXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 6];
+ let Latency = 7;
+}
+def : WriteRes<WriteVecALUY, [LNLPVPort00_01]>;
+def : WriteRes<WriteVecALUYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 7];
+ let Latency = 8;
+}
+defm : X86WriteResPairUnsupported<WriteVecALUZ>;
+defm : X86WriteRes<WriteVecExtract, [LNLPVPort00_01, LNLPVPort02_03], 4, [3, 1], 2>;
+defm : X86WriteRes<WriteVecExtractSt, [LNLPVPort02_03, LNLPPort10_11, LNLPPort25_26_27], 2, [1, 1, 1], 2>;
+defm : LNLPWriteResPair<WriteVecIMul, [LNLPVPort00_01], 5, [1], 1, 8>;
+def : WriteRes<WriteVecIMulX, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteVecIMulXLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : WriteRes<WriteVecIMulY, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+}
+def : WriteRes<WriteVecIMulYLd, [LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+}
+defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
+defm : X86WriteRes<WriteVecInsert, [LNLPPort01_03_05, LNLPVPort02_03], 5, [4, 1], 2>;
+defm : X86WriteRes<WriteVecInsertLd, [LNLPVPort02_03, LNLPPort20_21_22], 7, [1, 6], 2>;
+def : WriteRes<WriteVecLoad, [LNLPPort20_21_22]> {
+ let Latency = 6;
+}
+// FIXME: Incompleted schedwrite.
+def : WriteRes<WriteVecLoadNT, [LNLPPort20_21_22]> {
+ let Latency = 7;
+}
+// FIXME: Incompleted schedwrite.
+def : WriteRes<WriteVecLoadNTY, [LNLPPort20_21_22]> {
+ let Latency = 8;
+}
+
+def : WriteRes<WriteVecLoadX, [LNLPPort20_21_22]> {
+ let Latency = 6;
+}
+def : WriteRes<WriteVecLoadY, [LNLPPort20_21_22]> {
+ let Latency = 7;
+}
+defm : LNLPWriteResPair<WriteVecLogic, [LNLPVPort00_01_02_03], 1, [1], 1, 8>;
+def : WriteRes<WriteVecLogicX, [LNLPVPort00_01_02_03]>;
+def : WriteRes<WriteVecLogicXLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 6];
+ let Latency = 7;
+}
+def : WriteRes<WriteVecLogicY, [LNLPVPort00_01_02_03]>;
+def : WriteRes<WriteVecLogicYLd, [LNLPVPort00_01_02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 7];
+ let Latency = 8;
+}
+defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
+def : WriteRes<WriteVecMOVMSK, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : WriteRes<WriteVecMOVMSKY, [LNLPVPort00_01]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 3; // Tool added Max
+}
+defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;
+defm : X86WriteRes<WriteVecMaskedLoad, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 7, [1, 6], 2>;
+defm : X86WriteRes<WriteVecMaskedLoadY, [LNLPVPort00_01_02_03, LNLPPort20_21_22], 8, [1, 7], 2>;
+defm : X86WriteRes<WriteVecMaskedStore32, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 14, [1, 1, 1], 3>; // updated lat from 3 to 14
+defm : X86WriteRes<WriteVecMaskedStore32Y, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 14, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteVecMaskedStore64, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 14, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteVecMaskedStore64Y, [LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27], 14, [1, 1, 1], 3>;
+def : WriteRes<WriteVecMove, [LNLPVPort00_01_02_03]>;
+def : WriteRes<WriteVecMoveFromGpr, [LNLPPort01_03_05]> {
+ let Latency = 3; // Originally 4
+}
+def : WriteRes<WriteVecMoveToGpr, [LNLPVPort00_01]> {
+ let Latency = 3;
+}
+defm : X86WriteRes<WriteVecMoveX, [LNLPVPort00_01_02_03], 1, [2], 2>;
+defm : X86WriteRes<WriteVecMoveY, [], 1, [], 0>;
+defm : X86WriteResUnsupported<WriteVecMoveZ>;
+defm : LNLPWriteResPair<WriteVecShift, [LNLPVPort00_01], 1, [1], 1, 8>;
+def : WriteRes<WriteVecShiftImm, [LNLPVPort00_01]>;
+def : WriteRes<WriteVecShiftImmX, [LNLPVPort00_01]>;
+defm : X86WriteResUnsupported<WriteVecShiftImmXLd>;
+def : WriteRes<WriteVecShiftImmY, [LNLPVPort00_01]>;
+defm : X86WriteResUnsupported<WriteVecShiftImmYLd>;
+defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
+defm : X86WriteRes<WriteVecShiftX, [LNLPVPort00_01, LNLPVPort02_03], 2, [1, 1], 2>;
+defm : X86WriteRes<WriteVecShiftXLd, [LNLPVPort00_01, LNLPPort20_21_22], 8, [1, 1], 2>; // 7
+defm : X86WriteRes<WriteVecShiftY, [LNLPVPort00_01, LNLPVPort02_03], 4, [1, 1], 2>;
+defm : X86WriteRes<WriteVecShiftYLd, [LNLPVPort00_01, LNLPPort20_21_22], 9, [1, 7], 2>; // 8
+defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
+defm : X86WriteRes<WriteVecStore, [LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteVecStoreNT, [LNLPPort10_11, LNLPPort25_26_27], 511, [1, 1], 2>; // historic value
+defm : X86WriteRes<WriteVecStoreNTY, [LNLPPort10_11, LNLPPort25_26_27], 507, [1, 1], 2>;
+defm : X86WriteRes<WriteVecStoreX, [LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteVecStoreY, [LNLPPort10_11, LNLPPort25_26_27], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteVecTest, [LNLPVPort00_01, LNLPVPort02_03], 4, [1, 1], 2>;
+defm : X86WriteRes<WriteVecTestLd, [LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22], 10, [3, 1, 6], 3>;
+defm : X86WriteRes<WriteVecTestY, [LNLPVPort00_01, LNLPVPort02_03], LunarlakePModel.MaxLatency, [3, 1], 2>;
+defm : X86WriteRes<WriteVecTestYLd, [LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22], 11, [3, 1, 6], 3>;
+defm : X86WriteRes<WriteXCHG, [LNLPPort00_01_02_03_04_05], 2, [3], 3>;
+def : WriteRes<WriteZero, []>;
+
+// Manual Regressive SchedWriteRes and InstRW Definition. Suffix with "_X"
+// All _X(N) prefix sequence are defs used from prev. generation to bypass incomplete data.
+def LNLPWriteResGroupX0 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22, LNLPPort20_21_22, LNLPPort10_11]> {
+ let Latency = 7;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX0], (instregex "^AA(D|N)D64mr$",
+ "^A(X?)OR64mr$")>;
+def LNLPWriteResGroupX1 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [2, 1, 1, 1, 1];
+ let Latency = 12;
+ let NumMicroOps = 6;
+}
+def : InstRW<[LNLPWriteResGroupX1, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(16|32|64)mr$")>;
+def LNLPWriteResGroupX2 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort20_21_22]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX2], (instregex "^JMP(16|32|64)m((_NT)?)$",
+ "^RET(16|32)$",
+ "^RORX(32|64)mi$")>;
+def : InstRW<[LNLPWriteResGroupX2, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)rm$",
+ "^AD(C|O)X(32|64)rm$")>;
+def LNLPWriteResGroupX5 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX5], (instregex "^CMP(8|16|32)mi$",
+ "^CMP(8|16|32|64)mi8$",
+ "^MOV(8|16)rm$",
+ "^POP(16|32)r((mr)?)$")>;
+def : InstRW<[LNLPWriteResGroupX5], (instrs CMP64mi32,
+ MOV8rm_NOREX,
+ MOVZX16rm8)>;
+def : InstRW<[LNLPWriteResGroupX5, ReadAfterLd], (instregex "^(ADD|CMP|SUB)(8|16|32|64)rm$",
+ "^AND(8|16|32)rm$",
+ "^(X?)OR(8|16|32)rm$")>;
+def : InstRW<[LNLPWriteResGroupX5, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^CMP(8|16|32|64)mr$")>;
+def LNLPWriteResGroupX6 : SchedWriteRes<[]> {
+ let NumMicroOps = 0;
+}
+def : InstRW<[LNLPWriteResGroupX6], (instregex "^(ADD|SUB)64ri8$",
+ "^(DE|IN)C64r$",
+ "^MOV64rr((_REV)?)$")>;
+def : InstRW<[LNLPWriteResGroupX6], (instrs CLC,
+ JMP_2)>;
+def LNLPWriteResGroupX7 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 13;
+ let NumMicroOps = 4;
+}
+def : InstRW<[LNLPWriteResGroupX7], (instregex "^A(D|N)D8mi(8?)$",
+ "^(DE|IN)C8m$",
+ "^N(EG|OT)8m$",
+ "^(X?)OR8mi(8?)$",
+ "^SUB8mi(8?)$")>;
+def : InstRW<[LNLPWriteResGroupX7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^A(D|N)D8mr$",
+ "^(X?)OR8mr$")>;
+def : InstRW<[LNLPWriteResGroupX7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs SUB8mr)>;
+def LNLPWriteResGroupX8 : SchedWriteRes<[LNLPPort01_03_05]> {
+ let Latency = 3;
+}
+def : InstRW<[LNLPWriteResGroupX8], (instregex "^(V?)(ADD|SUB)SSrr((_Int)?)$")>;
+def LNLPWriteResGroupX9 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort01_03_05]> {
+ let Latency = 10;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX9], (instregex "^ADD_F(32|64)m$",
+ "^ILD_F(16|32|64)m$",
+ "^SUB(R?)_F(32|64)m$")>;
+def LNLPWriteResGroupX10 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [1, 2];
+ let Latency = 13;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX10], (instregex "^ADD_FI(16|32)m$",
+ "^SUB(R?)_FI(16|32)m$")>;
+
+def LNLPWriteResGroupX11 : SchedWriteRes<[LNLPPort00_01_02_03_04_05]> {
+ let Latency = 2;
+}
+def : InstRW<[LNLPWriteResGroupX11], (instregex "^AND(8|16|32|64)r(r|i8)$",
+ "^AND(8|16|32|64)rr_REV$",
+ "^(AND|TEST)(32|64)i32$",
+ "^(AND|TEST)(8|32)ri$",
+ "^(AND|TEST)64ri32$",
+ "^(AND|TEST)8i8$",
+ "^(X?)OR(8|16|32|64)r(r|i8)$",
+ "^(X?)OR(8|16|32|64)rr_REV$",
+ "^(X?)OR(32|64)i32$",
+ "^(X?)OR(8|32)ri$",
+ "^(X?)OR64ri32$",
+ "^(X?)OR8i8$",
+ "^TEST(8|16|32|64)rr$")>;
+def : InstRW<[LNLPWriteResGroupX11], (instrs XOR8rr_NOREX)>;
+def LNLPWriteResGroupX12 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22]> {
+ let Latency = 7;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX12], (instregex "^TEST(8|16|32)mi$")>;
+def : InstRW<[LNLPWriteResGroupX12], (instrs TEST64mi32)>;
+def : InstRW<[LNLPWriteResGroupX12, ReadAfterLd], (instregex "^(X?)OR64rm$")>;
+def : InstRW<[LNLPWriteResGroupX12, ReadAfterLd], (instrs AND64rm)>;
+def : InstRW<[LNLPWriteResGroupX12, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^TEST(8|16|32|64)mr$")>;
+def LNLPWriteResGroupX13 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort20_21_22]> {
+ let Latency = 7;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX13, ReadAfterLd], (instregex "^ANDN(32|64)rm$")>;
+def LNLPWriteResGroupX14 : SchedWriteRes<[LNLPPort01_03_05]> {
+ let Latency = 2;
+}
+def : InstRW<[LNLPWriteResGroupX14], (instregex "^ANDN(32|64)rr$")>;
+def LNLPWriteResGroupX15 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [5, 2, 1, 1];
+ let Latency = 10;
+ let NumMicroOps = 9;
+}
+def : InstRW<[LNLPWriteResGroupX15], (instrs BT64mr)>;
+def LNLPWriteResGroupX16 : SchedWriteRes<[LNLPPort01]> {
+ let Latency = 3;
+}
+def : InstRW<[LNLPWriteResGroupX16], (instregex "^BT((C|R|S)?)64rr$")>;
+def LNLPWriteResGroupX17 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [4, 2, 1, 1, 1, 1];
+ let Latency = 17;
+ let NumMicroOps = 10;
+}
+def : InstRW<[LNLPWriteResGroupX17], (instregex "^BT(C|R|S)64mr$")>;
+def LNLPWriteResGroupX18 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 7;
+ let NumMicroOps = 5;
+}
+def : InstRW<[LNLPWriteResGroupX18], (instregex "^CALL(16|32|64)m((_NT)?)$")>;
+
+def LNLPWriteResGroupX19 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 3;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX19], (instregex "^CALL(16|32|64)r((_NT)?)$")>;
+
+def LNLPWriteResGroupX20 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 3;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX20], (instrs CALL64pcrel32,
+ MFENCE)>;
+def LNLPWriteResGroupX21 : SchedWriteRes<[LNLPVPort02_03]>;
+def : InstRW<[LNLPWriteResGroupX21], (instregex "^C(DQ|WD)E$",
+ "^(V?)MOVS(H|L)DUPrr$",
+ "^(V?)SHUFP(D|S)rri$",
+ "^VMOVS(H|L)DUPYrr$",
+ "^VSHUFP(D|S)Yrri$")>;
+def : InstRW<[LNLPWriteResGroupX21], (instrs CBW)>;
+
+def LNLPWriteResGroupX22 : SchedWriteRes<[LNLPPort00_02_04]>;
+def : InstRW<[LNLPWriteResGroupX22], (instregex "^C(DQ|QO)$",
+ "^(CL|ST)AC$")>;
+def LNLPWriteResGroupX23 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04]> {
+ let Latency = 3;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX23], (instrs CLD)>;
+
+def LNLPWriteResGroupX24 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 3;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX24], (instrs CLDEMOTE)>;
+
+def LNLPWriteResGroupX25 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 2;
+ let NumMicroOps = 4;
+}
+def : InstRW<[LNLPWriteResGroupX25], (instrs CLFLUSH)>;
+
+def LNLPWriteResGroupX26 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 2;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX26], (instrs CLFLUSHOPT)>;
+
+def LNLPWriteResGroupX27 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort01]> {
+ let ReleaseAtCycles = [2, 1];
+ let Latency = LunarlakePModel.MaxLatency;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX27], (instrs CLI)>;
+
+def LNLPWriteResGroupX28 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort01, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [6, 1, 3];
+ let Latency = LunarlakePModel.MaxLatency;
+ let NumMicroOps = 10;
+}
+def : InstRW<[LNLPWriteResGroupX28], (instrs CLTS)>;
+
+def LNLPWriteResGroupX29 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 5;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX29], (instregex "^MOV16o(16|32|64)a$")>;
+def : InstRW<[LNLPWriteResGroupX29], (instrs CLWB)>;
+
+def LNLPWriteResGroupX30 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [5, 2];
+ let Latency = 6;
+ let NumMicroOps = 7;
+}
+def : InstRW<[LNLPWriteResGroupX30], (instregex "^CMPS(B|L|Q|W)$")>;
+
+def LNLPWriteResGroupX31 : SchedWriteRes<[LNLPPort00, LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPVPort02_03, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [2, 7, 6, 2, 1, 1, 2, 1];
+ let Latency = 32;
+ let NumMicroOps = 22;
+}
+def : InstRW<[LNLPWriteResGroupX31], (instrs CMPXCHG16B)>;
+
+def LNLPWriteResGroupX32 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [4, 7, 2, 1, 1, 1];
+ let Latency = 25;
+ let NumMicroOps = 16;
+}
+def : InstRW<[LNLPWriteResGroupX32], (instrs CMPXCHG8B)>;
+
+def LNLPWriteResGroupX33 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [1, 2, 1, 1, 1];
+ let Latency = 13;
+ let NumMicroOps = 6;
+}
+def : InstRW<[LNLPWriteResGroupX33], (instrs CMPXCHG8rm)>;
+
+def LNLPWriteResGroupX34 : SchedWriteRes<[LNLPPort00, LNLPVPort00_01, LNLPPort00_02_04, LNLPPort01, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [2, 1, 10, 6, 1, 5, 1];
+ let Latency = 18;
+ let NumMicroOps = 26;
+}
+def : InstRW<[LNLPWriteResGroupX34], (instrs CPUID)>;
+
+def LNLPWriteResGroupX35 : SchedWriteRes<[LNLPVPort02_03, LNLPVPort00_01, LNLPPort20_21_22]> {
+ let Latency = 26;
+ let NumMicroOps = 3;
+}
+def LNLPWriteResGroupX36 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22, LNLPPort01_03_05]> {
+ let Latency = 12;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX36], (instrs CVTSI642SSrm)>;
+def : InstRW<[LNLPWriteResGroupX36, ReadAfterVecLd], (instrs VCVTSI642SSrm)>;
+def LNLPWriteResGroupX37 : SchedWriteRes<[LNLPVPort00_01, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [1, 2];
+ let Latency = 8;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX37, ReadInt2Fpu], (instrs CVTSI642SSrr)>;
+def : InstRW<[LNLPWriteResGroupX37, ReadDefault, ReadInt2Fpu], (instrs VCVTSI642SSrr)>;
+def LNLPWriteResGroupX38 : SchedWriteRes<[LNLPVPort02_03, LNLPVPort00_01, LNLPPort01_03_05]> {
+ let Latency = 8;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX38, ReadDefault], (instregex "^(V?)CVT(T?)SS2SI64rr$")>;
+def LNLPWriteResGroupX39 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX39], (instregex "^J(E|R)CXZ$")>;
+def : InstRW<[LNLPWriteResGroupX39], (instrs CWD)>;
+
+def LNLPWriteResGroupX40 : SchedWriteRes<[LNLPPort00_01_02_03_04_05]>;
+def : InstRW<[LNLPWriteResGroupX40], (instregex "^(LD|ST)_Frr$",
+ "^MOV16s(m|r)$",
+ "^MOV(32|64)sr$")>;
+def : InstRW<[LNLPWriteResGroupX40], (instrs DEC16r_alt,
+ SALC,
+ ST_FPrr,
+ SYSCALL)>;
+
+def LNLPWriteResGroupX41 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 7;
+}
+def : InstRW<[LNLPWriteResGroupX41], (instrs DEC32r_alt)>;
+def LNLPWriteResGroupX42 : SchedWriteRes<[LNLPPort00, LNLPPort20_21_22]> {
+ let Latency = 27;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX42], (instregex "^DIVR_F(32|64)m$")>;
+def LNLPWriteResGroupX43 : SchedWriteRes<[LNLPPort00, LNLPPort20_21_22, LNLPPort01_03_05]> {
+ let Latency = 30;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX43], (instregex "^DIVR_FI(16|32)m$")>;
+
+def LNLPWriteResGroupX44 : SchedWriteRes<[LNLPPort00]> {
+ let Latency = 15;
+}
+def : InstRW<[LNLPWriteResGroupX44], (instregex "^DIVR_F(P?)rST0$")>;
+def : InstRW<[LNLPWriteResGroupX44], (instrs DIVR_FST0r)>;
+def LNLPWriteResGroupX45 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {
+ let Latency = 20;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX45, ReadAfterVecLd], (instregex "^(V?)DIVSDrm_Int$")>;
+def LNLPWriteResGroupX46 : SchedWriteRes<[LNLPPort00, LNLPPort20_21_22]> {
+ let Latency = 22;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX46], (instregex "^DIV_F(32|64)m$")>;
+def LNLPWriteResGroupX47 : SchedWriteRes<[LNLPPort00, LNLPPort20_21_22, LNLPPort01_03_05]> {
+ let Latency = 25;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX47], (instregex "^DIV_FI(16|32)m$")>;
+
+def LNLPWriteResGroupX48 : SchedWriteRes<[LNLPPort00]> {
+ let Latency = 20;
+}
+def : InstRW<[LNLPWriteResGroupX48], (instregex "^DIV_F(P?)rST0$")>;
+def : InstRW<[LNLPWriteResGroupX48], (instrs DIV_FST0r)>;
+
+def LNLPWriteResGroupX49 : SchedWriteRes<[LNLPPort00, LNLPPort00_02_04, LNLPPort01, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [2, 21, 2, 14, 4, 9, 5];
+ let Latency = 126;
+ let NumMicroOps = 57;
+}
+def : InstRW<[LNLPWriteResGroupX49], (instrs ENTER)>;
+
+def LNLPWriteResGroupX50 : SchedWriteRes<[LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {
+ let Latency = 12;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX50], (instregex "^(V?)EXTRACTPSmri$")>;
+def : InstRW<[LNLPWriteResGroupX50], (instrs SMSW16m)>;
+
+def LNLPWriteResGroupX51 : SchedWriteRes<[LNLPVPort02_03, LNLPPort01_03_05]> {
+ let Latency = 4;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX51], (instregex "^(V?)EXTRACTPSrri$")>;
+def : InstRW<[LNLPWriteResGroupX51], (instrs MMX_PEXTRWrri)>;
+
+def LNLPWriteResGroupX52 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22, LNLPPort20_21_22, LNLPPort10_11, LNLPVPort02_03]> {
+ let Latency = 7;
+ let NumMicroOps = 5;
+}
+def : InstRW<[LNLPWriteResGroupX52], (instrs FARCALL64m)>;
+
+def LNLPWriteResGroupX53 : SchedWriteRes<[LNLPPort20_21_22, LNLPVPort02_03]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX53], (instrs FARJMP64m,
+ JMP64m_REX)>;
+
+def LNLPWriteResGroupX54 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort10_11]> {
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX54], (instregex "^(V?)MASKMOVDQU((64)?)$",
+ "^ST_FP(32|64|80)m$")>;
+def : InstRW<[LNLPWriteResGroupX54], (instrs FBSTPm,
+ VMPTRSTm)>;
+
+def LNLPWriteResGroupX55 : SchedWriteRes<[LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [2];
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX55], (instrs FDECSTP)>;
+
+def LNLPWriteResGroupX56 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [1, 2];
+ let Latency = 11;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX56], (instregex "^FICOM(P?)(16|32)m$")>;
+
+def LNLPWriteResGroupX57 : SchedWriteRes<[LNLPPort01_03_05]>;
+def : InstRW<[LNLPWriteResGroupX57], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rr$")>;
+def : InstRW<[LNLPWriteResGroupX57], (instrs FINCSTP,
+ FNOP)>;
+
+def LNLPWriteResGroupX58 : SchedWriteRes<[LNLPVPort02_03, LNLPPort01_03_05, LNLPPort20_21_22]> {
+ let Latency = 7;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX58], (instrs FLDCW16m)>;
+
+def LNLPWriteResGroupX59 : SchedWriteRes<[LNLPVPort02_03, LNLPVPort00_01_02_03, LNLPPort01_03_05, LNLPPort00_02_04, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [2, 39, 5, 10, 8];
+ let Latency = 62;
+ let NumMicroOps = 64;
+}
+def : InstRW<[LNLPWriteResGroupX59], (instrs FLDENVm)>;
+
+def LNLPWriteResGroupX60 : SchedWriteRes<[LNLPVPort00_01_02_03]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 4;
+ let NumMicroOps = 4;
+}
+def : InstRW<[LNLPWriteResGroupX60], (instrs FNCLEX)>;
+
+def LNLPWriteResGroupX61 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPPort01_03_05, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [6, 3, 6];
+ let Latency = 75;
+ let NumMicroOps = 15;
+}
+def : InstRW<[LNLPWriteResGroupX61], (instrs FNINIT)>;
+
+def LNLPWriteResGroupX62 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort10_11, LNLPVPort02_03]> {
+ let Latency = 2;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX62], (instrs FNSTCW16m)>;
+
+def LNLPWriteResGroupX63 : SchedWriteRes<[LNLPVPort02_03, LNLPVPort00_01_02_03]> {
+ let Latency = 3;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX63], (instrs FNSTSW16r)>;
+
+def LNLPWriteResGroupX64 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22, LNLPPort10_11]> {
+ let Latency = 3;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX64], (instrs FNSTSWm)>;
+
+def LNLPWriteResGroupX65 : SchedWriteRes<[LNLPVPort02_03, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPVPort02_03]> {
+ let ReleaseAtCycles = [9, 30, 21, 1, 11, 11, 16, 1];
+ let Latency = 106;
+ let NumMicroOps = 100;
+}
+def : InstRW<[LNLPWriteResGroupX65], (instrs FSTENVm)>;
+
+def LNLPWriteResGroupX66 : SchedWriteRes<[LNLPVPort02_03, LNLPVPort00_01_02_03, LNLPPort01_03_05, LNLPPort00_02_04, LNLPVPort02_03, LNLPPort20_21_22, LNLPVPort02_03]> {
+ let ReleaseAtCycles = [4, 47, 1, 2, 1, 33, 2];
+ let Latency = 63;
+ let NumMicroOps = 90;
+}
+def : InstRW<[LNLPWriteResGroupX66], (instrs FXRSTOR)>;
+
+def LNLPWriteResGroupX67 : SchedWriteRes<[LNLPVPort02_03, LNLPVPort00_01_02_03, LNLPPort01_03_05, LNLPPort00_02_04, LNLPVPort02_03, LNLPPort20_21_22, LNLPVPort02_03]> {
+ let ReleaseAtCycles = [4, 45, 1, 2, 1, 31, 4];
+ let Latency = 63;
+ let NumMicroOps = 88;
+}
+def : InstRW<[LNLPWriteResGroupX67], (instrs FXRSTOR64)>;
+
+def LNLPWriteResGroupX68 : SchedWriteRes<[LNLPVPort02_03, LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [2, 5, 10, 10, 2, 38, 5, 38];
+ let Latency = LunarlakePModel.MaxLatency;
+ let NumMicroOps = 110;
+}
+def : InstRW<[LNLPWriteResGroupX68], (instregex "^FXSAVE((64)?)$")>;
+
+def LNLPWriteResGroupX69 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {
+ let Latency = 12;
+ let NumMicroOps = 2;
+}
+
+def LNLPWriteResGroupX77 : SchedWriteRes<[LNLPPort00_02_04]> {
+ let NumMicroOps = 4;
+}
+def : InstRW<[LNLPWriteResGroupX77], (instrs INC16r_alt)>;
+
+def LNLPWriteResGroupX78 : SchedWriteRes<[LNLPPort20_21_22]> {
+ let Latency = 7;
+}
+def : InstRW<[LNLPWriteResGroupX78], (instrs INC32r_alt)>;
+
+def LNLPWriteResGroupX85 : SchedWriteRes<[LNLPPort00_02_04]>;
+def : InstRW<[LNLPWriteResGroupX85], (instrs JMP64r_REX)>;
+def LNLPWriteResGroupX86 : SchedWriteRes<[]> {
+ let Latency = 0;
+ let NumMicroOps = 0;
+}
+def : InstRW<[LNLPWriteResGroupX86], (instregex "^JMP_(1|4)$")>;
+def : InstRW<[LNLPWriteResGroupX86], (instrs VZEROUPPER)>;
+
+def LNLPWriteResGroupX93 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort01_03_05]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX93], (instrs LEA16r)>;
+
+def LNLPWriteResGroupX104 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [4, 6, 1];
+ let Latency = 3;
+ let NumMicroOps = 11;
+}
+def : InstRW<[LNLPWriteResGroupX104], (instrs LOOPE)>;
+
+def LNLPWriteResGroupX105 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [4, 6, 1];
+ let Latency = 2;
+ let NumMicroOps = 11;
+}
+def : InstRW<[LNLPWriteResGroupX105], (instrs LOOPNE)>;
+
+def LNLPWriteResGroupX115 : SchedWriteRes<[LNLPVPort00_01, LNLPPort10_11, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [2, 1, 1];
+ let Latency = 12;
+ let NumMicroOps = 4;
+}
+def : InstRW<[LNLPWriteResGroupX115], (instregex "^MMX_MASKMOVQ((64)?)$")>;
+def LNLPWriteResGroupX118 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPVPort00_01]> {
+ let Latency = 3;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX118], (instregex "^MMX_MOV(DQ|FR64)2Qrr$")>;
+def LNLPWriteResGroupX122 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {
+ let Latency = 9;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX122, ReadAfterVecLd], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rm$")>;
+def LNLPWriteResGroupX123 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [1, 1, 2];
+ let Latency = 11;
+ let NumMicroOps = 4;
+}
+def : InstRW<[LNLPWriteResGroupX123, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)SWrm$")>;
+def LNLPWriteResGroupX124 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [1, 2];
+ let Latency = 3;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX124], (instregex "^MMX_PH(ADD|SUB)SWrr$")>;
+def LNLPWriteResGroupX116 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 18;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX116], (instrs MMX_MOVD64mr)>;
+def LNLPWriteResGroupX117 : SchedWriteRes<[LNLPPort20_21_22]> {
+ let Latency = 8;
+}
+def : InstRW<[LNLPWriteResGroupX117], (instregex "^MMX_MOV(D|Q)64rm$",
+ "^VBROADCASTI128rm$")>;
+def : InstRW<[LNLPWriteResGroupX117], (instrs MMX_MOVD64to64rm)>;
+def LNLPWriteResGroupX120 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [1, 2];
+ let Latency = 12;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX120, ReadAfterVecLd], (instregex "^MMX_PACKSS(DW|WB)rm$")>;
+def : InstRW<[LNLPWriteResGroupX120, ReadAfterVecLd], (instrs MMX_PACKUSWBrm)>;
+def LNLPWriteResGroupX121 : SchedWriteRes<[LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [2];
+ let Latency = 4;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX121], (instregex "^MMX_PACKSS(DW|WB)rr$")>;
+def : InstRW<[LNLPWriteResGroupX121], (instrs MMX_PACKUSWBrr)>;
+def : InstRW<[LNLPWriteResGroupX121, ReadDefault, ReadInt2Fpu], (instrs MMX_PINSRWrri)>;
+def LNLPWriteResGroupX125 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort01_03_05]> {
+ let Latency = 9;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX125, ReadAfterLd], (instrs MMX_PINSRWrmi)>;
+def LNLPWriteResGroupX126 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22]> {
+ let Latency = 5;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX126], (instregex "^MOV16ao(16|32|64)$")>;
+def LNLPWriteResGroupX127 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 12;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX127], (instregex "^PUSH(F|G)S(16|32)$")>;
+def : InstRW<[LNLPWriteResGroupX127], (instrs MOV16ms,
+ MOVBE32mr)>;
+def LNLPWriteResGroupX128 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort01_03_05]> {
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX128], (instregex "^MOV(16|32|64)rs$",
+ "^S(TR|LDT)16r$")>;
+def LNLPWriteResGroupX129 : SchedWriteRes<[LNLPPort20_21_22]>;
+def : InstRW<[LNLPWriteResGroupX129], (instregex "^MOV32ao(16|32|64)$")>;
+def : InstRW<[LNLPWriteResGroupX129], (instrs MOV64ao64)>;
+def LNLPWriteResGroupX130 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort10_11, LNLPPort25_26_27]> {
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX130], (instregex "^MOV(8|32)o(16|32)a$",
+ "^MOV(8|32|64)o64a$")>;
+def LNLPWriteResGroupX131 : SchedWriteRes<[LNLPPort00_01_02_03_04_05]> {
+ let Latency = 0;
+}
+def : InstRW<[LNLPWriteResGroupX131], (instregex "^MOV32rr((_REV)?)$",
+ "^MOVZX(32|64)rr8$")>;
+def : InstRW<[LNLPWriteResGroupX131], (instrs MOVZX32rr8_NOREX)>;
+
+def LNLPWriteResGroupX132 : SchedWriteRes<[LNLPPort20_21_22]> {
+ let Latency = 5;
+}
+def : InstRW<[LNLPWriteResGroupX132], (instrs MOV64ao32)>;
+def LNLPWriteResGroupX134 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 12;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX134], (instrs MOV64o32a)>;
+def LNLPWriteResGroupX135 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {
+ let Latency = LunarlakePModel.MaxLatency;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX135], (instrs MOV64rc)>;
+def LNLPWriteResGroupX137 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22]> {
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX137], (instregex "^MOV8ao(16|32|64)$")>;
+def LNLPWriteResGroupX138 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 13;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX138], (instregex "^MOV8m(i|r)$")>;
+def : InstRW<[LNLPWriteResGroupX138], (instrs MOV8mr_NOREX)>;
+def LNLPWriteResGroupX139 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 12;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX139], (instrs MOVBE16mr)>;
+def LNLPWriteResGroupX142 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 12;
+ let NumMicroOps = 4;
+}
+def : InstRW<[LNLPWriteResGroupX142], (instrs MOVBE64mr,
+ PUSHF16,
+ SLDT16m,
+ STRm)>;
+
+def LNLPWriteResGroupX144 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {
+ let NumMicroOps = 4;
+}
+def : InstRW<[LNLPWriteResGroupX144], (instregex "^MOVDIR64B(16|32|64)$")>;
+def LNLPWriteResGroupX147 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPPort20_21_22]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX147, ReadAfterVecXLd], (instregex "^(V?)MOVLP(D|S)rm$")>;
+def LNLPWriteResGroupX148 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 512;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX148], (instrs MOVNTDQmr)>;
+def LNLPWriteResGroupX149 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 518;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX149], (instrs MOVNTImr)>;
+def LNLPWriteResGroupX150 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [4, 1, 1, 1];
+ let Latency = 8;
+ let NumMicroOps = 7;
+}
+def : InstRW<[LNLPWriteResGroupX150], (instrs MOVSB)>;
+def LNLPWriteResGroupX151 : SchedWriteRes<[LNLPVPort00_01_02_03]>;
+def : InstRW<[LNLPWriteResGroupX151], (instrs VPBLENDDrri)>;
+def LNLPWriteResGroupX152 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [4, 1, 1, 1];
+ let Latency = 7;
+ let NumMicroOps = 7;
+}
+def : InstRW<[LNLPWriteResGroupX152], (instregex "^MOVS(L|Q|W)$")>;
+def LNLPWriteResGroupX153 : SchedWriteRes<[LNLPPort20_21_22]> {
+ let Latency = 6;
+}
+def : InstRW<[LNLPWriteResGroupX153], (instregex "^MOVSX(16|32|64)rm(16|32)$",
+ "^MOVSX(32|64)rm8$")>;
+def : InstRW<[LNLPWriteResGroupX153], (instrs MOVSX32rm8_NOREX)>;
+def LNLPWriteResGroupX154 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort20_21_22]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX154], (instrs MOVSX16rm8)>;
+def LNLPWriteResGroupX156 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPVPort02_03]> {
+ let Latency = 11;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX156], (instregex "^MUL_F(32|64)m$")>;
+def LNLPWriteResGroupX157 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPVPort02_03, LNLPPort01_03_05]> {
+ let Latency = 14;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX157], (instregex "^MUL_FI(16|32)m$")>;
+def LNLPWriteResGroupX158 : SchedWriteRes<[LNLPVPort00_01_02_03]> {
+ let Latency = 4;
+}
+def : InstRW<[LNLPWriteResGroupX158], (instregex "^MUL_F(P?)rST0$")>;
+def : InstRW<[LNLPWriteResGroupX158], (instrs MUL_FST0r)>;
+def LNLPWriteResGroupX155 : SchedWriteRes<[LNLPPort01_03_05]>;
+def : InstRW<[LNLPWriteResGroupX155], (instregex "^MOVSX(16|32|64)rr(8|16|32)$")>;
+def : InstRW<[LNLPWriteResGroupX155], (instrs MOVSX32rr8_NOREX)>;
+def LNLPWriteResGroupX173 : SchedWriteRes<[LNLPPort01_03_05]>;
+def : InstRW<[LNLPWriteResGroupX173], (instregex "^(V?)PALIGNRrri$",
+ "^VPBROADCAST(B|D|Q|W)rr$")>;
+def : InstRW<[LNLPWriteResGroupX173], (instrs VPALIGNRYrri)>;
+def LNLPWriteResGroupX176 : SchedWriteRes<[LNLPVPort02_03, LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 12;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX176], (instregex "^(V?)PEXTR(D|Q)mri$")>;
+def LNLPWriteResGroupX179 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 12;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX179], (instregex "^POP(16|32|64)rmm$",
+ "^PUSH(16|32)rmm$")>;
+def LNLPWriteResGroupX180 : SchedWriteRes<[LNLPPort20_21_22]> {
+ let Latency = 5;
+}
+def : InstRW<[LNLPWriteResGroupX180], (instregex "^POPA(16|32)$",
+ "^PREFETCHIT(0|1)$")>;
+def : InstRW<[LNLPWriteResGroupX180], (instrs POPF32)>;
+def LNLPWriteResGroupX181 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [6, 2, 1, 1];
+ let Latency = 5;
+ let NumMicroOps = 10;
+}
+def : InstRW<[LNLPWriteResGroupX181], (instrs POPF16)>;
+def LNLPWriteResGroupX182 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [2, 1, 1];
+ let Latency = 5;
+ let NumMicroOps = 7;
+}
+def : InstRW<[LNLPWriteResGroupX182], (instrs POPF64)>;
+def LNLPWriteResGroupX183 : SchedWriteRes<[LNLPPort20_21_22]> {
+ let Latency = 0;
+}
+def : InstRW<[LNLPWriteResGroupX183], (instregex "^PREFETCHT(0|1|2)$")>;
+def : InstRW<[LNLPWriteResGroupX183], (instrs PREFETCHNTA)>;
+def LNLPWriteResGroupX187 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX187], (instregex "^PUSH64r((mr)?)$")>;
+def LNLPWriteResGroupX188 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX188], (instrs PUSH64rmm)>;
+def LNLPWriteResGroupX189 : SchedWriteRes<[LNLPPort20_21_22, LNLPPort10_11]>;
+def : InstRW<[LNLPWriteResGroupX189], (instregex "^PUSHA(16|32)$",
+ "^ST_F(32|64)m$")>;
+def : InstRW<[LNLPWriteResGroupX189], (instrs PUSHF32)>;
+def LNLPWriteResGroupX190 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 4;
+ let NumMicroOps = 4;
+}
+def : InstRW<[LNLPWriteResGroupX190], (instrs PUSHF64)>;
+def LNLPWriteResGroupX191 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort10_11, LNLPPort25_26_27]> {
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX191], (instregex "^PUSH(F|G)S64$")>;
+def LNLPWriteResGroupX192 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [2, 3, 2];
+ let Latency = 8;
+ let NumMicroOps = 7;
+}
+def : InstRW<[LNLPWriteResGroupX192], (instregex "^RC(L|R)(16|32|64)rCL$")>;
+def LNLPWriteResGroupX193 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04]> {
+ let ReleaseAtCycles = [1, 2];
+ let Latency = 13;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX193, WriteRMW], (instregex "^RC(L|R)8m(1|i)$")>;
+def LNLPWriteResGroupX194 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [1, 5, 2];
+ let Latency = 20;
+ let NumMicroOps = 8;
+}
+def : InstRW<[LNLPWriteResGroupX194, WriteRMW], (instrs RCL8mCL)>;
+def LNLPWriteResGroupX195 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [2, 5, 2];
+ let Latency = 7;
+ let NumMicroOps = 9;
+}
+def : InstRW<[LNLPWriteResGroupX195], (instrs RCL8rCL)>;
+def LNLPWriteResGroupX196 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [2, 4, 3];
+ let Latency = 20;
+ let NumMicroOps = 9;
+}
+def : InstRW<[LNLPWriteResGroupX196, WriteRMW], (instrs RCR8mCL)>;
+def LNLPWriteResGroupX197 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [3, 4, 3];
+ let Latency = 9;
+ let NumMicroOps = 10;
+}
+def : InstRW<[LNLPWriteResGroupX197], (instrs RCR8rCL)>;
+def LNLPWriteResGroupX206 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [5, 6, 3, 1];
+ let Latency = 18;
+ let NumMicroOps = 15;
+}
+def : InstRW<[LNLPWriteResGroupX206], (instrs RDTSC)>;
+def LNLPWriteResGroupX208 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort20_21_22]> {
+ let Latency = 7;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX208], (instrs RET64)>;
+def LNLPWriteResGroupX209 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [2, 1];
+ let Latency = 6;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX209], (instregex "^RETI(16|32|64)$")>;
+def LNLPWriteResGroupX210 : SchedWriteRes<[]>;
+def : InstRW<[LNLPWriteResGroupX210], (instrs REX64_PREFIX)>;
+def LNLPWriteResGroupX211 : SchedWriteRes<[LNLPPort00_02_04]> {
+ let ReleaseAtCycles = [2];
+ let Latency = 12;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX211, WriteRMW], (instregex "^RO(L|R)(16|32|64)m(1|i|CL)$")>;
+def LNLPWriteResGroupX212 : SchedWriteRes<[LNLPPort00_02_04]> {
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX212], (instregex "^RO(L|R)(8|16|32|64)r(1|i)$")>;
+def LNLPWriteResGroupX213 : SchedWriteRes<[LNLPPort00_02_04]> {
+ let ReleaseAtCycles = [2];
+ let Latency = 13;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX213, WriteRMW], (instregex "^RO(L|R)8m(1|i)$",
+ "^(RO|SH)L8mCL$",
+ "^(RO|SA|SH)R8mCL$")>;
+def LNLPWriteResGroupX214 : SchedWriteRes<[LNLPPort00_02_04]> {
+ let ReleaseAtCycles = [2];
+ let Latency = 4;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX214], (instrs SAHF)>;
+def LNLPWriteResGroupX215 : SchedWriteRes<[LNLPPort00_02_04]> {
+ let Latency = 13;
+}
+def : InstRW<[LNLPWriteResGroupX215, WriteRMW], (instregex "^S(A|H)R8m(1|i)$",
+ "^SHL8m(1|i)$")>;
+def LNLPWriteResGroupX216 : SchedWriteRes<[LNLPPort00_02_04, LNLPPort20_21_22]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX216, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^S(A|H)RX(32|64)rm$",
+ "^SHLX(32|64)rm$")>;
+def LNLPWriteResGroupX217 : SchedWriteRes<[LNLPPort00_02_04]> {
+ let Latency = 3;
+}
+def : InstRW<[LNLPWriteResGroupX217], (instregex "^S(A|H)RX(32|64)rr$",
+ "^SHLX(32|64)rr$")>;
+def LNLPWriteResGroupX218 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort10_11, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [2, 2, 1, 1, 1];
+ let Latency = LunarlakePModel.MaxLatency;
+ let NumMicroOps = 7;
+}
+def : InstRW<[LNLPWriteResGroupX218], (instrs SERIALIZE)>;
+def LNLPWriteResGroupX219 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX219], (instrs SFENCE)>;
+def LNLPWriteResGroupX220 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort10_11, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [1, 2, 2, 2];
+ let Latency = 21;
+ let NumMicroOps = 7;
+}
+def : InstRW<[LNLPWriteResGroupX220], (instregex "^S(G|I)DT64m$")>;
+def LNLPWriteResGroupX223 : SchedWriteRes<[LNLPVPort00_01, LNLPPort01_03_05, LNLPPort00_02_04, LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [2, 2, 1, 2, 1];
+ let Latency = 13;
+ let NumMicroOps = 8;
+}
+def : InstRW<[LNLPWriteResGroupX223, ReadAfterVecXLd], (instrs SHA1MSG2rm)>;
+def LNLPWriteResGroupX224 : SchedWriteRes<[LNLPVPort00_01, LNLPPort01_03_05, LNLPPort00_02_04, LNLPVPort02_03]> {
+ let ReleaseAtCycles = [2, 2, 1, 2];
+ let Latency = 6;
+ let NumMicroOps = 7;
+}
+def : InstRW<[LNLPWriteResGroupX224], (instrs SHA1MSG2rr)>;
+def LNLPWriteResGroupX233 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 13;
+ let NumMicroOps = 5;
+}
+def : InstRW<[LNLPWriteResGroupX233], (instrs SHRD16mri8)>;
+def LNLPWriteResGroupX234 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort01_03_05]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX234], (instregex "^SLDT(32|64)r$")>;
+def LNLPWriteResGroupX235 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort01_03_05]> {
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX235], (instrs SMSW16r)>;
+def LNLPWriteResGroupX236 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort01_03_05]> {
+ let Latency = LunarlakePModel.MaxLatency;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX236], (instregex "^SMSW(32|64)r$")>;
+def LNLPWriteResGroupX237 : SchedWriteRes<[ADLPPort00, LNLPPort20_21_22]> {
+ let Latency = 24;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX237, ReadAfterVecLd], (instregex "^(V?)SQRTSDm_Int$")>;
+def LNLPWriteResGroupX238 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX238], (instrs STD)>;
+def LNLPWriteResGroupX239 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [1, 4, 1];
+ let Latency = LunarlakePModel.MaxLatency;
+ let NumMicroOps = 6;
+}
+def : InstRW<[LNLPWriteResGroupX239], (instrs STI)>;
+def LNLPWriteResGroupX240 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort10_11, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [2, 1, 1];
+ let Latency = 8;
+ let NumMicroOps = 4;
+}
+def : InstRW<[LNLPWriteResGroupX240], (instrs STOSB)>;
+def LNLPWriteResGroupX241 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort10_11, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [2, 1, 1];
+ let Latency = 7;
+ let NumMicroOps = 4;
+}
+def : InstRW<[LNLPWriteResGroupX241], (instregex "^STOS(L|Q|W)$")>;
+def LNLPWriteResGroupX242 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort01_03_05]> {
+ let Latency = 5;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX242], (instregex "^STR(32|64)r$")>;
+def LNLPWriteResGroupX243 : SchedWriteRes<[LNLPPort01_03_05]> {
+ let Latency = 2;
+}
+def : InstRW<[LNLPWriteResGroupX243], (instregex "^(TST|XAM)_F$")>;
+def : InstRW<[LNLPWriteResGroupX243], (instrs UCOM_FPPr)>;
+def LNLPWriteResGroupX244 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 1];
+ let Latency = 9;
+ let NumMicroOps = 4;
+}
+def : InstRW<[LNLPWriteResGroupX244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rmr$")>;
+def : InstRW<[LNLPWriteResGroupX244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrmr)>;
+def LNLPWriteResGroupX245 : SchedWriteRes<[LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX245], (instregex "^VBLENDVP(D|S)rrr$")>;
+def : InstRW<[LNLPWriteResGroupX245], (instrs VPBLENDVBrrr)>;
+def LNLPWriteResGroupX250 : SchedWriteRes<[LNLPVPort00_01, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 1, 2, 4];
+ let Latency = 29;
+ let NumMicroOps = 8;
+}
+def : InstRW<[LNLPWriteResGroupX250, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDYrm$",
+ "^VPGATHER(D|Q)QYrm$")>;
+def : InstRW<[LNLPWriteResGroupX250, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSYrm,
+ VPGATHERQDYrm)>;
+def LNLPWriteResGroupX251 : SchedWriteRes<[LNLPVPort00_01, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 1, 1, 2];
+ let Latency = 20;
+ let NumMicroOps = 5;
+}
+def : InstRW<[LNLPWriteResGroupX251, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDrm$",
+ "^VPGATHER(D|Q)Qrm$")>;
+def : InstRW<[LNLPWriteResGroupX251, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSrm,
+ VPGATHERQDrm)>;
+def LNLPWriteResGroupX252 : SchedWriteRes<[LNLPVPort00_01, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 1, 2, 8];
+ let Latency = 30;
+ let NumMicroOps = 12;
+}
+def : InstRW<[LNLPWriteResGroupX252, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSYrm,
+ VPGATHERDDYrm)>;
+def LNLPWriteResGroupX253 : SchedWriteRes<[LNLPVPort00_01, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 1, 2, 4];
+ let Latency = 28;
+ let NumMicroOps = 8;
+}
+def : InstRW<[LNLPWriteResGroupX253, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSrm,
+ VPGATHERDDrm)>;
+def LNLPWriteResGroupX254 : SchedWriteRes<[LNLPVPort02_03, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [1, 2];
+ let Latency = 5;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX254], (instregex "^VH(ADD|SUB)P(D|S)rr$")>;
+def LNLPWriteResGroupX256 : SchedWriteRes<[LNLPVPort00_01, LNLPPort00_02_04, LNLPPort20_21_22]> {
+ let Latency = 7;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX256], (instrs VLDMXCSR)>;
+def LNLPWriteResGroupX257 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort00_02_04]> {
+ let ReleaseAtCycles = [8, 1, 1, 1, 1, 1, 2, 3];
+ let Latency = 40;
+ let NumMicroOps = 18;
+}
+def : InstRW<[LNLPWriteResGroupX257], (instrs VMCLEARm)>;
+def LNLPWriteResGroupX259 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 521;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX259], (instrs VMOVNTDQmr)>;
+def LNLPWriteResGroupX260 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 473;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX260], (instrs VMOVNTPDmr)>;
+def LNLPWriteResGroupX261 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 494;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX261], (instrs VMOVNTPSYmr)>;
+def LNLPWriteResGroupX262 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = 470;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX262], (instrs VMOVNTPSmr)>;
+def LNLPWriteResGroupX264 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {
+ let Latency = 9;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX264, ReadAfterVecYLd], (instregex "^VSHUFP(D|S)Yrmi$")>;
+def LNLPWriteResGroupX267 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [1, 2, 3, 3, 1];
+ let Latency = 16;
+ let NumMicroOps = 10;
+}
+def : InstRW<[LNLPWriteResGroupX267], (instrs VZEROALL)>;
+def LNLPWriteResGroupX268 : SchedWriteRes<[LNLPVPort00_01_02_03]> {
+ let ReleaseAtCycles = [2];
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX268], (instrs WAIT)>;
+def LNLPWriteResGroupX269 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1];
+ let Latency = LunarlakePModel.MaxLatency;
+ let NumMicroOps = 144;
+}
+def : InstRW<[LNLPWriteResGroupX269], (instrs WRMSR)>;
+def LNLPWriteResGroupX270 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [2, 1, 4, 1];
+ let Latency = LunarlakePModel.MaxLatency;
+ let NumMicroOps = 8;
+}
+def : InstRW<[LNLPWriteResGroupX270], (instrs WRPKRUr)>;
+def LNLPWriteResGroupX271 : SchedWriteRes<[LNLPPort00_01_02_03_04_05]> {
+ let ReleaseAtCycles = [2];
+ let Latency = 12;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX271, WriteRMW], (instregex "^XADD(16|32|64)rm$")>;
+def LNLPWriteResGroupX272 : SchedWriteRes<[LNLPPort00_01_02_03_04_05]> {
+ let ReleaseAtCycles = [2];
+ let Latency = 13;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroupX272, WriteRMW], (instrs XADD8rm)>;
+def LNLPWriteResGroupX273 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04]> {
+ let ReleaseAtCycles = [4, 1];
+ let Latency = 39;
+ let NumMicroOps = 5;
+}
+def : InstRW<[LNLPWriteResGroupX273, WriteRMW], (instregex "^XCHG(16|32)rm$")>;
+def LNLPWriteResGroupX274 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04]> {
+ let ReleaseAtCycles = [5, 1];
+ let Latency = 39;
+ let NumMicroOps = 6;
+}
+def : InstRW<[LNLPWriteResGroupX274, WriteRMW], (instrs XCHG64rm)>;
+def LNLPWriteResGroupX275 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort00_02_04]> {
+ let ReleaseAtCycles = [4, 1];
+ let Latency = 40;
+ let NumMicroOps = 5;
+}
+def : InstRW<[LNLPWriteResGroupX275, WriteRMW], (instrs XCHG8rm)>;
+def LNLPWriteResGroupX276 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPVPort00_01_02_03, LNLPPort01_03_05, LNLPPort01_03_05, LNLPPort00_02_04]> {
+ let ReleaseAtCycles = [2, 4, 2, 1, 2, 4];
+ let Latency = 17;
+ let NumMicroOps = 15;
+}
+def : InstRW<[LNLPWriteResGroupX276], (instrs XCH_F)>;
+def LNLPWriteResGroupX277 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [7, 3, 8, 5];
+ let Latency = 4;
+ let NumMicroOps = 23;
+}
+def : InstRW<[LNLPWriteResGroupX277], (instrs XGETBV)>;
+def LNLPWriteResGroupX278 : SchedWriteRes<[LNLPPort00_01_02_03_04_05, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [2, 1];
+ let Latency = 7;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroupX278], (instrs XLAT)>;
+def LNLPWriteResGroupX279 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort00_02_04]> {
+ let ReleaseAtCycles = [21, 1, 1, 8];
+ let Latency = 37;
+ let NumMicroOps = 31;
+}
+def : InstRW<[LNLPWriteResGroupX279], (instregex "^XRSTOR((S|64)?)$")>;
+def : InstRW<[LNLPWriteResGroupX279], (instrs XRSTORS64)>;
+def LNLPWriteResGroupX280 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
+ let Latency = 42;
+ let NumMicroOps = 140;
+}
+def : InstRW<[LNLPWriteResGroupX280], (instrs XSAVE)>;
+def LNLPWriteResGroupX281 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
+ let Latency = 41;
+ let NumMicroOps = 140;
+}
+def : InstRW<[LNLPWriteResGroupX281], (instrs XSAVE64)>;
+def LNLPWriteResGroupX282 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2];
+ let Latency = 42;
+ let NumMicroOps = 151;
+}
+def : InstRW<[LNLPWriteResGroupX282], (instrs XSAVEC)>;
+def LNLPWriteResGroupX283 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2];
+ let Latency = 42;
+ let NumMicroOps = 152;
+}
+def : InstRW<[LNLPWriteResGroupX283], (instrs XSAVEC64)>;
+def LNLPWriteResGroupX284 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [25, 35, 52, 27, 4, 1, 10, 1];
+ let Latency = 46;
+ let NumMicroOps = 155;
+}
+def : InstRW<[LNLPWriteResGroupX284], (instrs XSAVEOPT)>;
+def LNLPWriteResGroupX285 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [25, 35, 53, 27, 4, 1, 10, 1];
+ let Latency = 46;
+ let NumMicroOps = 156;
+}
+def : InstRW<[LNLPWriteResGroupX285], (instrs XSAVEOPT64)>;
+def LNLPWriteResGroupX286 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2];
+ let Latency = 42;
+ let NumMicroOps = 184;
+}
+def : InstRW<[LNLPWriteResGroupX286], (instrs XSAVES)>;
+def LNLPWriteResGroupX287 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPVPort02_03, LNLPPort20_21_22, LNLPPort10_11, LNLPPort01_03_05, LNLPPort25_26_27]> {
+ let ReleaseAtCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2];
+ let Latency = 42;
+ let NumMicroOps = 186;
+}
+def : InstRW<[LNLPWriteResGroupX287], (instrs XSAVES64)>;
+def LNLPWriteResGroupX288 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort00_01_02_03_04_05, LNLPVPort00_01_02_03, LNLPPort00_02_04, LNLPPort01_03_05, LNLPPort01_03_05, LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [4, 23, 2, 14, 8, 1, 2];
+ let Latency = 5;
+ let NumMicroOps = 54;
+}
+def : InstRW<[LNLPWriteResGroupX288], (instrs XSETBV)>;
+
+// SchedWriteRes and InstRW definition
+// Following defs are based on data shared by arch team
+def LNLPWriteResGroup0 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup0, ReadAfterVecXLd], (instregex "^(V?)CMPP(D|S)rmi$",
+ "^GF2P8AFFINE((INV)?)QBrmi$")>;
+def : InstRW<[LNLPWriteResGroup0, ReadAfterVecXLd], (instrs GF2P8MULBrm)>;
+def : InstRW<[LNLPWriteResGroup0, ReadAfterVecLd], (instregex "^(V?)CMPS(D|S)rmi((_Int)?)$")>;
+def LNLPWriteResGroup1 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 1, 6];
+ let Latency = 11;
+ let NumMicroOps = 2;
+}
+def LNLPWriteResGroup2 : SchedWriteRes<[LNLPPort01_03_05, LNLPVPort00_01, LNLPVPort02_03]> {
+ let ReleaseAtCycles = [4, 4, 1];
+ let Latency = 9;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroup2, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CVTSI642SSrr_Int$")>;
+def LNLPWriteResGroup3 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [7, 4];
+ let Latency = 11;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroup3], (instregex "^CVT(T?)SS2SI((64)?)rm_Int$",
+ "^CVT(T?)SS2SIrm$",
+ "^VCVTTSD2SI((64)?)rm_Int$")>;
+def LNLPWriteResGroup4 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort02_03]> {
+ let ReleaseAtCycles = [7, 1];
+ let Latency = 8;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroup4], (instregex "^(V?)CVT(T?)SS2SI64rr_Int$")>;
+def LNLPWriteResGroup5 : SchedWriteRes<[LNLPVPort00_01]> {
+ let ReleaseAtCycles = [4];
+ let Latency = 3;
+}
+def : InstRW<[LNLPWriteResGroup5], (instregex "^GF2P8AFFINE((INV)?)QBrri$")>;
+def : InstRW<[LNLPWriteResGroup5], (instrs GF2P8MULBrr)>;
+def LNLPWriteResGroup6 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 1, 8];
+ let Latency = 13;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroup6], (instregex "^MMX_CVT(T?)PD2PIrm$")>;
+def LNLPWriteResGroup7 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort02_03]> {
+ let ReleaseAtCycles = [4, 1];
+ let Latency = LunarlakePModel.MaxLatency;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup7], (instregex "^MMX_CVT(T?)PD2PIrr$")>;
+def : InstRW<[LNLPWriteResGroup7], (instrs MMX_CVTPI2PDrr)>;
+def LNLPWriteResGroup8 : SchedWriteRes<[LNLPVPort00_01]> {
+ let ReleaseAtCycles = [5];
+ let Latency = LunarlakePModel.MaxLatency;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup8], (instrs MMX_CVTPI2PSrr)>;
+def LNLPWriteResGroup9 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 8];
+ let Latency = 13;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup9], (instregex "^MMX_CVT(T?)PS2PIrm$")>;
+def LNLPWriteResGroup10 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03]> {
+ let ReleaseAtCycles = [4, 1];
+ let Latency = LunarlakePModel.MaxLatency;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup10], (instrs MMX_CVTPS2PIrr)>;
+def LNLPWriteResGroup11 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03]> {
+ let ReleaseAtCycles = [4, 1];
+ let Latency = 5;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup11], (instrs MMX_CVTTPS2PIrr)>;
+def LNLPWriteResGroup12 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03]> {
+ let Latency = 3;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup12], (instregex "^MMX_MOVQ2(DQ|FR64)rr$")>;
+def LNLPWriteResGroup13 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [2, 4];
+ let Latency = LunarlakePModel.MaxLatency;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroup13], (instregex "^MOVBE(16|32|64)rm$")>;
+def LNLPWriteResGroup14 : SchedWriteRes<[LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [6];
+ let Latency = 6;
+}
+def : InstRW<[LNLPWriteResGroup14], (instregex "^(V?)MOV(D|SH|SL)DUPrm$",
+ "^VPBROADCAST(D|Q|W)rm$")>;
+def : InstRW<[LNLPWriteResGroup14], (instrs VBROADCASTSSrm)>;
+def LNLPWriteResGroup15 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {
+ let Latency = LunarlakePModel.MaxLatency;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup15], (instregex "^MOVDIRI(32|64)$")>;
+def LNLPWriteResGroup16 : SchedWriteRes<[LNLPVPort00_01_02_03]>;
+def : InstRW<[LNLPWriteResGroup16], (instregex "^(V?)MOVS(D|S)rr((_REV)?)$",
+ "^(V?)P(ADD|SUB)(B|D|Q|W)rr$",
+ "^VP(ADD|SUB)(B|D|Q|W)Yrr$")>;
+def LNLPWriteResGroup17 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 6];
+ let Latency = 9; // originally 10
+}
+def : InstRW<[LNLPWriteResGroup17, ReadAfterVecXLd], (instregex "^(V?)PACK(S|U)S(DW|WB)rm$",
+ "^(V?)PCMPGTQrm$")>;
+def LNLPWriteResGroup18 : SchedWriteRes<[LNLPVPort02_03]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : InstRW<[LNLPWriteResGroup18], (instregex "^(V?)PACK(S|U)S(DW|WB)rr$",
+ "^(V?)PACKUSWBrr$",
+ "^(V?)PCMPGTQrr$",
+ "^VPACK(S|U)S(DW|WB)Yrr$",
+ "^VSHA512MSG(1|2)rr$")>;
+def : InstRW<[LNLPWriteResGroup18], (instrs VPCMPGTQYrr)>;
+def LNLPWriteResGroup19 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 6];
+ let Latency = 7;
+}
+def : InstRW<[LNLPWriteResGroup19, ReadAfterVecXLd], (instregex "^(V?)P(ADD|SUB)(B|D|Q|W)rm$")>;
+def : InstRW<[LNLPWriteResGroup19, ReadAfterVecXLd], (instrs VPBLENDDrmi)>;
+def LNLPWriteResGroup20 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 6];
+ let Latency = 7;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup20], (instregex "^(V?)PSHUF(D|HW|LW)mi$",
+ "^VPERMILP(D|S)mi$")>;
+def : InstRW<[LNLPWriteResGroup20, ReadAfterVecXLd], (instregex "^(V?)PALIGNRrmi$",
+ "^(V?)SHUFP(D|S)rmi$")>;
+def : InstRW<[LNLPWriteResGroup20, ReadAfterVecXLd], (instrs VINSERTPSrmi,
+ VPBLENDWrmi)>;
+def LNLPWriteResGroup21 : SchedWriteRes<[LNLPPort01_03_05, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 4];
+ let Latency = 7;
+}
+def : InstRW<[LNLPWriteResGroup21, ReadAfterLd], (instregex "^P(DEP|EXT)(32|64)rm$")>;
+def LNLPWriteResGroup22 : SchedWriteRes<[LNLPPort01_03_05]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : InstRW<[LNLPWriteResGroup22], (instregex "^P(DEP|EXT)(32|64)rr$")>;
+def LNLPWriteResGroup23 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 2, 1];
+ let Latency = 9; // originally LunarlakePModel.MaxLatency;
+ let NumMicroOps = 4;
+}
+def : InstRW<[LNLPWriteResGroup23, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)SWrm$")>;
+def LNLPWriteResGroup24 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort02_03]> {
+ let ReleaseAtCycles = [1, 2];
+ let Latency = 2;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroup24], (instregex "^(V?)PH(ADD|SUB)SWrr$",
+ "^VPH(ADD|SUB)SWYrr$")>;
+def LNLPWriteResGroup25 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 6];
+ let Latency = 9;
+}
+def : InstRW<[LNLPWriteResGroup25, ReadAfterVecXLd], (instregex "^(V?)PMULUDQrm$")>;
+def : InstRW<[LNLPWriteResGroup25, ReadAfterVecXLd], (instrs VPMULDQrm)>;
+def LNLPWriteResGroup26 : SchedWriteRes<[LNLPVPort00_01]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 3;
+}
+def : InstRW<[LNLPWriteResGroup26], (instregex "^(V?)PMULUDQrr$",
+ "^VPMUL(U?)DQYrr$")>;
+def : InstRW<[LNLPWriteResGroup26], (instrs VMOVSDto64Zrr,
+ VPMULDQrr)>;
+
+def LNLPWriteResGroup27 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 1, 6];
+ let Latency = 8;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroup27, ReadAfterVecXLd], (instrs SHA1MSG1rm)>;
+def LNLPWriteResGroup28 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPVPort02_03]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup28], (instrs SHA1MSG1rr)>;
+def LNLPWriteResGroup29 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 1, 1, 6];
+ let Latency = 7; // Originally 8
+ let NumMicroOps = 4;
+}
+def : InstRW<[LNLPWriteResGroup29, ReadAfterVecXLd], (instrs SHA1NEXTErm)>;
+def LNLPWriteResGroup30 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort00_01_02_03, LNLPVPort02_03]> {
+ let Latency = 3; // originally LunarlakePModel.MaxLatency;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroup30], (instrs SHA1NEXTErr)>;
+def LNLPWriteResGroup31 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 6];
+ let Latency = LunarlakePModel.MaxLatency;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup31, ReadAfterVecXLd], (instrs SHA1RNDS4rmi)>;
+def LNLPWriteResGroup32 : SchedWriteRes<[LNLPVPort02_03]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 2;
+}
+def : InstRW<[LNLPWriteResGroup32], (instrs SHA1RNDS4rri,
+ SHA256RNDS2rr)>;
+def LNLPWriteResGroup33 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 6];
+ let Latency = 12 ; // orignally 99; diff lat for 1 & 2 version
+}
+def : InstRW<[LNLPWriteResGroup33, ReadAfterVecXLd], (instregex "^SHA256MSG(1|2)rm$")>;
+
+def LNLPWriteResGroup34 : SchedWriteRes<[LNLPVPort00_01]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 5; // orignally 99; Diff lat for 1 & 2 version
+}
+def : InstRW<[LNLPWriteResGroup34], (instregex "^SHA256MSG(1|2)rr$")>;
+def LNLPWriteResGroup35 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 6];
+ let Latency = 9;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup35, ReadAfterVecXLd], (instrs SHA256RNDS2rm)>;
+def LNLPWriteResGroup36 : SchedWriteRes<[LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [7];
+ let Latency = 7;
+}
+def : InstRW<[LNLPWriteResGroup36], (instregex "^VBROADCASTS(D|S)Yrm$",
+ "^VMOV(D|SH|SL)DUPYrm$",
+ "^VPBROADCAST(D|Q|W)Yrm$")>;
+def : InstRW<[LNLPWriteResGroup36], (instrs VBROADCASTF128rm)>;
+def LNLPWriteResGroup37 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 7];
+ let Latency = 11;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup37, ReadAfterVecYLd], (instregex "^VCMPP(D|S)Yrmi$")>;
+def LNLPWriteResGroup38 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 6];
+ let Latency = 10;
+}
+def : InstRW<[LNLPWriteResGroup38], (instregex "^VCVT(T?)PS2DQrm$")>;
+def LNLPWriteResGroup39 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [4, 1, 6];
+ let Latency = 11;
+ let NumMicroOps = 3;
+}
+def : InstRW<[LNLPWriteResGroup39, ReadAfterVecLd], (instrs VCVTSI642SSrm_Int)>;
+def LNLPWriteResGroup40 : SchedWriteRes<[LNLPPort10_11, LNLPPort25_26_27]> {
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup40], (instregex "^VEXTRACT(F|I)128mri$")>;
+def LNLPWriteResGroup41 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 7];
+ let Latency = 8;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup41, ReadAfterVecYLd], (instregex "^VINSERT(F|I)128rmi$")>;
+def LNLPWriteResGroup42 : SchedWriteRes<[LNLPVPort00_01]> {
+ let ReleaseAtCycles = [3];
+ let Latency = 4;
+}
+def : InstRW<[LNLPWriteResGroup42], (instregex "^VMOVMSKP(D|S)Yrr$")>;
+def LNLPWriteResGroup43 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 7];
+ let Latency = 10;
+}
+def : InstRW<[LNLPWriteResGroup43, ReadAfterVecYLd], (instregex "^VPACK(S|U)S(DW|WB)Yrm$")>;
+def : InstRW<[LNLPWriteResGroup43, ReadAfterVecYLd], (instrs VPCMPGTQYrm)>;
+def LNLPWriteResGroup44 : SchedWriteRes<[LNLPVPort00_01_02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 7];
+ let Latency = 8;
+}
+def : InstRW<[LNLPWriteResGroup44, ReadAfterVecYLd], (instregex "^VP(ADD|SUB)(B|D|Q|W)Yrm$")>;
+def LNLPWriteResGroup45 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 7];
+ let Latency = 8;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup45], (instregex "^VPSHUF(D|HW|LW)Ymi$")>;
+def : InstRW<[LNLPWriteResGroup45, ReadAfterVecYLd], (instrs VPALIGNRYrmi,
+ VPBLENDWYrmi)>;
+def LNLPWriteResGroup46 : SchedWriteRes<[LNLPVPort02_03]>;
+def : InstRW<[LNLPWriteResGroup46], (instregex "^VPBLENDW(Y?)rri$")>;
+def LNLPWriteResGroup47 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 7];
+ let Latency = 8;
+}
+def : InstRW<[LNLPWriteResGroup47], (instrs VPBROADCASTBYrm)>;
+def : InstRW<[LNLPWriteResGroup47, ReadAfterVecYLd], (instregex "^VUNPCK(H|L)P(D|S)Yrm$")>;
+def LNLPWriteResGroup48 : SchedWriteRes<[LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 7];
+ let Latency = 10;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup48, ReadAfterVecXLd], (instrs VPCLMULQDQYrmi)>;
+def LNLPWriteResGroup49 : SchedWriteRes<[LNLPVPort00_01, LNLPVPort02_03, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [1, 2, 7];
+ let Latency = 9;
+ let NumMicroOps = 4;
+}
+def : InstRW<[LNLPWriteResGroup49, ReadAfterVecYLd], (instregex "^VPH(ADD|SUB)SWYrm$")>;
+def LNLPWriteResGroup50 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 7];
+ let Latency = 10;
+}
+def : InstRW<[LNLPWriteResGroup50, ReadAfterVecYLd], (instregex "^VPMUL(U?)DQYrm$")>;
+def LNLPWriteResGroup51 : SchedWriteRes<[LNLPVPort02_03]> {
+ let ReleaseAtCycles = [3];
+ let Latency = LunarlakePModel.MaxLatency;
+}
+def : InstRW<[LNLPWriteResGroup51], (instrs VSHA512RNDS2rr)>;
+def LNLPWriteResGroup52 : SchedWriteRes<[LNLPVPort00_01, LNLPPort20_21_22]> {
+ let ReleaseAtCycles = [3, 6];
+ let Latency = LunarlakePModel.MaxLatency;
+ let NumMicroOps = 2;
+}
+def : InstRW<[LNLPWriteResGroup52], (instregex "^VSM3MSG(1|2)rm$")>;
+def LNLPWriteResGroup53 : SchedWriteRes<[LNLPVPort00_01]> {
+ let ReleaseAtCycles = [3];
+ let Latency = LunarlakePModel.MaxLatency;
+}
+def : InstRW<[LNLPWriteResGroup53], (instregex "^VSM3MSG(1|2)rr$")>;
+def : InstRW<[LNLPWriteResGroup53], (instrs VTESTPSYrr)>;
+}
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/independent-load-stores.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/independent-load-stores.s
new file mode 100644
index 0000000000000..c07cf7a80a380
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/independent-load-stores.s
@@ -0,0 +1,149 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -timeline -timeline-max-iterations=1 < %s | FileCheck %s -check-prefixes=ALL,NOALIAS
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -timeline -timeline-max-iterations=1 -noalias=false < %s | FileCheck %s -check-prefixes=ALL,YESALIAS
+
+ addq $44, 64(%r14)
+ addq $44, 128(%r14)
+ addq $44, 192(%r14)
+ addq $44, 256(%r14)
+ addq $44, 320(%r14)
+ addq $44, 384(%r14)
+ addq $44, 448(%r14)
+ addq $44, 512(%r14)
+ addq $44, 576(%r14)
+ addq $44, 640(%r14)
+
+# ALL: Iterations: 100
+# ALL-NEXT: Instructions: 1000
+
+# NOALIAS-NEXT: Total Cycles: 681
+# YESALIAS-NEXT: Total Cycles: 12003
+
+# ALL-NEXT: Total uOps: 4000
+
+# ALL: Dispatch Width: 8
+
+# NOALIAS-NEXT: uOps Per Cycle: 5.87
+# NOALIAS-NEXT: IPC: 1.47
+
+# YESALIAS-NEXT: uOps Per Cycle: 0.33
+# YESALIAS-NEXT: IPC: 0.08
+
+# ALL-NEXT: Block RThroughput: 6.7
+
+# ALL: Instruction Info:
+# ALL-NEXT: [1]: #uOps
+# ALL-NEXT: [2]: Latency
+# ALL-NEXT: [3]: RThroughput
+# ALL-NEXT: [4]: MayLoad
+# ALL-NEXT: [5]: MayStore
+# ALL-NEXT: [6]: HasSideEffects (U)
+
+# ALL: [1] [2] [3] [4] [5] [6] Instructions:
+# ALL-NEXT: 4 12 0.67 * * addq $44, 64(%r14)
+# ALL-NEXT: 4 12 0.67 * * addq $44, 128(%r14)
+# ALL-NEXT: 4 12 0.67 * * addq $44, 192(%r14)
+# ALL-NEXT: 4 12 0.67 * * addq $44, 256(%r14)
+# ALL-NEXT: 4 12 0.67 * * addq $44, 320(%r14)
+# ALL-NEXT: 4 12 0.67 * * addq $44, 384(%r14)
+# ALL-NEXT: 4 12 0.67 * * addq $44, 448(%r14)
+# ALL-NEXT: 4 12 0.67 * * addq $44, 512(%r14)
+# ALL-NEXT: 4 12 0.67 * * addq $44, 576(%r14)
+# ALL-NEXT: 4 12 0.67 * * addq $44, 640(%r14)
+
+# ALL: Resources:
+# ALL-NEXT: [0] - ADLPPort00
+# ALL-NEXT: [1] - LNLPPort00
+# ALL-NEXT: [2] - LNLPPort01
+# ALL-NEXT: [3] - LNLPPort02
+# ALL-NEXT: [4] - LNLPPort03
+# ALL-NEXT: [5] - LNLPPort04
+# ALL-NEXT: [6] - LNLPPort05
+# ALL-NEXT: [7] - LNLPPort10
+# ALL-NEXT: [8] - LNLPPort11
+# ALL-NEXT: [9] - LNLPPort20
+# ALL-NEXT: [10] - LNLPPort21
+# ALL-NEXT: [11] - LNLPPort22
+# ALL-NEXT: [12] - LNLPPort25
+# ALL-NEXT: [13] - LNLPPort26
+# ALL-NEXT: [14] - LNLPPort27
+# ALL-NEXT: [15] - LNLPPortInvalid
+# ALL-NEXT: [16] - LNLPVPort00
+# ALL-NEXT: [17] - LNLPVPort01
+# ALL-NEXT: [18] - LNLPVPort02
+# ALL-NEXT: [19] - LNLPVPort03
+
+# ALL: Resource pressure per iteration:
+# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# ALL-NEXT: - - 3.33 - 3.33 - 3.34 5.00 5.00 6.66 6.66 6.68 3.33 3.33 3.34 - - - - -
+
+# ALL: Resource pressure by instruction:
+# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# ALL-NEXT: - - 0.33 - 0.33 - 0.34 - 1.00 0.66 0.66 0.68 0.33 0.33 0.34 - - - - - addq $44, 64(%r14)
+# ALL-NEXT: - - 0.33 - 0.34 - 0.33 1.00 - 0.66 0.68 0.66 0.33 0.34 0.33 - - - - - addq $44, 128(%r14)
+# ALL-NEXT: - - 0.34 - 0.33 - 0.33 - 1.00 0.68 0.66 0.66 0.34 0.33 0.33 - - - - - addq $44, 192(%r14)
+# ALL-NEXT: - - 0.33 - 0.33 - 0.34 1.00 - 0.66 0.66 0.68 0.33 0.33 0.34 - - - - - addq $44, 256(%r14)
+# ALL-NEXT: - - 0.33 - 0.34 - 0.33 - 1.00 0.66 0.68 0.66 0.33 0.34 0.33 - - - - - addq $44, 320(%r14)
+# ALL-NEXT: - - 0.34 - 0.33 - 0.33 1.00 - 0.68 0.66 0.66 0.34 0.33 0.33 - - - - - addq $44, 384(%r14)
+# ALL-NEXT: - - 0.33 - 0.33 - 0.34 - 1.00 0.66 0.66 0.68 0.33 0.33 0.34 - - - - - addq $44, 448(%r14)
+# ALL-NEXT: - - 0.33 - 0.34 - 0.33 1.00 - 0.66 0.68 0.66 0.33 0.34 0.33 - - - - - addq $44, 512(%r14)
+# ALL-NEXT: - - 0.34 - 0.33 - 0.33 - 1.00 0.68 0.66 0.66 0.34 0.33 0.33 - - - - - addq $44, 576(%r14)
+# ALL-NEXT: - - 0.33 - 0.33 - 0.34 1.00 - 0.66 0.66 0.68 0.33 0.33 0.34 - - - - - addq $44, 640(%r14)
+
+# ALL: Timeline view:
+
+# NOALIAS-NEXT: 0123456789
+# NOALIAS-NEXT: Index 0123456789 0
+
+# YESALIAS-NEXT: 0123456789 0123456789 0123456789 01234
+# YESALIAS-NEXT: Index 0123456789 0123456789 0123456789 0123456789
+
+# NOALIAS: [0,0] DeeeeeeeeeeeeER. . addq $44, 64(%r14)
+# NOALIAS-NEXT: [0,1] DeeeeeeeeeeeeER. . addq $44, 128(%r14)
+# NOALIAS-NEXT: [0,2] .DeeeeeeeeeeeeER . addq $44, 192(%r14)
+# NOALIAS-NEXT: [0,3] .D=eeeeeeeeeeeeER . addq $44, 256(%r14)
+# NOALIAS-NEXT: [0,4] . DeeeeeeeeeeeeER . addq $44, 320(%r14)
+# NOALIAS-NEXT: [0,5] . D=eeeeeeeeeeeeER . addq $44, 384(%r14)
+# NOALIAS-NEXT: [0,6] . D=eeeeeeeeeeeeER . addq $44, 448(%r14)
+# NOALIAS-NEXT: [0,7] . D=eeeeeeeeeeeeER . addq $44, 512(%r14)
+# NOALIAS-NEXT: [0,8] . D=eeeeeeeeeeeeER. addq $44, 576(%r14)
+# NOALIAS-NEXT: [0,9] . D==eeeeeeeeeeeeER addq $44, 640(%r14)
+
+# YESALIAS: [0,0] DeeeeeeeeeeeeER. . . . . . . . . . . . . addq $44, 64(%r14)
+# YESALIAS-NEXT: [0,1] D============eeeeeeeeeeeeER . . . . . . . . . . addq $44, 128(%r14)
+# YESALIAS-NEXT: [0,2] .D=======================eeeeeeeeeeeeER . . . . . . . . addq $44, 192(%r14)
+# YESALIAS-NEXT: [0,3] .D===================================eeeeeeeeeeeeER . . . . . addq $44, 256(%r14)
+# YESALIAS-NEXT: [0,4] . D==============================================eeeeeeeeeeeeER . . . addq $44, 320(%r14)
+# YESALIAS-NEXT: [0,5] . D==========================================================eeeeeeeeeeeeER addq $44, 384(%r14)
+# YESALIAS-NEXT: Truncated display due to cycle limit
+
+# ALL: Average Wait times (based on the timeline view):
+# ALL-NEXT: [0]: Executions
+# ALL-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# ALL-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# ALL-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# ALL: [0] [1] [2] [3]
+# ALL-NEXT: 0. 1 1.0 1.0 0.0 addq $44, 64(%r14)
+
+# NOALIAS-NEXT: 1. 1 1.0 0.0 0.0 addq $44, 128(%r14)
+# NOALIAS-NEXT: 2. 1 1.0 1.0 0.0 addq $44, 192(%r14)
+# NOALIAS-NEXT: 3. 1 2.0 1.0 0.0 addq $44, 256(%r14)
+# NOALIAS-NEXT: 4. 1 1.0 0.0 0.0 addq $44, 320(%r14)
+# NOALIAS-NEXT: 5. 1 2.0 1.0 0.0 addq $44, 384(%r14)
+# NOALIAS-NEXT: 6. 1 2.0 1.0 0.0 addq $44, 448(%r14)
+# NOALIAS-NEXT: 7. 1 2.0 0.0 0.0 addq $44, 512(%r14)
+# NOALIAS-NEXT: 8. 1 2.0 1.0 0.0 addq $44, 576(%r14)
+# NOALIAS-NEXT: 9. 1 3.0 1.0 0.0 addq $44, 640(%r14)
+# NOALIAS-NEXT: 1 1.7 0.7 0.0 <total>
+
+# YESALIAS-NEXT: 1. 1 13.0 0.0 0.0 addq $44, 128(%r14)
+# YESALIAS-NEXT: 2. 1 24.0 0.0 0.0 addq $44, 192(%r14)
+# YESALIAS-NEXT: 3. 1 36.0 0.0 0.0 addq $44, 256(%r14)
+# YESALIAS-NEXT: 4. 1 47.0 0.0 0.0 addq $44, 320(%r14)
+# YESALIAS-NEXT: 5. 1 59.0 0.0 0.0 addq $44, 384(%r14)
+# YESALIAS-NEXT: 6. 1 70.0 0.0 0.0 addq $44, 448(%r14)
+# YESALIAS-NEXT: 7. 1 82.0 0.0 0.0 addq $44, 512(%r14)
+# YESALIAS-NEXT: 8. 1 93.0 0.0 0.0 addq $44, 576(%r14)
+# YESALIAS-NEXT: 9. 1 105.0 0.0 0.0 addq $44, 640(%r14)
+# YESALIAS-NEXT: 1 53.0 0.1 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/partially-overlapping-groups.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/partially-overlapping-groups.s
new file mode 100644
index 0000000000000..c118824ba79c2
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/partially-overlapping-groups.s
@@ -0,0 +1,21 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -all-views=false -summary-view < %s | FileCheck %s
+
+# Issue #57548
+
+# Do not crash when simulating instructions that consume partially overlapping
+# resource groups.
+
+vpsllw %xmm1, %ymm0, %ymm0
+vpsllw %xmm1, %xmm2, %xmm1
+vpand %ymm1, %ymm0, %ymm0
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 300
+# CHECK-NEXT: Total Cycles: 503
+# CHECK-NEXT: Total uOps: 500
+
+# CHECK: Dispatch Width: 8
+# CHECK-NEXT: uOps Per Cycle: 0.99
+# CHECK-NEXT: IPC: 0.60
+# CHECK-NEXT: Block RThroughput: 1.0
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-aes.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-aes.s
new file mode 100644
index 0000000000000..a434b12e0eafe
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-aes.s
@@ -0,0 +1,69 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+aesdec %xmm0, %xmm2
+aesdec (%rax), %xmm2
+
+aesdeclast %xmm0, %xmm2
+aesdeclast (%rax), %xmm2
+
+aesenc %xmm0, %xmm2
+aesenc (%rax), %xmm2
+
+aesenclast %xmm0, %xmm2
+aesenclast (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 2.00 aesdec %xmm0, %xmm2
+# CHECK-NEXT: 2 11 2.33 * aesdec (%rax), %xmm2
+# CHECK-NEXT: 1 3 2.00 aesdeclast %xmm0, %xmm2
+# CHECK-NEXT: 2 11 2.33 * aesdeclast (%rax), %xmm2
+# CHECK-NEXT: 1 3 2.00 aesenc %xmm0, %xmm2
+# CHECK-NEXT: 2 11 2.33 * aesenc (%rax), %xmm2
+# CHECK-NEXT: 1 3 2.00 aesenclast %xmm0, %xmm2
+# CHECK-NEXT: 2 11 2.33 * aesenclast (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - - - - - - - - - 9.33 9.33 9.33 - - - - 16.00 16.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - aesdec %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - aesdec (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - aesdeclast %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - aesdeclast (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - aesenc %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - aesenc (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - aesenclast %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - aesenclast (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avx1.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avx1.s
new file mode 100644
index 0000000000000..789203d11e0ea
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avx1.s
@@ -0,0 +1,2429 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+vaddpd %xmm0, %xmm1, %xmm2
+vaddpd (%rax), %xmm1, %xmm2
+
+vaddpd %ymm0, %ymm1, %ymm2
+vaddpd (%rax), %ymm1, %ymm2
+
+vaddps %xmm0, %xmm1, %xmm2
+vaddps (%rax), %xmm1, %xmm2
+
+vaddps %ymm0, %ymm1, %ymm2
+vaddps (%rax), %ymm1, %ymm2
+
+vaddsd %xmm0, %xmm1, %xmm2
+vaddsd (%rax), %xmm1, %xmm2
+
+vaddss %xmm0, %xmm1, %xmm2
+vaddss (%rax), %xmm1, %xmm2
+
+vaddsubpd %xmm0, %xmm1, %xmm2
+vaddsubpd (%rax), %xmm1, %xmm2
+
+vaddsubpd %ymm0, %ymm1, %ymm2
+vaddsubpd (%rax), %ymm1, %ymm2
+
+vaddsubps %xmm0, %xmm1, %xmm2
+vaddsubps (%rax), %xmm1, %xmm2
+
+vaddsubps %ymm0, %ymm1, %ymm2
+vaddsubps (%rax), %ymm1, %ymm2
+
+vaesdec %xmm0, %xmm1, %xmm2
+vaesdec (%rax), %xmm1, %xmm2
+
+vaesdeclast %xmm0, %xmm1, %xmm2
+vaesdeclast (%rax), %xmm1, %xmm2
+
+vaesenc %xmm0, %xmm1, %xmm2
+vaesenc (%rax), %xmm1, %xmm2
+
+vaesenclast %xmm0, %xmm1, %xmm2
+vaesenclast (%rax), %xmm1, %xmm2
+
+vandnpd %xmm0, %xmm1, %xmm2
+vandnpd (%rax), %xmm1, %xmm2
+
+vandnpd %ymm0, %ymm1, %ymm2
+vandnpd (%rax), %ymm1, %ymm2
+
+vandnps %xmm0, %xmm1, %xmm2
+vandnps (%rax), %xmm1, %xmm2
+
+vandnps %ymm0, %ymm1, %ymm2
+vandnps (%rax), %ymm1, %ymm2
+
+vandpd %xmm0, %xmm1, %xmm2
+vandpd (%rax), %xmm1, %xmm2
+
+vandpd %ymm0, %ymm1, %ymm2
+vandpd (%rax), %ymm1, %ymm2
+
+vandps %xmm0, %xmm1, %xmm2
+vandps (%rax), %xmm1, %xmm2
+
+vandps %ymm0, %ymm1, %ymm2
+vandps (%rax), %ymm1, %ymm2
+
+vblendpd $11, %xmm0, %xmm1, %xmm2
+vblendpd $11, (%rax), %xmm1, %xmm2
+
+vblendpd $11, %ymm0, %ymm1, %ymm2
+vblendpd $11, (%rax), %ymm1, %ymm2
+
+vblendps $11, %xmm0, %xmm1, %xmm2
+vblendps $11, (%rax), %xmm1, %xmm2
+
+vblendps $11, %ymm0, %ymm1, %ymm2
+vblendps $11, (%rax), %ymm1, %ymm2
+
+vblendvpd %xmm3, %xmm0, %xmm1, %xmm2
+vblendvpd %xmm3, (%rax), %xmm1, %xmm2
+
+vblendvpd %ymm3, %ymm0, %ymm1, %ymm2
+vblendvpd %ymm3, (%rax), %ymm1, %ymm2
+
+vblendvps %xmm3, %xmm0, %xmm1, %xmm2
+vblendvps %xmm3, (%rax), %xmm1, %xmm2
+
+vblendvps %ymm3, %ymm0, %ymm1, %ymm2
+vblendvps %ymm3, (%rax), %ymm1, %ymm2
+
+vbroadcastf128 (%rax), %ymm2
+
+vbroadcastsd (%rax), %ymm2
+
+vbroadcastss (%rax), %xmm2
+vbroadcastss (%rax), %ymm2
+
+vcmppd $0, %xmm0, %xmm1, %xmm2
+vcmppd $0, (%rax), %xmm1, %xmm2
+
+vcmppd $0, %ymm0, %ymm1, %ymm2
+vcmppd $0, (%rax), %ymm1, %ymm2
+
+vcmpps $0, %xmm0, %xmm1, %xmm2
+vcmpps $0, (%rax), %xmm1, %xmm2
+
+vcmpps $0, %ymm0, %ymm1, %ymm2
+vcmpps $0, (%rax), %ymm1, %ymm2
+
+vcmpsd $0, %xmm0, %xmm1, %xmm2
+vcmpsd $0, (%rax), %xmm1, %xmm2
+
+vcmpss $0, %xmm0, %xmm1, %xmm2
+vcmpss $0, (%rax), %xmm1, %xmm2
+
+vcomisd %xmm0, %xmm1
+vcomisd (%rax), %xmm1
+
+vcomiss %xmm0, %xmm1
+vcomiss (%rax), %xmm1
+
+vcvtdq2pd %xmm0, %xmm2
+vcvtdq2pd (%rax), %xmm2
+
+vcvtdq2pd %xmm0, %ymm2
+vcvtdq2pd (%rax), %ymm2
+
+vcvtdq2ps %xmm0, %xmm2
+vcvtdq2ps (%rax), %xmm2
+
+vcvtdq2ps %ymm0, %ymm2
+vcvtdq2ps (%rax), %ymm2
+
+vcvtpd2dqx %xmm0, %xmm2
+vcvtpd2dqx (%rax), %xmm2
+
+vcvtpd2dqy %ymm0, %xmm2
+vcvtpd2dqy (%rax), %xmm2
+
+vcvtpd2psx %xmm0, %xmm2
+vcvtpd2psx (%rax), %xmm2
+
+vcvtpd2psy %ymm0, %xmm2
+vcvtpd2psy (%rax), %xmm2
+
+vcvtps2dq %xmm0, %xmm2
+vcvtps2dq (%rax), %xmm2
+
+vcvtps2dq %ymm0, %ymm2
+vcvtps2dq (%rax), %ymm2
+
+vcvtps2pd %xmm0, %xmm2
+vcvtps2pd (%rax), %xmm2
+
+vcvtps2pd %xmm0, %ymm2
+vcvtps2pd (%rax), %ymm2
+
+vcvtsd2si %xmm0, %ecx
+vcvtsd2si %xmm0, %rcx
+vcvtsd2si (%rax), %ecx
+vcvtsd2si (%rax), %rcx
+
+vcvtsd2ss %xmm0, %xmm1, %xmm2
+vcvtsd2ss (%rax), %xmm1, %xmm2
+
+vcvtsi2sdl %ecx, %xmm0, %xmm2
+vcvtsi2sdq %rcx, %xmm0, %xmm2
+vcvtsi2sdl (%rax), %xmm0, %xmm2
+vcvtsi2sdq (%rax), %xmm0, %xmm2
+
+vcvtsi2ssl %ecx, %xmm0, %xmm2
+vcvtsi2ssq %rcx, %xmm0, %xmm2
+vcvtsi2ssl (%rax), %xmm0, %xmm2
+vcvtsi2ssq (%rax), %xmm0, %xmm2
+
+vcvtss2sd %xmm0, %xmm1, %xmm2
+vcvtss2sd (%rax), %xmm1, %xmm2
+
+vcvtss2si %xmm0, %ecx
+vcvtss2si %xmm0, %rcx
+vcvtss2si (%rax), %ecx
+vcvtss2si (%rax), %rcx
+
+vcvttpd2dqx %xmm0, %xmm2
+vcvttpd2dqx (%rax), %xmm2
+
+vcvttpd2dqy %ymm0, %xmm2
+vcvttpd2dqy (%rax), %xmm2
+
+vcvttps2dq %xmm0, %xmm2
+vcvttps2dq (%rax), %xmm2
+
+vcvttps2dq %ymm0, %ymm2
+vcvttps2dq (%rax), %ymm2
+
+vcvttsd2si %xmm0, %ecx
+vcvttsd2si %xmm0, %rcx
+vcvttsd2si (%rax), %ecx
+vcvttsd2si (%rax), %rcx
+
+vcvttss2si %xmm0, %ecx
+vcvttss2si %xmm0, %rcx
+vcvttss2si (%rax), %ecx
+vcvttss2si (%rax), %rcx
+
+vdivpd %xmm0, %xmm1, %xmm2
+vdivpd (%rax), %xmm1, %xmm2
+
+vdivpd %ymm0, %ymm1, %ymm2
+vdivpd (%rax), %ymm1, %ymm2
+
+vdivps %xmm0, %xmm1, %xmm2
+vdivps (%rax), %xmm1, %xmm2
+
+vdivps %ymm0, %ymm1, %ymm2
+vdivps (%rax), %ymm1, %ymm2
+
+vdivsd %xmm0, %xmm1, %xmm2
+vdivsd (%rax), %xmm1, %xmm2
+
+vdivss %xmm0, %xmm1, %xmm2
+vdivss (%rax), %xmm1, %xmm2
+
+vdppd $22, %xmm0, %xmm1, %xmm2
+vdppd $22, (%rax), %xmm1, %xmm2
+
+vdpps $22, %xmm0, %xmm1, %xmm2
+vdpps $22, (%rax), %xmm1, %xmm2
+
+vdpps $22, %ymm0, %ymm1, %ymm2
+vdpps $22, (%rax), %ymm1, %ymm2
+
+vextractf128 $1, %ymm0, %xmm2
+vextractf128 $1, %ymm0, (%rax)
+
+vextractps $1, %xmm0, %rcx
+vextractps $1, %xmm0, (%rax)
+
+vhaddpd %xmm0, %xmm1, %xmm2
+vhaddpd (%rax), %xmm1, %xmm2
+
+vhaddpd %ymm0, %ymm1, %ymm2
+vhaddpd (%rax), %ymm1, %ymm2
+
+vhaddps %xmm0, %xmm1, %xmm2
+vhaddps (%rax), %xmm1, %xmm2
+
+vhaddps %ymm0, %ymm1, %ymm2
+vhaddps (%rax), %ymm1, %ymm2
+
+vhsubpd %xmm0, %xmm1, %xmm2
+vhsubpd (%rax), %xmm1, %xmm2
+
+vhsubpd %ymm0, %ymm1, %ymm2
+vhsubpd (%rax), %ymm1, %ymm2
+
+vhsubps %xmm0, %xmm1, %xmm2
+vhsubps (%rax), %xmm1, %xmm2
+
+vhsubps %ymm0, %ymm1, %ymm2
+vhsubps (%rax), %ymm1, %ymm2
+
+vinsertf128 $1, %xmm0, %ymm1, %ymm2
+vinsertf128 $1, (%rax), %ymm1, %ymm2
+
+vinsertps $1, %xmm0, %xmm1, %xmm2
+vinsertps $1, (%rax), %xmm1, %xmm2
+
+vlddqu (%rax), %xmm2
+vlddqu (%rax), %ymm2
+
+vldmxcsr (%rax)
+
+vmaskmovdqu %xmm0, %xmm1
+
+vmaskmovpd (%rax), %xmm0, %xmm2
+vmaskmovpd (%rax), %ymm0, %ymm2
+
+vmaskmovpd %xmm0, %xmm1, (%rax)
+vmaskmovpd %ymm0, %ymm1, (%rax)
+
+vmaskmovps (%rax), %xmm0, %xmm2
+vmaskmovps (%rax), %ymm0, %ymm2
+
+vmaskmovps %xmm0, %xmm1, (%rax)
+vmaskmovps %ymm0, %ymm1, (%rax)
+
+vmaxpd %xmm0, %xmm1, %xmm2
+vmaxpd (%rax), %xmm1, %xmm2
+
+vmaxpd %ymm0, %ymm1, %ymm2
+vmaxpd (%rax), %ymm1, %ymm2
+
+vmaxps %xmm0, %xmm1, %xmm2
+vmaxps (%rax), %xmm1, %xmm2
+
+vmaxps %ymm0, %ymm1, %ymm2
+vmaxps (%rax), %ymm1, %ymm2
+
+vmaxsd %xmm0, %xmm1, %xmm2
+vmaxsd (%rax), %xmm1, %xmm2
+
+vmaxss %xmm0, %xmm1, %xmm2
+vmaxss (%rax), %xmm1, %xmm2
+
+vminpd %xmm0, %xmm1, %xmm2
+vminpd (%rax), %xmm1, %xmm2
+
+vminpd %ymm0, %ymm1, %ymm2
+vminpd (%rax), %ymm1, %ymm2
+
+vminps %xmm0, %xmm1, %xmm2
+vminps (%rax), %xmm1, %xmm2
+
+vminps %ymm0, %ymm1, %ymm2
+vminps (%rax), %ymm1, %ymm2
+
+vminsd %xmm0, %xmm1, %xmm2
+vminsd (%rax), %xmm1, %xmm2
+
+vminss %xmm0, %xmm1, %xmm2
+vminss (%rax), %xmm1, %xmm2
+
+vmovapd %xmm0, %xmm2
+vmovapd %xmm0, (%rax)
+vmovapd (%rax), %xmm2
+
+vmovapd %ymm0, %ymm2
+vmovapd %ymm0, (%rax)
+vmovapd (%rax), %ymm2
+
+vmovaps %xmm0, %xmm2
+vmovaps %xmm0, (%rax)
+vmovaps (%rax), %xmm2
+
+vmovaps %ymm0, %ymm2
+vmovaps %ymm0, (%rax)
+vmovaps (%rax), %ymm2
+
+vmovd %eax, %xmm2
+vmovd (%rax), %xmm2
+
+vmovd %xmm0, %ecx
+vmovd %xmm0, (%rax)
+
+vmovddup %xmm0, %xmm2
+vmovddup (%rax), %xmm2
+
+vmovddup %ymm0, %ymm2
+vmovddup (%rax), %ymm2
+
+vmovdqa %xmm0, %xmm2
+vmovdqa %xmm0, (%rax)
+vmovdqa (%rax), %xmm2
+
+vmovdqa %ymm0, %ymm2
+vmovdqa %ymm0, (%rax)
+vmovdqa (%rax), %ymm2
+
+vmovdqu %xmm0, %xmm2
+vmovdqu %xmm0, (%rax)
+vmovdqu (%rax), %xmm2
+
+vmovdqu %ymm0, %ymm2
+vmovdqu %ymm0, (%rax)
+vmovdqu (%rax), %ymm2
+
+vmovhlps %xmm0, %xmm1, %xmm2
+vmovlhps %xmm0, %xmm1, %xmm2
+
+vmovhpd %xmm0, (%rax)
+vmovhpd (%rax), %xmm1, %xmm2
+
+vmovhps %xmm0, (%rax)
+vmovhps (%rax), %xmm1, %xmm2
+
+vmovlpd %xmm0, (%rax)
+vmovlpd (%rax), %xmm1, %xmm2
+
+vmovlps %xmm0, (%rax)
+vmovlps (%rax), %xmm1, %xmm2
+
+vmovmskpd %xmm0, %rcx
+vmovmskpd %ymm0, %rcx
+
+vmovmskps %xmm0, %rcx
+vmovmskps %ymm0, %rcx
+
+vmovntdq %xmm0, (%rax)
+vmovntdq %ymm0, (%rax)
+
+vmovntdqa (%rax), %xmm2
+vmovntdqa (%rax), %ymm2
+
+vmovntpd %xmm0, (%rax)
+vmovntpd %ymm0, (%rax)
+
+vmovntps %xmm0, (%rax)
+vmovntps %ymm0, (%rax)
+
+vmovq %xmm0, %xmm2
+
+vmovq %rax, %xmm2
+vmovq (%rax), %xmm2
+
+vmovq %xmm0, %rcx
+vmovq %xmm0, (%rax)
+
+vmovsd %xmm0, %xmm1, %xmm2
+vmovsd %xmm0, (%rax)
+vmovsd (%rax), %xmm2
+
+vmovshdup %xmm0, %xmm2
+vmovshdup (%rax), %xmm2
+
+vmovshdup %ymm0, %ymm2
+vmovshdup (%rax), %ymm2
+
+vmovsldup %xmm0, %xmm2
+vmovsldup (%rax), %xmm2
+
+vmovsldup %ymm0, %ymm2
+vmovsldup (%rax), %ymm2
+
+vmovss %xmm0, %xmm1, %xmm2
+vmovss %xmm0, (%rax)
+vmovss (%rax), %xmm2
+
+vmovupd %xmm0, %xmm2
+vmovupd %xmm0, (%rax)
+vmovupd (%rax), %xmm2
+
+vmovupd %ymm0, %ymm2
+vmovupd %ymm0, (%rax)
+vmovupd (%rax), %ymm2
+
+vmovups %xmm0, %xmm2
+vmovups %xmm0, (%rax)
+vmovups (%rax), %xmm2
+
+vmovups %ymm0, %ymm2
+vmovups %ymm0, (%rax)
+vmovups (%rax), %ymm2
+
+vmpsadbw $1, %xmm0, %xmm1, %xmm2
+vmpsadbw $1, (%rax), %xmm1, %xmm2
+
+vmulpd %xmm0, %xmm1, %xmm2
+vmulpd (%rax), %xmm1, %xmm2
+
+vmulpd %ymm0, %ymm1, %ymm2
+vmulpd (%rax), %ymm1, %ymm2
+
+vmulps %xmm0, %xmm1, %xmm2
+vmulps (%rax), %xmm1, %xmm2
+
+vmulps %ymm0, %ymm1, %ymm2
+vmulps (%rax), %ymm1, %ymm2
+
+vmulsd %xmm0, %xmm1, %xmm2
+vmulsd (%rax), %xmm1, %xmm2
+
+vmulss %xmm0, %xmm1, %xmm2
+vmulss (%rax), %xmm1, %xmm2
+
+vorpd %xmm0, %xmm1, %xmm2
+vorpd (%rax), %xmm1, %xmm2
+
+vorpd %ymm0, %ymm1, %ymm2
+vorpd (%rax), %ymm1, %ymm2
+
+vorps %xmm0, %xmm1, %xmm2
+vorps (%rax), %xmm1, %xmm2
+
+vorps %ymm0, %ymm1, %ymm2
+vorps (%rax), %ymm1, %ymm2
+
+vpabsb %xmm0, %xmm2
+vpabsb (%rax), %xmm2
+
+vpabsd %xmm0, %xmm2
+vpabsd (%rax), %xmm2
+
+vpabsw %xmm0, %xmm2
+vpabsw (%rax), %xmm2
+
+vpackssdw %xmm0, %xmm1, %xmm2
+vpackssdw (%rax), %xmm1, %xmm2
+
+vpacksswb %xmm0, %xmm1, %xmm2
+vpacksswb (%rax), %xmm1, %xmm2
+
+vpackusdw %xmm0, %xmm1, %xmm2
+vpackusdw (%rax), %xmm1, %xmm2
+
+vpackuswb %xmm0, %xmm1, %xmm2
+vpackuswb (%rax), %xmm1, %xmm2
+
+vpaddb %xmm0, %xmm1, %xmm2
+vpaddb (%rax), %xmm1, %xmm2
+
+vpaddd %xmm0, %xmm1, %xmm2
+vpaddd (%rax), %xmm1, %xmm2
+
+vpaddq %xmm0, %xmm1, %xmm2
+vpaddq (%rax), %xmm1, %xmm2
+
+vpaddsb %xmm0, %xmm1, %xmm2
+vpaddsb (%rax), %xmm1, %xmm2
+
+vpaddsw %xmm0, %xmm1, %xmm2
+vpaddsw (%rax), %xmm1, %xmm2
+
+vpaddusb %xmm0, %xmm1, %xmm2
+vpaddusb (%rax), %xmm1, %xmm2
+
+vpaddusw %xmm0, %xmm1, %xmm2
+vpaddusw (%rax), %xmm1, %xmm2
+
+vpaddw %xmm0, %xmm1, %xmm2
+vpaddw (%rax), %xmm1, %xmm2
+
+vpalignr $1, %xmm0, %xmm1, %xmm2
+vpalignr $1, (%rax), %xmm1, %xmm2
+
+vpand %xmm0, %xmm1, %xmm2
+vpand (%rax), %xmm1, %xmm2
+
+vpandn %xmm0, %xmm1, %xmm2
+vpandn (%rax), %xmm1, %xmm2
+
+vpavgb %xmm0, %xmm1, %xmm2
+vpavgb (%rax), %xmm1, %xmm2
+
+vpavgw %xmm0, %xmm1, %xmm2
+vpavgw (%rax), %xmm1, %xmm2
+
+vpblendvb %xmm3, %xmm0, %xmm1, %xmm2
+vpblendvb %xmm3, (%rax), %xmm1, %xmm2
+
+vpblendw $11, %xmm0, %xmm1, %xmm2
+vpblendw $11, (%rax), %xmm1, %xmm2
+
+vpclmulqdq $11, %xmm0, %xmm1, %xmm2
+vpclmulqdq $11, (%rax), %xmm1, %xmm2
+
+vpcmpeqb %xmm0, %xmm1, %xmm2
+vpcmpeqb (%rax), %xmm1, %xmm2
+
+vpcmpeqd %xmm0, %xmm1, %xmm2
+vpcmpeqd (%rax), %xmm1, %xmm2
+
+vpcmpeqq %xmm0, %xmm1, %xmm2
+vpcmpeqq (%rax), %xmm1, %xmm2
+
+vpcmpeqw %xmm0, %xmm1, %xmm2
+vpcmpeqw (%rax), %xmm1, %xmm2
+
+vpcmpestri $1, %xmm0, %xmm2
+vpcmpestri $1, (%rax), %xmm2
+
+vpcmpestrm $1, %xmm0, %xmm2
+vpcmpestrm $1, (%rax), %xmm2
+
+vpcmpgtb %xmm0, %xmm1, %xmm2
+vpcmpgtb (%rax), %xmm1, %xmm2
+
+vpcmpgtd %xmm0, %xmm1, %xmm2
+vpcmpgtd (%rax), %xmm1, %xmm2
+
+vpcmpgtq %xmm0, %xmm1, %xmm2
+vpcmpgtq (%rax), %xmm1, %xmm2
+
+vpcmpgtw %xmm0, %xmm1, %xmm2
+vpcmpgtw (%rax), %xmm1, %xmm2
+
+vpcmpistri $1, %xmm0, %xmm2
+vpcmpistri $1, (%rax), %xmm2
+
+vpcmpistrm $1, %xmm0, %xmm2
+vpcmpistrm $1, (%rax), %xmm2
+
+vperm2f128 $1, %ymm0, %ymm1, %ymm2
+vperm2f128 $1, (%rax), %ymm1, %ymm2
+
+vpermilpd $1, %xmm0, %xmm2
+vpermilpd $1, (%rax), %xmm2
+vpermilpd %xmm0, %xmm1, %xmm2
+vpermilpd (%rax), %xmm1, %xmm2
+
+vpermilpd $1, %ymm0, %ymm2
+vpermilpd $1, (%rax), %ymm2
+vpermilpd %ymm0, %ymm1, %ymm2
+vpermilpd (%rax), %ymm1, %ymm2
+
+vpermilps $1, %xmm0, %xmm2
+vpermilps $1, (%rax), %xmm2
+vpermilps %xmm0, %xmm1, %xmm2
+vpermilps (%rax), %xmm1, %xmm2
+
+vpermilps $1, %ymm0, %ymm2
+vpermilps $1, (%rax), %ymm2
+vpermilps %ymm0, %ymm1, %ymm2
+vpermilps (%rax), %ymm1, %ymm2
+
+vpextrb $1, %xmm0, %ecx
+vpextrb $1, %xmm0, (%rax)
+
+vpextrd $1, %xmm0, %ecx
+vpextrd $1, %xmm0, (%rax)
+
+vpextrq $1, %xmm0, %rcx
+vpextrq $1, %xmm0, (%rax)
+
+vpextrw $1, %xmm0, %ecx
+vpextrw $1, %xmm0, (%rax)
+
+vphaddd %xmm0, %xmm1, %xmm2
+vphaddd (%rax), %xmm1, %xmm2
+
+vphaddsw %xmm0, %xmm1, %xmm2
+vphaddsw (%rax), %xmm1, %xmm2
+
+vphaddw %xmm0, %xmm1, %xmm2
+vphaddw (%rax), %xmm1, %xmm2
+
+vphminposuw %xmm0, %xmm2
+vphminposuw (%rax), %xmm2
+
+vphsubd %xmm0, %xmm1, %xmm2
+vphsubd (%rax), %xmm1, %xmm2
+
+vphsubsw %xmm0, %xmm1, %xmm2
+vphsubsw (%rax), %xmm1, %xmm2
+
+vphsubw %xmm0, %xmm1, %xmm2
+vphsubw (%rax), %xmm1, %xmm2
+
+vpinsrb $1, %eax, %xmm1, %xmm2
+vpinsrb $1, (%rax), %xmm1, %xmm2
+
+vpinsrd $1, %eax, %xmm1, %xmm2
+vpinsrd $1, (%rax), %xmm1, %xmm2
+
+vpinsrq $1, %rax, %xmm1, %xmm2
+vpinsrq $1, (%rax), %xmm1, %xmm2
+
+vpinsrw $1, %eax, %xmm1, %xmm2
+vpinsrw $1, (%rax), %xmm1, %xmm2
+
+vpmaddubsw %xmm0, %xmm1, %xmm2
+vpmaddubsw (%rax), %xmm1, %xmm2
+
+vpmaddwd %xmm0, %xmm1, %xmm2
+vpmaddwd (%rax), %xmm1, %xmm2
+
+vpmaxsb %xmm0, %xmm1, %xmm2
+vpmaxsb (%rax), %xmm1, %xmm2
+
+vpmaxsd %xmm0, %xmm1, %xmm2
+vpmaxsd (%rax), %xmm1, %xmm2
+
+vpmaxsw %xmm0, %xmm1, %xmm2
+vpmaxsw (%rax), %xmm1, %xmm2
+
+vpmaxub %xmm0, %xmm1, %xmm2
+vpmaxub (%rax), %xmm1, %xmm2
+
+vpmaxud %xmm0, %xmm1, %xmm2
+vpmaxud (%rax), %xmm1, %xmm2
+
+vpmaxuw %xmm0, %xmm1, %xmm2
+vpmaxuw (%rax), %xmm1, %xmm2
+
+vpminsb %xmm0, %xmm1, %xmm2
+vpminsb (%rax), %xmm1, %xmm2
+
+vpminsd %xmm0, %xmm1, %xmm2
+vpminsd (%rax), %xmm1, %xmm2
+
+vpminsw %xmm0, %xmm1, %xmm2
+vpminsw (%rax), %xmm1, %xmm2
+
+vpminub %xmm0, %xmm1, %xmm2
+vpminub (%rax), %xmm1, %xmm2
+
+vpminud %xmm0, %xmm1, %xmm2
+vpminud (%rax), %xmm1, %xmm2
+
+vpminuw %xmm0, %xmm1, %xmm2
+vpminuw (%rax), %xmm1, %xmm2
+
+vpmovmskb %xmm0, %rcx
+
+vpmovsxbd %xmm0, %xmm2
+vpmovsxbd (%rax), %xmm2
+
+vpmovsxbq %xmm0, %xmm2
+vpmovsxbq (%rax), %xmm2
+
+vpmovsxbw %xmm0, %xmm2
+vpmovsxbw (%rax), %xmm2
+
+vpmovsxdq %xmm0, %xmm2
+vpmovsxdq (%rax), %xmm2
+
+vpmovsxwd %xmm0, %xmm2
+vpmovsxwd (%rax), %xmm2
+
+vpmovsxwq %xmm0, %xmm2
+vpmovsxwq (%rax), %xmm2
+
+vpmovzxbd %xmm0, %xmm2
+vpmovzxbd (%rax), %xmm2
+
+vpmovzxbq %xmm0, %xmm2
+vpmovzxbq (%rax), %xmm2
+
+vpmovzxbw %xmm0, %xmm2
+vpmovzxbw (%rax), %xmm2
+
+vpmovzxdq %xmm0, %xmm2
+vpmovzxdq (%rax), %xmm2
+
+vpmovzxwd %xmm0, %xmm2
+vpmovzxwd (%rax), %xmm2
+
+vpmovzxwq %xmm0, %xmm2
+vpmovzxwq (%rax), %xmm2
+
+vpmuldq %xmm0, %xmm1, %xmm2
+vpmuldq (%rax), %xmm1, %xmm2
+
+vpmulhrsw %xmm0, %xmm1, %xmm2
+vpmulhrsw (%rax), %xmm1, %xmm2
+
+vpmulhuw %xmm0, %xmm1, %xmm2
+vpmulhuw (%rax), %xmm1, %xmm2
+
+vpmulhw %xmm0, %xmm1, %xmm2
+vpmulhw (%rax), %xmm1, %xmm2
+
+vpmulld %xmm0, %xmm1, %xmm2
+vpmulld (%rax), %xmm1, %xmm2
+
+vpmullw %xmm0, %xmm1, %xmm2
+vpmullw (%rax), %xmm1, %xmm2
+
+vpmuludq %xmm0, %xmm1, %xmm2
+vpmuludq (%rax), %xmm1, %xmm2
+
+vpor %xmm0, %xmm1, %xmm2
+vpor (%rax), %xmm1, %xmm2
+
+vpsadbw %xmm0, %xmm1, %xmm2
+vpsadbw (%rax), %xmm1, %xmm2
+
+vpshufb %xmm0, %xmm1, %xmm2
+vpshufb (%rax), %xmm1, %xmm2
+
+vpshufd $1, %xmm0, %xmm2
+vpshufd $1, (%rax), %xmm2
+
+vpshufhw $1, %xmm0, %xmm2
+vpshufhw $1, (%rax), %xmm2
+
+vpshuflw $1, %xmm0, %xmm2
+vpshuflw $1, (%rax), %xmm2
+
+vpsignb %xmm0, %xmm1, %xmm2
+vpsignb (%rax), %xmm1, %xmm2
+
+vpsignd %xmm0, %xmm1, %xmm2
+vpsignd (%rax), %xmm1, %xmm2
+
+vpsignw %xmm0, %xmm1, %xmm2
+vpsignw (%rax), %xmm1, %xmm2
+
+vpslld $1, %xmm0, %xmm2
+vpslld %xmm0, %xmm1, %xmm2
+vpslld (%rax), %xmm1, %xmm2
+
+vpslldq $1, %xmm1, %xmm2
+
+vpsllq $1, %xmm0, %xmm2
+vpsllq %xmm0, %xmm1, %xmm2
+vpsllq (%rax), %xmm1, %xmm2
+
+vpsllw $1, %xmm0, %xmm2
+vpsllw %xmm0, %xmm1, %xmm2
+vpsllw (%rax), %xmm1, %xmm2
+
+vpsrad $1, %xmm0, %xmm2
+vpsrad %xmm0, %xmm1, %xmm2
+vpsrad (%rax), %xmm1, %xmm2
+
+vpsraw $1, %xmm0, %xmm2
+vpsraw %xmm0, %xmm1, %xmm2
+vpsraw (%rax), %xmm1, %xmm2
+
+vpsrld $1, %xmm0, %xmm2
+vpsrld %xmm0, %xmm1, %xmm2
+vpsrld (%rax), %xmm1, %xmm2
+
+vpsrldq $1, %xmm1, %xmm2
+
+vpsrlq $1, %xmm0, %xmm2
+vpsrlq %xmm0, %xmm1, %xmm2
+vpsrlq (%rax), %xmm1, %xmm2
+
+vpsrlw $1, %xmm0, %xmm2
+vpsrlw %xmm0, %xmm1, %xmm2
+vpsrlw (%rax), %xmm1, %xmm2
+
+vpsubb %xmm0, %xmm1, %xmm2
+vpsubb (%rax), %xmm1, %xmm2
+
+vpsubd %xmm0, %xmm1, %xmm2
+vpsubd (%rax), %xmm1, %xmm2
+
+vpsubq %xmm0, %xmm1, %xmm2
+vpsubq (%rax), %xmm1, %xmm2
+
+vpsubsb %xmm0, %xmm1, %xmm2
+vpsubsb (%rax), %xmm1, %xmm2
+
+vpsubsw %xmm0, %xmm1, %xmm2
+vpsubsw (%rax), %xmm1, %xmm2
+
+vpsubusb %xmm0, %xmm1, %xmm2
+vpsubusb (%rax), %xmm1, %xmm2
+
+vpsubusw %xmm0, %xmm1, %xmm2
+vpsubusw (%rax), %xmm1, %xmm2
+
+vpsubw %xmm0, %xmm1, %xmm2
+vpsubw (%rax), %xmm1, %xmm2
+
+vptest %xmm0, %xmm1
+vptest (%rax), %xmm1
+
+vptest %ymm0, %ymm1
+vptest (%rax), %ymm1
+
+vpunpckhbw %xmm0, %xmm1, %xmm2
+vpunpckhbw (%rax), %xmm1, %xmm2
+
+vpunpckhdq %xmm0, %xmm1, %xmm2
+vpunpckhdq (%rax), %xmm1, %xmm2
+
+vpunpckhqdq %xmm0, %xmm1, %xmm2
+vpunpckhqdq (%rax), %xmm1, %xmm2
+
+vpunpckhwd %xmm0, %xmm1, %xmm2
+vpunpckhwd (%rax), %xmm1, %xmm2
+
+vpunpcklbw %xmm0, %xmm1, %xmm2
+vpunpcklbw (%rax), %xmm1, %xmm2
+
+vpunpckldq %xmm0, %xmm1, %xmm2
+vpunpckldq (%rax), %xmm1, %xmm2
+
+vpunpcklqdq %xmm0, %xmm1, %xmm2
+vpunpcklqdq (%rax), %xmm1, %xmm2
+
+vpunpcklwd %xmm0, %xmm1, %xmm2
+vpunpcklwd (%rax), %xmm1, %xmm2
+
+vpxor %xmm0, %xmm1, %xmm2
+vpxor (%rax), %xmm1, %xmm2
+
+vrcpps %xmm0, %xmm2
+vrcpps (%rax), %xmm2
+
+vrcpps %ymm0, %ymm2
+vrcpps (%rax), %ymm2
+
+vrcpss %xmm0, %xmm1, %xmm2
+vrcpss (%rax), %xmm1, %xmm2
+
+vroundpd $1, %xmm0, %xmm2
+vroundpd $1, (%rax), %xmm2
+
+vroundpd $1, %ymm0, %ymm2
+vroundpd $1, (%rax), %ymm2
+
+vroundps $1, %xmm0, %xmm2
+vroundps $1, (%rax), %xmm2
+
+vroundps $1, %ymm0, %ymm2
+vroundps $1, (%rax), %ymm2
+
+vroundsd $1, %xmm0, %xmm1, %xmm2
+vroundsd $1, (%rax), %xmm1, %xmm2
+
+vroundss $1, %xmm0, %xmm1, %xmm2
+vroundss $1, (%rax), %xmm1, %xmm2
+
+vrsqrtps %xmm0, %xmm2
+vrsqrtps (%rax), %xmm2
+
+vrsqrtps %ymm0, %ymm2
+vrsqrtps (%rax), %ymm2
+
+vrsqrtss %xmm0, %xmm1, %xmm2
+vrsqrtss (%rax), %xmm1, %xmm2
+
+vshufpd $1, %xmm0, %xmm1, %xmm2
+vshufpd $1, (%rax), %xmm1, %xmm2
+
+vshufpd $1, %ymm0, %ymm1, %ymm2
+vshufpd $1, (%rax), %ymm1, %ymm2
+
+vshufps $1, %xmm0, %xmm1, %xmm2
+vshufps $1, (%rax), %xmm1, %xmm2
+
+vshufps $1, %ymm0, %ymm1, %ymm2
+vshufps $1, (%rax), %ymm1, %ymm2
+
+vsqrtpd %xmm0, %xmm2
+vsqrtpd (%rax), %xmm2
+
+vsqrtpd %ymm0, %ymm2
+vsqrtpd (%rax), %ymm2
+
+vsqrtps %xmm0, %xmm2
+vsqrtps (%rax), %xmm2
+
+vsqrtps %ymm0, %ymm2
+vsqrtps (%rax), %ymm2
+
+vsqrtsd %xmm0, %xmm1, %xmm2
+vsqrtsd (%rax), %xmm1, %xmm2
+
+vsqrtss %xmm0, %xmm1, %xmm2
+vsqrtss (%rax), %xmm1, %xmm2
+
+vstmxcsr (%rax)
+
+vsubpd %xmm0, %xmm1, %xmm2
+vsubpd (%rax), %xmm1, %xmm2
+
+vsubpd %ymm0, %ymm1, %ymm2
+vsubpd (%rax), %ymm1, %ymm2
+
+vsubps %xmm0, %xmm1, %xmm2
+vsubps (%rax), %xmm1, %xmm2
+
+vsubps %ymm0, %ymm1, %ymm2
+vsubps (%rax), %ymm1, %ymm2
+
+vsubsd %xmm0, %xmm1, %xmm2
+vsubsd (%rax), %xmm1, %xmm2
+
+vsubss %xmm0, %xmm1, %xmm2
+vsubss (%rax), %xmm1, %xmm2
+
+vtestpd %xmm0, %xmm1
+vtestpd (%rax), %xmm1
+
+vtestpd %ymm0, %ymm1
+vtestpd (%rax), %ymm1
+
+vtestps %xmm0, %xmm1
+vtestps (%rax), %xmm1
+
+vtestps %ymm0, %ymm1
+vtestps (%rax), %ymm1
+
+vucomisd %xmm0, %xmm1
+vucomisd (%rax), %xmm1
+
+vucomiss %xmm0, %xmm1
+vucomiss (%rax), %xmm1
+
+vunpckhpd %xmm0, %xmm1, %xmm2
+vunpckhpd (%rax), %xmm1, %xmm2
+
+vunpckhpd %ymm0, %ymm1, %ymm2
+vunpckhpd (%rax), %ymm1, %ymm2
+
+vunpckhps %xmm0, %xmm1, %xmm2
+vunpckhps (%rax), %xmm1, %xmm2
+
+vunpckhps %ymm0, %ymm1, %ymm2
+vunpckhps (%rax), %ymm1, %ymm2
+
+vunpcklpd %xmm0, %xmm1, %xmm2
+vunpcklpd (%rax), %xmm1, %xmm2
+
+vunpcklpd %ymm0, %ymm1, %ymm2
+vunpcklpd (%rax), %ymm1, %ymm2
+
+vunpcklps %xmm0, %xmm1, %xmm2
+vunpcklps (%rax), %xmm1, %xmm2
+
+vunpcklps %ymm0, %ymm1, %ymm2
+vunpcklps (%rax), %ymm1, %ymm2
+
+vxorpd %xmm0, %xmm1, %xmm2
+vxorpd (%rax), %xmm1, %xmm2
+
+vxorpd %ymm0, %ymm1, %ymm2
+vxorpd (%rax), %ymm1, %ymm2
+
+vxorps %xmm0, %xmm1, %xmm2
+vxorps (%rax), %xmm1, %xmm2
+
+vxorps %ymm0, %ymm1, %ymm2
+vxorps (%rax), %ymm1, %ymm2
+
+vzeroall
+vzeroupper
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 vaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vaddsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vaddsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.33 vaddss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vaddss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vaddsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vaddsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vaddsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vaddsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vaddsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 2.00 vaesdec %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 2.33 * vaesdec (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 2.00 vaesdeclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 2.33 * vaesdeclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 2.00 vaesenc %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 2.33 * vaesenc (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 2.00 vaesenclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 2.33 * vaesenclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandnpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vandnpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandnpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vandnpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vandnps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vandnps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandnps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vandnps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vandpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vandpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vandpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vandps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vandps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vandps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vblendpd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 7 2.00 * vblendpd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vblendpd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 8 2.33 * vblendpd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vblendps $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 7 2.00 * vblendps $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vblendps $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 8 2.33 * vblendps $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 3 1.00 vblendvpd %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vblendvpd %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 3 0.75 vblendvpd %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 10 0.75 * vblendvpd %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 3 1.00 vblendvps %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vblendvps %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 3 0.75 vblendvps %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 10 0.75 * vblendvps %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 7 2.33 * vbroadcastf128 (%rax), %ymm2
+# CHECK-NEXT: 1 7 2.33 * vbroadcastsd (%rax), %ymm2
+# CHECK-NEXT: 1 6 2.00 * vbroadcastss (%rax), %xmm2
+# CHECK-NEXT: 1 7 2.33 * vbroadcastss (%rax), %ymm2
+# CHECK-NEXT: 1 4 2.00 vcmpeqpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 2.00 * vcmpeqpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vcmpeqpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 2.33 * vcmpeqpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vcmpeqps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 2.00 * vcmpeqps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vcmpeqps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 2.33 * vcmpeqps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vcmpeqsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 2.00 * vcmpeqsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vcmpeqss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 2.00 * vcmpeqss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.50 vcomisd %xmm0, %xmm1
+# CHECK-NEXT: 2 9 2.00 * vcomisd (%rax), %xmm1
+# CHECK-NEXT: 1 3 1.50 vcomiss %xmm0, %xmm1
+# CHECK-NEXT: 2 9 2.00 * vcomiss (%rax), %xmm1
+# CHECK-NEXT: 2 5 0.50 vcvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vcvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: 2 7 2.00 vcvtdq2pd %xmm0, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vcvtdq2pd (%rax), %ymm2
+# CHECK-NEXT: 1 4 2.00 vcvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vcvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvtdq2ps %ymm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vcvtdq2ps (%rax), %ymm2
+# CHECK-NEXT: 2 5 0.50 vcvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 3 12 0.50 * vcvtpd2dqx (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 vcvtpd2dq %ymm0, %xmm2
+# CHECK-NEXT: 3 15 0.50 * vcvtpd2dqy (%rax), %xmm2
+# CHECK-NEXT: 2 5 0.50 vcvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: 3 12 0.50 * vcvtpd2psx (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 vcvtpd2ps %ymm0, %xmm2
+# CHECK-NEXT: 3 15 0.50 * vcvtpd2psy (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 vcvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vcvtps2dq (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 vcvtps2dq %ymm0, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vcvtps2dq (%rax), %ymm2
+# CHECK-NEXT: 2 5 2.00 vcvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vcvtps2pd (%rax), %xmm2
+# CHECK-NEXT: 2 7 2.00 vcvtps2pd %xmm0, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vcvtps2pd (%rax), %ymm2
+# CHECK-NEXT: 2 7 3.50 vcvtsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 7 3.50 vcvtsd2si %xmm0, %rcx
+# CHECK-NEXT: 3 11 3.50 * vcvtsd2si (%rax), %ecx
+# CHECK-NEXT: 3 11 3.50 * vcvtsd2si (%rax), %rcx
+# CHECK-NEXT: 2 5 0.50 vcvtsd2ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 3 11 2.00 * vcvtsd2ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 8 2.00 vcvtsi2sd %ecx, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 2.00 vcvtsi2sd %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vcvtsi2sdl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vcvtsi2sdq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 8 2.00 vcvtsi2ss %ecx, %xmm0, %xmm2
+# CHECK-NEXT: 3 9 2.00 vcvtsi2ss %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vcvtsi2ssl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 3 11 2.00 * vcvtsi2ssq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 5 2.00 vcvtss2sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vcvtss2sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 3.50 vcvtss2si %xmm0, %ecx
+# CHECK-NEXT: 3 8 3.50 vcvtss2si %xmm0, %rcx
+# CHECK-NEXT: 2 11 3.50 * vcvtss2si (%rax), %ecx
+# CHECK-NEXT: 2 11 3.50 * vcvtss2si (%rax), %rcx
+# CHECK-NEXT: 2 5 0.50 vcvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 3 12 0.50 * vcvttpd2dqx (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 vcvttpd2dq %ymm0, %xmm2
+# CHECK-NEXT: 3 15 0.50 * vcvttpd2dqy (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 vcvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vcvttps2dq (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 vcvttps2dq %ymm0, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vcvttps2dq (%rax), %ymm2
+# CHECK-NEXT: 2 7 3.50 vcvttsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 7 3.50 vcvttsd2si %xmm0, %rcx
+# CHECK-NEXT: 3 11 3.50 * vcvttsd2si (%rax), %ecx
+# CHECK-NEXT: 3 11 3.50 * vcvttsd2si (%rax), %rcx
+# CHECK-NEXT: 2 7 3.50 vcvttss2si %xmm0, %ecx
+# CHECK-NEXT: 3 8 3.50 vcvttss2si %xmm0, %rcx
+# CHECK-NEXT: 2 11 3.50 * vcvttss2si (%rax), %ecx
+# CHECK-NEXT: 2 11 3.50 * vcvttss2si (%rax), %rcx
+# CHECK-NEXT: 1 10 5.00 vdivpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 16 5.00 * vdivpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 10 5.00 vdivpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 17 5.00 * vdivpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 7 3.50 vdivps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 13 3.50 * vdivps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 7 3.50 vdivps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 14 3.50 * vdivps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 10 5.00 vdivsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 20 0.50 * vdivsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 7 3.50 vdivss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 13 3.50 * vdivss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 8 1.00 vdppd $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 13 1.00 * vdppd $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 5 11 1.50 vdpps $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 6 18 1.50 * vdpps $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 5 12 1.50 vdpps $22, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 6 19 1.50 * vdpps $22, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vextractf128 $1, %ymm0, %xmm2
+# CHECK-NEXT: 2 1 0.50 * vextractf128 $1, %ymm0, (%rax)
+# CHECK-NEXT: 2 4 0.50 vextractps $1, %xmm0, %ecx
+# CHECK-NEXT: 3 12 0.50 * vextractps $1, %xmm0, (%rax)
+# CHECK-NEXT: 3 5 0.67 vhaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 10 2.50 * vhaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 4 2.50 vhaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 11 2.50 * vhaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 5 0.67 vhaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 10 2.50 * vhaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 4 2.50 vhaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 11 2.50 * vhaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 5 0.67 vhsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 10 2.50 * vhsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 4 2.50 vhsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 11 2.50 * vhsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 5 0.67 vhsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 10 2.50 * vhsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 4 2.50 vhsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 11 2.50 * vhsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vinsertf128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 8 2.33 * vinsertf128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vinsertps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 7 2.00 * vinsertps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 6 0.33 * vlddqu (%rax), %xmm2
+# CHECK-NEXT: 1 7 0.33 * vlddqu (%rax), %ymm2
+# CHECK-NEXT: 3 7 0.50 * * U vldmxcsr (%rax)
+# CHECK-NEXT: 2 1 0.50 * * U vmaskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: 2 8 0.33 * vmaskmovpd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 9 0.33 * vmaskmovpd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 3 14 0.50 * * vmaskmovpd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 3 14 0.50 * * vmaskmovpd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 2 8 0.33 * vmaskmovps (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 9 0.33 * vmaskmovps (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 3 14 0.50 * * vmaskmovps %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 3 14 0.50 * * vmaskmovps %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 1 4 2.00 vmaxpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vmaxpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vmaxpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vmaxpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vmaxps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vmaxps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vmaxps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vmaxps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vmaxss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vmaxss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vminpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vminpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vminpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vminpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vminps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vminps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vminps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vminps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vminss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vminss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0 1 0.00 vmovapd %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovapd %xmm0, (%rax)
+# CHECK-NEXT: 1 7 2.00 * vmovapd (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 vmovapd %ymm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vmovapd %ymm0, (%rax)
+# CHECK-NEXT: 1 8 2.33 * vmovapd (%rax), %ymm2
+# CHECK-NEXT: 0 1 0.00 vmovaps %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovaps %xmm0, (%rax)
+# CHECK-NEXT: 1 7 2.00 * vmovaps (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 vmovaps %ymm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vmovaps %ymm0, (%rax)
+# CHECK-NEXT: 1 8 2.33 * vmovaps (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.33 vmovd %eax, %xmm2
+# CHECK-NEXT: 1 6 0.33 * vmovd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vmovd %xmm0, %ecx
+# CHECK-NEXT: 2 12 0.50 * vmovd %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.50 vmovddup %xmm0, %xmm2
+# CHECK-NEXT: 1 6 2.00 * vmovddup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovddup %ymm0, %ymm2
+# CHECK-NEXT: 1 7 2.33 * vmovddup (%rax), %ymm2
+# CHECK-NEXT: 2 1 0.50 vmovdqa %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovdqa %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * vmovdqa (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 vmovdqa %ymm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vmovdqa %ymm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovdqa (%rax), %ymm2
+# CHECK-NEXT: 2 1 0.50 vmovdqu %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovdqu %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * vmovdqu (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 vmovdqu %ymm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vmovdqu %ymm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovdqu (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vmovhlps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovlhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovhpd %xmm0, (%rax)
+# CHECK-NEXT: 2 8 0.50 * vmovhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovhps %xmm0, (%rax)
+# CHECK-NEXT: 2 8 0.50 * vmovhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovlpd %xmm0, (%rax)
+# CHECK-NEXT: 2 8 0.33 * vmovlpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovlps %xmm0, (%rax)
+# CHECK-NEXT: 2 8 0.33 * vmovlps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.50 vmovmskpd %xmm0, %ecx
+# CHECK-NEXT: 1 4 1.50 vmovmskpd %ymm0, %ecx
+# CHECK-NEXT: 1 3 1.50 vmovmskps %xmm0, %ecx
+# CHECK-NEXT: 1 4 1.50 vmovmskps %ymm0, %ecx
+# CHECK-NEXT: 2 521 0.50 * vmovntdq %xmm0, (%rax)
+# CHECK-NEXT: 2 507 0.50 * vmovntdq %ymm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovntdqa (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.33 * vmovntdqa (%rax), %ymm2
+# CHECK-NEXT: 2 473 0.50 * vmovntpd %xmm0, (%rax)
+# CHECK-NEXT: 2 542 0.50 * vmovntpd %ymm0, (%rax)
+# CHECK-NEXT: 2 470 0.50 * vmovntps %xmm0, (%rax)
+# CHECK-NEXT: 2 494 0.50 * vmovntps %ymm0, (%rax)
+# CHECK-NEXT: 1 1 0.25 vmovq %xmm0, %xmm2
+# CHECK-NEXT: 1 3 0.33 vmovq %rax, %xmm2
+# CHECK-NEXT: 1 6 0.33 * vmovq (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vmovq %xmm0, %rcx
+# CHECK-NEXT: 2 12 0.50 * vmovq %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.25 vmovsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovsd %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovshdup %xmm0, %xmm2
+# CHECK-NEXT: 1 6 2.00 * vmovshdup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovshdup %ymm0, %ymm2
+# CHECK-NEXT: 1 7 2.33 * vmovshdup (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vmovsldup %xmm0, %xmm2
+# CHECK-NEXT: 1 6 2.00 * vmovsldup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovsldup %ymm0, %ymm2
+# CHECK-NEXT: 1 7 2.33 * vmovsldup (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.25 vmovss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovss %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovss (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 vmovupd %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovupd %xmm0, (%rax)
+# CHECK-NEXT: 1 7 2.00 * vmovupd (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 vmovupd %ymm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vmovupd %ymm0, (%rax)
+# CHECK-NEXT: 1 8 2.33 * vmovupd (%rax), %ymm2
+# CHECK-NEXT: 0 1 0.00 vmovups %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovups %xmm0, (%rax)
+# CHECK-NEXT: 1 7 2.00 * vmovups (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 vmovups %ymm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vmovups %ymm0, (%rax)
+# CHECK-NEXT: 1 8 2.33 * vmovups (%rax), %ymm2
+# CHECK-NEXT: 2 4 1.00 vmpsadbw $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 3 11 1.00 * vmpsadbw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.50 vmulpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 2.00 * vmulpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.50 vmulpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 2.33 * vmulpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.50 vmulps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 2.00 * vmulps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.50 vmulps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 2.33 * vmulps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.50 vmulsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 2.00 * vmulsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.50 vmulss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 2.00 * vmulss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpabsb %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpabsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpabsd %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpabsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpabsw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpabsw (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 vpackssdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 2.00 * vpackssdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.50 vpacksswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 2.00 * vpacksswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.50 vpackusdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 2.00 * vpackusdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.50 vpackuswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 2.00 * vpackuswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpaddb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpaddq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpaddsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpaddsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpaddusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpaddusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpaddusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpaddusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vpalignr $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 7 2.00 * vpalignr $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpand %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpand (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpandn %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpandn (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpavgb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpavgb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpavgw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpavgw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 3 1.00 vpblendvb %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vpblendvb %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpblendw $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 7 2.00 * vpblendw $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpclmulqdq $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vpclmulqdq $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpcmpeqb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpcmpeqb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpcmpeqd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpcmpeqd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpcmpeqq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpcmpeqq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpcmpeqw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpcmpeqw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 8 16 3.00 vpcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 31 3.00 * vpcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: 9 16 3.00 vpcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 9 17 3.00 * vpcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpcmpgtb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpcmpgtb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpcmpgtd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpcmpgtd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.50 vpcmpgtq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 2.00 * vpcmpgtq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpcmpgtw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpcmpgtw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 11 3.00 vpcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: 4 31 3.00 * vpcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: 3 11 3.00 vpcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 4 15 3.00 * vpcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vperm2f128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vperm2f128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpermilpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 7 2.00 * vpermilpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpermilpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpermilpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpermilpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpermilpd $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpermilpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpermilpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpermilps $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 7 2.00 * vpermilps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpermilps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpermilps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpermilps $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpermilps $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpermilps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpermilps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 4 1.50 vpextrb $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 0.50 * vpextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 4 1.50 vpextrd $1, %xmm0, %ecx
+# CHECK-NEXT: 3 12 0.50 * vpextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 4 1.50 vpextrq $1, %xmm0, %rcx
+# CHECK-NEXT: 3 12 0.50 * vpextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 4 1.50 vpextrw $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 0.50 * vpextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: 3 2 1.00 vphaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vphaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 2 1.00 vphaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vphaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 2 1.00 vphaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vphaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vphminposuw %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vphminposuw (%rax), %xmm2
+# CHECK-NEXT: 3 2 1.00 vphsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vphsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 2 1.00 vphsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vphsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 2 1.00 vphsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vphsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 5 1.33 vpinsrb $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 2 7 2.00 * vpinsrb $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 5 1.33 vpinsrd $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 2 7 2.00 * vpinsrd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 5 1.33 vpinsrq $1, %rax, %xmm1, %xmm2
+# CHECK-NEXT: 2 7 2.00 * vpinsrq $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 5 1.33 vpinsrw $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 2 7 2.00 * vpinsrw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vpmaddubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vpmaddubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vpmaddwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vpmaddwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmaxsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpmaxsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmaxsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpmaxsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmaxub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpmaxub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmaxud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpmaxud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmaxuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpmaxuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpminsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpminsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpminsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpminsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpminub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpminub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpminud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpminud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpminuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpminuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.50 vpmovmskb %xmm0, %ecx
+# CHECK-NEXT: 1 1 0.50 vpmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovsxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovsxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovsxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovsxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovsxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovsxwq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovzxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovzxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovzxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovzxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovzxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovzxwq (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 vpmuldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 2.00 * vpmuldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vpmulhrsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vpmulhrsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vpmulhuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vpmulhuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vpmulhw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vpmulhw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 vpmulld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 3 18 0.50 * vpmulld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vpmullw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vpmullw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.50 vpmuludq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 2.00 * vpmuludq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpsadbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vpsadbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshufb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 7 2.00 * vpshufb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 7 2.00 * vpshufd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 7 2.00 * vpshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 7 2.00 * vpshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsignb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpsignb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsignd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpsignd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsignw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpsignw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpslld $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 2 0.50 vpslld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpslld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpslldq $1, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllq $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 2 0.50 vpsllq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsllq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllw $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 2 0.50 vpsllw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsllw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrad $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 2 0.50 vpsrad %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsrad (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsraw $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 2 0.50 vpsraw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsraw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrld $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 2 0.50 vpsrld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsrld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrldq $1, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlq $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 2 0.50 vpsrlq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsrlq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlw $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 2 0.50 vpsrlw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsrlw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpsubb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpsubq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsubsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpsubsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsubusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpsubusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsubusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpsubusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 4 0.50 vptest %xmm0, %xmm1
+# CHECK-NEXT: 3 10 2.00 * vptest (%rax), %xmm1
+# CHECK-NEXT: 2 100 1.50 vptest %ymm0, %ymm1
+# CHECK-NEXT: 3 11 2.00 * vptest (%rax), %ymm1
+# CHECK-NEXT: 1 1 0.50 vpunpckhbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpunpckhbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpunpckhdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpunpckhqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpunpckhwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpunpcklbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpunpckldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpunpcklqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpunpcklwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpxor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpxor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vrcpps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vrcpps (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 vrcpps %ymm0, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vrcpps (%rax), %ymm2
+# CHECK-NEXT: 1 4 2.00 vrcpss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vrcpss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 8 4.00 vroundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 14 4.00 * vroundpd $1, (%rax), %xmm2
+# CHECK-NEXT: 2 8 4.00 vroundpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 3 15 4.00 * vroundpd $1, (%rax), %ymm2
+# CHECK-NEXT: 2 8 4.00 vroundps $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 14 4.00 * vroundps $1, (%rax), %xmm2
+# CHECK-NEXT: 2 8 4.00 vroundps $1, %ymm0, %ymm2
+# CHECK-NEXT: 3 15 4.00 * vroundps $1, (%rax), %ymm2
+# CHECK-NEXT: 2 8 4.00 vroundsd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 3 14 4.00 * vroundsd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 8 4.00 vroundss $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 3 14 4.00 * vroundss $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vrsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vrsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 vrsqrtps %ymm0, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vrsqrtps (%rax), %ymm2
+# CHECK-NEXT: 1 4 2.00 vrsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vrsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vshufpd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 7 2.00 * vshufpd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vshufpd $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vshufpd $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vshufps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 7 2.00 * vshufps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vshufps $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vshufps $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 15 7.50 vsqrtpd %xmm0, %xmm2
+# CHECK-NEXT: 1 21 7.50 * vsqrtpd (%rax), %xmm2
+# CHECK-NEXT: 1 15 7.50 vsqrtpd %ymm0, %ymm2
+# CHECK-NEXT: 1 22 7.50 * vsqrtpd (%rax), %ymm2
+# CHECK-NEXT: 1 10 5.00 vsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1 16 5.00 * vsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 10 5.00 vsqrtps %ymm0, %ymm2
+# CHECK-NEXT: 1 17 5.00 * vsqrtps (%rax), %ymm2
+# CHECK-NEXT: 1 15 7.50 vsqrtsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 24 1.00 * vsqrtsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 10 5.00 vsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 16 5.00 * vsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 100 3.00 * U vstmxcsr (%rax)
+# CHECK-NEXT: 1 3 0.50 vsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vsubsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vsubsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.33 vsubss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vsubss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vtestpd %xmm0, %xmm1
+# CHECK-NEXT: 2 7 0.50 * vtestpd (%rax), %xmm1
+# CHECK-NEXT: 1 5 0.50 vtestpd %ymm0, %ymm1
+# CHECK-NEXT: 2 11 0.50 * vtestpd (%rax), %ymm1
+# CHECK-NEXT: 1 3 0.50 vtestps %xmm0, %xmm1
+# CHECK-NEXT: 2 7 0.50 * vtestps (%rax), %xmm1
+# CHECK-NEXT: 1 100 1.50 vtestps %ymm0, %ymm1
+# CHECK-NEXT: 2 11 0.50 * vtestps (%rax), %ymm1
+# CHECK-NEXT: 1 3 1.50 vucomisd %xmm0, %xmm1
+# CHECK-NEXT: 2 9 2.00 * vucomisd (%rax), %xmm1
+# CHECK-NEXT: 1 3 1.50 vucomiss %xmm0, %xmm1
+# CHECK-NEXT: 2 9 2.00 * vucomiss (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.50 vunpckhpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vunpckhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vunpckhpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vunpckhpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vunpckhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vunpckhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vunpckhps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vunpckhps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vunpcklpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vunpcklpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vunpcklpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vunpcklpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vunpcklps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vunpcklps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vunpcklps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vunpcklps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vxorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vxorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vxorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vxorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vxorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vxorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vxorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vxorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 10 16 1.67 U vzeroall
+# CHECK-NEXT: 0 0 0.00 U vzeroupper
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: 1.00 27.67 28.67 3.67 28.67 3.67 28.67 19.00 19.00 459.00 459.00 459.00 12.33 12.33 12.33 - 565.50 565.50 193.50 193.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vaddsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vaddsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - vaddss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vaddss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vaddsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vaddsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vaddsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vaddsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vaddsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vaddsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vaddsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vaddsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vaesdec %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vaesdec (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vaesdeclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vaesdeclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vaesenc %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vaesenc (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vaesenclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vaesenclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vandnpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vandnpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vandnpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vandnpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vandnps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vandnps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vandnps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vandnps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vandpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vandpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vandpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vandpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vandps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vandps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vandps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vandps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vblendpd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vblendpd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vblendpd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vblendpd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vblendps $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vblendps $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vblendps $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vblendps $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - - - - - - - - - - - - vblendvpd %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - 0.33 0.33 0.33 - - - - - - - - vblendvpd %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.75 0.75 0.75 0.75 vblendvpd %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.75 0.75 0.75 0.75 vblendvpd %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - - - - - - - - - - - - vblendvps %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - 0.33 0.33 0.33 - - - - - - - - vblendvps %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.75 0.75 0.75 0.75 vblendvps %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.75 0.75 0.75 0.75 vblendvps %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - - - vbroadcastf128 (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - - - vbroadcastsd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - vbroadcastss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - - - vbroadcastss (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vcmpeqpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vcmpeqpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vcmpeqpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vcmpeqpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vcmpeqps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vcmpeqps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vcmpeqps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vcmpeqps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vcmpeqsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vcmpeqsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vcmpeqss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vcmpeqss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vcomisd %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - vcomisd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vcomiss %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - vcomiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vcvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - vcvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 1.50 1.50 vcvtdq2pd %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vcvtdq2pd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vcvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vcvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vcvtdq2ps %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - vcvtdq2ps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vcvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 vcvtpd2dqx (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vcvtpd2dq %ymm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 vcvtpd2dqy (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vcvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 vcvtpd2psx (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vcvtpd2ps %ymm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 vcvtpd2psy (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vcvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vcvtps2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vcvtps2dq %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vcvtps2dq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 0.50 0.50 vcvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vcvtps2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 1.50 1.50 vcvtps2pd %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vcvtps2pd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 - - vcvtsd2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 - - vcvtsd2si %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - 1.33 1.33 1.33 - - - - 3.50 3.50 - - vcvtsd2si (%rax), %ecx
+# CHECK-NEXT: - - - - - - - - - 1.33 1.33 1.33 - - - - 3.50 3.50 - - vcvtsd2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vcvtsd2ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 0.50 0.50 vcvtsd2ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - 1.33 - 1.33 - 1.33 - - - - - - - - - 2.00 2.00 - - vcvtsi2sd %ecx, %xmm0, %xmm2
+# CHECK-NEXT: - - 1.33 - 1.33 - 1.33 - - - - - - - - - 2.00 2.00 - - vcvtsi2sd %rcx, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vcvtsi2sdl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vcvtsi2sdq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - 1.33 - 1.33 - 1.33 - - - - - - - - - 2.00 2.00 - - vcvtsi2ss %ecx, %xmm0, %xmm2
+# CHECK-NEXT: - - 1.33 - 1.33 - 1.33 - - - - - - - - - 2.00 2.00 0.50 0.50 vcvtsi2ss %rcx, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vcvtsi2ssl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 0.50 0.50 vcvtsi2ssq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 0.50 0.50 vcvtss2sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vcvtss2sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 - - vcvtss2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 0.50 0.50 vcvtss2si %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - 1.33 1.33 1.33 - - - - 3.50 3.50 - - vcvtss2si (%rax), %ecx
+# CHECK-NEXT: - - - - - - - - - 1.33 1.33 1.33 - - - - 3.50 3.50 - - vcvtss2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vcvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 vcvttpd2dqx (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vcvttpd2dq %ymm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 vcvttpd2dqy (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vcvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vcvttps2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vcvttps2dq %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vcvttps2dq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 - - vcvttsd2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 - - vcvttsd2si %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - 1.33 1.33 1.33 - - - - 3.50 3.50 - - vcvttsd2si (%rax), %ecx
+# CHECK-NEXT: - - - - - - - - - 1.33 1.33 1.33 - - - - 3.50 3.50 - - vcvttsd2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 - - vcvttss2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 0.50 0.50 vcvttss2si %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - 1.33 1.33 1.33 - - - - 3.50 3.50 - - vcvttss2si (%rax), %ecx
+# CHECK-NEXT: - - - - - - - - - 1.33 1.33 1.33 - - - - 3.50 3.50 - - vcvttss2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 5.00 5.00 - - vdivpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 5.00 5.00 - - vdivpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 5.00 5.00 - - vdivpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 5.00 5.00 - - vdivpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 - - vdivps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 3.50 3.50 - - vdivps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 - - vdivps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 3.50 3.50 - - vdivps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 5.00 5.00 - - vdivsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vdivsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 - - vdivss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 3.50 3.50 - - vdivss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 1.00 0.50 0.50 vdppd $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 1.00 0.50 0.50 vdppd $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 1.50 1.50 vdpps $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.50 1.50 1.50 1.50 vdpps $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 1.50 1.50 vdpps $22, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.50 1.50 1.50 1.50 vdpps $22, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vextractf128 $1, %ymm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vextractf128 $1, %ymm0, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - 0.50 0.50 vextractps $1, %xmm0, %ecx
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vextractps $1, %xmm0, (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - 0.50 0.50 vhaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 2.50 2.50 vhaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.50 2.50 vhaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 2.50 2.50 vhaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - 0.50 0.50 vhaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 2.50 2.50 vhaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.50 2.50 vhaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 2.50 2.50 vhaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - 0.50 0.50 vhsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 2.50 2.50 vhsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.50 2.50 vhsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 2.50 2.50 vhsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - 0.50 0.50 vhsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 2.50 2.50 vhsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.50 2.50 vhsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 2.50 2.50 vhsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vinsertf128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vinsertf128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vinsertps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 vinsertps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - vlddqu (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - vlddqu (%rax), %ymm2
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - vldmxcsr (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 0.33 0.33 0.33 - - - - - - - - vmaskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 vmaskmovpd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 vmaskmovpd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - 0.50 0.50 - - vmaskmovpd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - 0.50 0.50 - - vmaskmovpd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 vmaskmovps (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 vmaskmovps (%rax), %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - 0.50 0.50 - - vmaskmovps %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - 0.50 0.50 - - vmaskmovps %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vmaxpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vmaxpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vmaxpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vmaxpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vmaxps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vmaxps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vmaxps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vmaxps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vmaxss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vmaxss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vminpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vminpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vminpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vminpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vminps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vminps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vminps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vminps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vminss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vminss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - vmovapd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovapd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - vmovapd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - vmovapd %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovapd %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - - - vmovapd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - vmovaps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovaps %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - vmovaps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - vmovaps %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovaps %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - - - vmovaps (%rax), %ymm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - vmovd %eax, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - vmovd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vmovd %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vmovddup %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - vmovddup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vmovddup %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - - - vmovddup (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vmovdqa %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovdqa %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - vmovdqa (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - vmovdqa %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovdqa %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - vmovdqa (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vmovdqu %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovdqu %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - vmovdqu (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - vmovdqu %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovdqu %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - vmovdqu (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vmovhlps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vmovlhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovhpd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vmovhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovhps %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vmovhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovlpd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 vmovlpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovlps %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 vmovlps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vmovmskpd %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vmovmskpd %ymm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vmovmskps %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vmovmskps %ymm0, %ecx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovntdq %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovntdq %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - vmovntdqa (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - vmovntdqa (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovntpd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovntpd %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovntps %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovntps %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vmovq %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - vmovq %rax, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - vmovq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vmovq %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovq %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vmovsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovsd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - vmovsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vmovshdup %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - vmovshdup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vmovshdup %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - - - vmovshdup (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vmovsldup %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - vmovsldup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vmovsldup %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - - - vmovsldup (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vmovss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovss %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - vmovss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - vmovupd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovupd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - vmovupd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - vmovupd %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovupd %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - - - vmovupd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - vmovups %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovups %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - vmovups (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - vmovups %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vmovups %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - - - vmovups (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 1.00 vmpsadbw $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 1.00 1.00 vmpsadbw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vmulpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - vmulpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vmulpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 1.50 1.50 - - vmulpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vmulps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - vmulps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vmulps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 1.50 1.50 - - vmulps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vmulsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - vmulsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vmulss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - vmulss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpabsb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpabsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpabsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpabsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpabsw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpabsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.50 1.50 vpackssdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 1.50 1.50 vpackssdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.50 1.50 vpacksswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 1.50 1.50 vpacksswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.50 1.50 vpackusdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 1.50 1.50 vpackusdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.50 1.50 vpackuswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 1.50 1.50 vpackuswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpaddb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vpaddb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vpaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpaddq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vpaddq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpaddsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpaddsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpaddusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpaddusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpaddusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpaddusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vpaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - vpalignr $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 vpalignr $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpand %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vpand (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpandn %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vpandn (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpavgb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpavgb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpavgw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpavgw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - - - - - - - - - - - - vpblendvb %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - 0.33 0.33 0.33 - - - - - - - - vpblendvb %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpblendw $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 vpblendw $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpclmulqdq $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpclmulqdq $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpcmpeqb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpcmpeqb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpcmpeqd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpcmpeqd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpcmpeqq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpcmpeqq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpcmpeqw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpcmpeqw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 3.67 1.00 0.67 1.00 0.67 1.00 - - - - - - - - - - - - - vpcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: - 3.17 1.17 0.17 1.17 0.17 1.17 - - 0.33 0.33 0.33 - - - - - - - - vpcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: - 3.50 1.50 0.50 1.50 0.50 1.50 - - - - - - - - - - - - - vpcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: - 3.33 1.33 0.33 1.33 0.33 1.33 - - 0.33 0.33 0.33 - - - - - - - - vpcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpcmpgtb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpcmpgtb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpcmpgtd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpcmpgtd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.50 1.50 vpcmpgtq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 1.50 1.50 vpcmpgtq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpcmpgtw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpcmpgtw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 3.00 - - - - - - - - - - - - - - - - - - vpcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: - 3.00 - - - - - - - 0.33 0.33 0.33 - - - - - - - - vpcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: - 3.00 - - - - - - - - - - - - - - - - - - vpcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: - 3.00 - - - - - - - 0.33 0.33 0.33 - - - - - - - - vpcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vperm2f128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vperm2f128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpermilpd $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 vpermilpd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpermilpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpermilpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpermilpd $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpermilpd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpermilpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpermilpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpermilps $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 vpermilps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpermilps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpermilps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpermilps $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpermilps $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpermilps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpermilps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 0.50 0.50 vpextrb $1, %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - 0.50 0.50 vpextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 0.50 0.50 vpextrd $1, %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - 0.50 0.50 vpextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 0.50 0.50 vpextrq $1, %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - 0.50 0.50 vpextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 0.50 0.50 vpextrw $1, %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - 0.50 0.50 vpextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 1.25 1.25 vphaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 1.25 1.25 vphaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 1.00 1.00 vphaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 1.00 1.00 vphaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 1.25 1.25 vphaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 1.25 1.25 vphaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vphminposuw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - vphminposuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 1.25 1.25 vphsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 1.25 1.25 vphsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 1.00 1.00 vphsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 1.00 1.00 vphsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 1.25 1.25 vphsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 1.25 1.25 vphsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - 1.33 - 1.33 - 1.33 - - - - - - - - - - - 0.50 0.50 vpinsrb $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 vpinsrb $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - 1.33 - 1.33 - 1.33 - - - - - - - - - - - 0.50 0.50 vpinsrd $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 vpinsrd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - 1.33 - 1.33 - 1.33 - - - - - - - - - - - 0.50 0.50 vpinsrq $1, %rax, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 vpinsrq $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - 1.33 - 1.33 - 1.33 - - - - - - - - - - - 0.50 0.50 vpinsrw $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 vpinsrw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpmaddubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vpmaddubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpmaddwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vpmaddwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpmaxsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpmaxsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpmaxsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpmaxsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpmaxub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpmaxub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpmaxud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpmaxud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpmaxuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpmaxuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpminsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpminsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpminsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpminsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpminub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpminub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpminud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpminud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpminuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpminuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vpmovmskb %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpmovsxbd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpmovsxbq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpmovsxbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpmovsxdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpmovsxwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpmovsxwq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpmovzxbd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpmovzxbq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpmovzxbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpmovzxdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpmovzxwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpmovzxwq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vpmuldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - vpmuldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpmulhrsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vpmulhrsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpmulhuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vpmulhuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpmulhw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vpmulhw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpmulld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 vpmulld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpmullw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vpmullw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vpmuludq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - vpmuludq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vpor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpsadbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpsadbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpshufb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 vpshufb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 vpshufd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 vpshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 vpshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsignb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpsignb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsignd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpsignd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsignw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpsignw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpslld $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpslld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - vpslld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpslldq $1, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsllq $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpsllq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - vpsllq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsllw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpsllw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - vpsllw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsrad $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpsrad %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - vpsrad (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsraw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpsraw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - vpsraw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsrld $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpsrld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - vpsrld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpsrldq $1, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsrlq $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpsrlq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - vpsrlq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsrlw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpsrlw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - vpsrlw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpsubb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vpsubb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vpsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpsubq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vpsubq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsubsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpsubsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsubusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpsubusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsubusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpsubusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vpsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vptest %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 0.50 0.50 vptest (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 0.50 0.50 vptest %ymm0, %ymm1
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 0.50 0.50 vptest (%rax), %ymm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpunpckhbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpunpckhbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpunpckhdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpunpckhdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpunpckhqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpunpckhqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpunpckhwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpunpckhwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpunpcklbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpunpcklbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpunpckldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpunpckldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpunpcklqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpunpcklqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpunpcklwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpunpcklwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpxor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vpxor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vrcpps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vrcpps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vrcpps %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vrcpps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vrcpss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vrcpss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 4.00 - - vroundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 4.00 4.00 - - vroundpd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 4.00 - - vroundpd $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 4.00 4.00 - - vroundpd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 4.00 - - vroundps $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 4.00 4.00 - - vroundps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 4.00 - - vroundps $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 4.00 4.00 - - vroundps $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 4.00 - - vroundsd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 4.00 4.00 - - vroundsd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 4.00 - - vroundss $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 4.00 4.00 - - vroundss $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vrsqrtps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vrsqrtps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vrsqrtps %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vrsqrtps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vrsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vrsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vshufpd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 vshufpd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vshufpd $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vshufpd $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vshufps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 vshufps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vshufps $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vshufps $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 7.50 7.50 - - vsqrtpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 7.50 7.50 - - vsqrtpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 7.50 7.50 - - vsqrtpd %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 7.50 7.50 - - vsqrtpd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 5.00 5.00 - - vsqrtps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 5.00 5.00 - - vsqrtps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 5.00 5.00 - - vsqrtps %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 5.00 5.00 - - vsqrtps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 7.50 7.50 - - vsqrtsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - 0.33 0.33 0.33 - - - - - - - - vsqrtsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 5.00 5.00 - - vsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 5.00 5.00 - - vsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - 0.50 0.50 - - - 0.33 0.33 0.33 - 3.00 3.00 - - vstmxcsr (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vsubsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vsubsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - vsubss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vsubss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vtestpd %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - vtestpd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vtestpd %ymm0, %ymm1
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - vtestpd (%rax), %ymm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vtestps %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - vtestps (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vtestps %ymm0, %ymm1
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - vtestps (%rax), %ymm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vucomisd %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - vucomisd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vucomiss %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - vucomiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vunpckhpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vunpckhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vunpckhpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 0.50 0.50 vunpckhpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vunpckhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vunpckhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vunpckhps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 0.50 0.50 vunpckhps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vunpcklpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vunpcklpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vunpcklpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 0.50 0.50 vunpcklpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vunpcklps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vunpcklps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vunpcklps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 0.50 0.50 vunpcklps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vxorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vxorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vxorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vxorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vxorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vxorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vxorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vxorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 1.33 2.00 1.33 2.00 1.33 2.00 - - - - - - - - - - - - - vzeroall
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - vzeroupper
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avx2.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avx2.s
new file mode 100644
index 0000000000000..38d2e0414f118
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avx2.s
@@ -0,0 +1,1093 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+vbroadcasti128 (%rax), %ymm0
+
+vbroadcastsd %xmm0, %ymm0
+vbroadcastss %xmm0, %ymm0
+
+vextracti128 $1, %ymm0, %xmm2
+vextracti128 $1, %ymm0, (%rax)
+
+vgatherdpd %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherdpd %ymm0, (%rax,%xmm1,2), %ymm2
+
+vgatherdps %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherdps %ymm0, (%rax,%ymm1,2), %ymm2
+
+vgatherqpd %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherqpd %ymm0, (%rax,%ymm1,2), %ymm2
+
+vgatherqps %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherqps %xmm0, (%rax,%ymm1,2), %xmm2
+
+vinserti128 $1, %xmm0, %ymm1, %ymm2
+vinserti128 $1, (%rax), %ymm1, %ymm2
+
+vmovntdqa (%rax), %ymm0
+
+vmpsadbw $1, %ymm0, %ymm1, %ymm2
+vmpsadbw $1, (%rax), %ymm1, %ymm2
+
+vpabsb %ymm0, %ymm2
+vpabsb (%rax), %ymm2
+
+vpabsd %ymm0, %ymm2
+vpabsd (%rax), %ymm2
+
+vpabsw %ymm0, %ymm2
+vpabsw (%rax), %ymm2
+
+vpackssdw %ymm0, %ymm1, %ymm2
+vpackssdw (%rax), %ymm1, %ymm2
+
+vpacksswb %ymm0, %ymm1, %ymm2
+vpacksswb (%rax), %ymm1, %ymm2
+
+vpackusdw %ymm0, %ymm1, %ymm2
+vpackusdw (%rax), %ymm1, %ymm2
+
+vpackuswb %ymm0, %ymm1, %ymm2
+vpackuswb (%rax), %ymm1, %ymm2
+
+vpaddb %ymm0, %ymm1, %ymm2
+vpaddb (%rax), %ymm1, %ymm2
+
+vpaddd %ymm0, %ymm1, %ymm2
+vpaddd (%rax), %ymm1, %ymm2
+
+vpaddq %ymm0, %ymm1, %ymm2
+vpaddq (%rax), %ymm1, %ymm2
+
+vpaddsb %ymm0, %ymm1, %ymm2
+vpaddsb (%rax), %ymm1, %ymm2
+
+vpaddsw %ymm0, %ymm1, %ymm2
+vpaddsw (%rax), %ymm1, %ymm2
+
+vpaddusb %ymm0, %ymm1, %ymm2
+vpaddusb (%rax), %ymm1, %ymm2
+
+vpaddusw %ymm0, %ymm1, %ymm2
+vpaddusw (%rax), %ymm1, %ymm2
+
+vpaddw %ymm0, %ymm1, %ymm2
+vpaddw (%rax), %ymm1, %ymm2
+
+vpalignr $1, %ymm0, %ymm1, %ymm2
+vpalignr $1, (%rax), %ymm1, %ymm2
+
+vpand %ymm0, %ymm1, %ymm2
+vpand (%rax), %ymm1, %ymm2
+
+vpandn %ymm0, %ymm1, %ymm2
+vpandn (%rax), %ymm1, %ymm2
+
+vpavgb %ymm0, %ymm1, %ymm2
+vpavgb (%rax), %ymm1, %ymm2
+
+vpavgw %ymm0, %ymm1, %ymm2
+vpavgw (%rax), %ymm1, %ymm2
+
+vpblendd $11, %xmm0, %xmm1, %xmm2
+vpblendd $11, (%rax), %xmm1, %xmm2
+
+vpblendd $11, %ymm0, %ymm1, %ymm2
+vpblendd $11, (%rax), %ymm1, %ymm2
+
+vpblendvb %ymm3, %ymm0, %ymm1, %ymm2
+vpblendvb %ymm3, (%rax), %ymm1, %ymm2
+
+vpblendw $11, %ymm0, %ymm1, %ymm2
+vpblendw $11, (%rax), %ymm1, %ymm2
+
+vpbroadcastb %xmm0, %xmm0
+vpbroadcastb (%rax), %xmm0
+
+vpbroadcastb %xmm0, %ymm0
+vpbroadcastb (%rax), %ymm0
+
+vpbroadcastd %xmm0, %xmm0
+vpbroadcastd (%rax), %xmm0
+
+vpbroadcastd %xmm0, %ymm0
+vpbroadcastd (%rax), %ymm0
+
+vpbroadcastq %xmm0, %xmm0
+vpbroadcastq (%rax), %xmm0
+
+vpbroadcastq %xmm0, %ymm0
+vpbroadcastq (%rax), %ymm0
+
+vpbroadcastw %xmm0, %xmm0
+vpbroadcastw (%rax), %xmm0
+
+vpbroadcastw %xmm0, %ymm0
+vpbroadcastw (%rax), %ymm0
+
+vpcmpeqb %ymm0, %ymm1, %ymm2
+vpcmpeqb (%rax), %ymm1, %ymm2
+
+vpcmpeqd %ymm0, %ymm1, %ymm2
+vpcmpeqd (%rax), %ymm1, %ymm2
+
+vpcmpeqq %ymm0, %ymm1, %ymm2
+vpcmpeqq (%rax), %ymm1, %ymm2
+
+vpcmpeqw %ymm0, %ymm1, %ymm2
+vpcmpeqw (%rax), %ymm1, %ymm2
+
+vpcmpgtb %ymm0, %ymm1, %ymm2
+vpcmpgtb (%rax), %ymm1, %ymm2
+
+vpcmpgtd %ymm0, %ymm1, %ymm2
+vpcmpgtd (%rax), %ymm1, %ymm2
+
+vpcmpgtq %ymm0, %ymm1, %ymm2
+vpcmpgtq (%rax), %ymm1, %ymm2
+
+vpcmpgtw %ymm0, %ymm1, %ymm2
+vpcmpgtw (%rax), %ymm1, %ymm2
+
+vperm2i128 $1, %ymm0, %ymm1, %ymm2
+vperm2i128 $1, (%rax), %ymm1, %ymm2
+
+vpermd %ymm0, %ymm1, %ymm2
+vpermd (%rax), %ymm1, %ymm2
+
+vpermpd $1, %ymm0, %ymm2
+vpermpd $1, (%rax), %ymm2
+
+vpermps %ymm0, %ymm1, %ymm2
+vpermps (%rax), %ymm1, %ymm2
+
+vpermq $1, %ymm0, %ymm2
+vpermq $1, (%rax), %ymm2
+
+vpgatherdd %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherdd %ymm0, (%rax,%ymm1,2), %ymm2
+
+vpgatherdq %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherdq %ymm0, (%rax,%xmm1,2), %ymm2
+
+vpgatherqd %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherqd %xmm0, (%rax,%ymm1,2), %xmm2
+
+vpgatherqq %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherqq %ymm0, (%rax,%ymm1,2), %ymm2
+
+vphaddd %ymm0, %ymm1, %ymm2
+vphaddd (%rax), %ymm1, %ymm2
+
+vphaddsw %ymm0, %ymm1, %ymm2
+vphaddsw (%rax), %ymm1, %ymm2
+
+vphaddw %ymm0, %ymm1, %ymm2
+vphaddw (%rax), %ymm1, %ymm2
+
+vphsubd %ymm0, %ymm1, %ymm2
+vphsubd (%rax), %ymm1, %ymm2
+
+vphsubsw %ymm0, %ymm1, %ymm2
+vphsubsw (%rax), %ymm1, %ymm2
+
+vphsubw %ymm0, %ymm1, %ymm2
+vphsubw (%rax), %ymm1, %ymm2
+
+vpmaddubsw %ymm0, %ymm1, %ymm2
+vpmaddubsw (%rax), %ymm1, %ymm2
+
+vpmaddwd %ymm0, %ymm1, %ymm2
+vpmaddwd (%rax), %ymm1, %ymm2
+
+vpmaskmovd (%rax), %xmm0, %xmm2
+vpmaskmovd (%rax), %ymm0, %ymm2
+
+vpmaskmovd %xmm0, %xmm1, (%rax)
+vpmaskmovd %ymm0, %ymm1, (%rax)
+
+vpmaskmovq (%rax), %xmm0, %xmm2
+vpmaskmovq (%rax), %ymm0, %ymm2
+
+vpmaskmovq %xmm0, %xmm1, (%rax)
+vpmaskmovq %ymm0, %ymm1, (%rax)
+
+vpmaxsb %ymm0, %ymm1, %ymm2
+vpmaxsb (%rax), %ymm1, %ymm2
+
+vpmaxsd %ymm0, %ymm1, %ymm2
+vpmaxsd (%rax), %ymm1, %ymm2
+
+vpmaxsw %ymm0, %ymm1, %ymm2
+vpmaxsw (%rax), %ymm1, %ymm2
+
+vpmaxub %ymm0, %ymm1, %ymm2
+vpmaxub (%rax), %ymm1, %ymm2
+
+vpmaxud %ymm0, %ymm1, %ymm2
+vpmaxud (%rax), %ymm1, %ymm2
+
+vpmaxuw %ymm0, %ymm1, %ymm2
+vpmaxuw (%rax), %ymm1, %ymm2
+
+vpminsb %ymm0, %ymm1, %ymm2
+vpminsb (%rax), %ymm1, %ymm2
+
+vpminsd %ymm0, %ymm1, %ymm2
+vpminsd (%rax), %ymm1, %ymm2
+
+vpminsw %ymm0, %ymm1, %ymm2
+vpminsw (%rax), %ymm1, %ymm2
+
+vpminub %ymm0, %ymm1, %ymm2
+vpminub (%rax), %ymm1, %ymm2
+
+vpminud %ymm0, %ymm1, %ymm2
+vpminud (%rax), %ymm1, %ymm2
+
+vpminuw %ymm0, %ymm1, %ymm2
+vpminuw (%rax), %ymm1, %ymm2
+
+vpmovmskb %ymm0, %rcx
+
+vpmovsxbd %xmm0, %ymm2
+vpmovsxbd (%rax), %ymm2
+
+vpmovsxbq %xmm0, %ymm2
+vpmovsxbq (%rax), %ymm2
+
+vpmovsxbw %xmm0, %ymm2
+vpmovsxbw (%rax), %ymm2
+
+vpmovsxdq %xmm0, %ymm2
+vpmovsxdq (%rax), %ymm2
+
+vpmovsxwd %xmm0, %ymm2
+vpmovsxwd (%rax), %ymm2
+
+vpmovsxwq %xmm0, %ymm2
+vpmovsxwq (%rax), %ymm2
+
+vpmovzxbd %xmm0, %ymm2
+vpmovzxbd (%rax), %ymm2
+
+vpmovzxbq %xmm0, %ymm2
+vpmovzxbq (%rax), %ymm2
+
+vpmovzxbw %xmm0, %ymm2
+vpmovzxbw (%rax), %ymm2
+
+vpmovzxdq %xmm0, %ymm2
+vpmovzxdq (%rax), %ymm2
+
+vpmovzxwd %xmm0, %ymm2
+vpmovzxwd (%rax), %ymm2
+
+vpmovzxwq %xmm0, %ymm2
+vpmovzxwq (%rax), %ymm2
+
+vpmuldq %ymm0, %ymm1, %ymm2
+vpmuldq (%rax), %ymm1, %ymm2
+
+vpmulhrsw %ymm0, %ymm1, %ymm2
+vpmulhrsw (%rax), %ymm1, %ymm2
+
+vpmulhuw %ymm0, %ymm1, %ymm2
+vpmulhuw (%rax), %ymm1, %ymm2
+
+vpmulhw %ymm0, %ymm1, %ymm2
+vpmulhw (%rax), %ymm1, %ymm2
+
+vpmulld %ymm0, %ymm1, %ymm2
+vpmulld (%rax), %ymm1, %ymm2
+
+vpmullw %ymm0, %ymm1, %ymm2
+vpmullw (%rax), %ymm1, %ymm2
+
+vpmuludq %ymm0, %ymm1, %ymm2
+vpmuludq (%rax), %ymm1, %ymm2
+
+vpor %ymm0, %ymm1, %ymm2
+vpor (%rax), %ymm1, %ymm2
+
+vpsadbw %ymm0, %ymm1, %ymm2
+vpsadbw (%rax), %ymm1, %ymm2
+
+vpshufb %ymm0, %ymm1, %ymm2
+vpshufb (%rax), %ymm1, %ymm2
+
+vpshufd $1, %ymm0, %ymm2
+vpshufd $1, (%rax), %ymm2
+
+vpshufhw $1, %ymm0, %ymm2
+vpshufhw $1, (%rax), %ymm2
+
+vpshuflw $1, %ymm0, %ymm2
+vpshuflw $1, (%rax), %ymm2
+
+vpsignb %ymm0, %ymm1, %ymm2
+vpsignb (%rax), %ymm1, %ymm2
+
+vpsignd %ymm0, %ymm1, %ymm2
+vpsignd (%rax), %ymm1, %ymm2
+
+vpsignw %ymm0, %ymm1, %ymm2
+vpsignw (%rax), %ymm1, %ymm2
+
+vpslld $1, %ymm0, %ymm2
+vpslld %xmm0, %ymm1, %ymm2
+vpslld (%rax), %ymm1, %ymm2
+
+vpslldq $1, %ymm1, %ymm2
+
+vpsllq $1, %ymm0, %ymm2
+vpsllq %xmm0, %ymm1, %ymm2
+vpsllq (%rax), %ymm1, %ymm2
+
+vpsllvd %xmm0, %xmm1, %xmm2
+vpsllvd (%rax), %xmm1, %xmm2
+
+vpsllvd %ymm0, %ymm1, %ymm2
+vpsllvd (%rax), %ymm1, %ymm2
+
+vpsllvq %xmm0, %xmm1, %xmm2
+vpsllvq (%rax), %xmm1, %xmm2
+
+vpsllvq %ymm0, %ymm1, %ymm2
+vpsllvq (%rax), %ymm1, %ymm2
+
+vpsllw $1, %ymm0, %ymm2
+vpsllw %xmm0, %ymm1, %ymm2
+vpsllw (%rax), %ymm1, %ymm2
+
+vpsrad $1, %ymm0, %ymm2
+vpsrad %xmm0, %ymm1, %ymm2
+vpsrad (%rax), %ymm1, %ymm2
+
+vpsravd %xmm0, %xmm1, %xmm2
+vpsravd (%rax), %xmm1, %xmm2
+
+vpsravd %ymm0, %ymm1, %ymm2
+vpsravd (%rax), %ymm1, %ymm2
+
+vpsraw $1, %ymm0, %ymm2
+vpsraw %xmm0, %ymm1, %ymm2
+vpsraw (%rax), %ymm1, %ymm2
+
+vpsrld $1, %ymm0, %ymm2
+vpsrld %xmm0, %ymm1, %ymm2
+vpsrld (%rax), %ymm1, %ymm2
+
+vpsrldq $1, %ymm1, %ymm2
+
+vpsrlq $1, %ymm0, %ymm2
+vpsrlq %xmm0, %ymm1, %ymm2
+vpsrlq (%rax), %ymm1, %ymm2
+
+vpsrlvd %xmm0, %xmm1, %xmm2
+vpsrlvd (%rax), %xmm1, %xmm2
+
+vpsrlvd %ymm0, %ymm1, %ymm2
+vpsrlvd (%rax), %ymm1, %ymm2
+
+vpsrlvq %xmm0, %xmm1, %xmm2
+vpsrlvq (%rax), %xmm1, %xmm2
+
+vpsrlvq %ymm0, %ymm1, %ymm2
+vpsrlvq (%rax), %ymm1, %ymm2
+
+vpsrlw $1, %ymm0, %ymm2
+vpsrlw %xmm0, %ymm1, %ymm2
+vpsrlw (%rax), %ymm1, %ymm2
+
+vpsubb %ymm0, %ymm1, %ymm2
+vpsubb (%rax), %ymm1, %ymm2
+
+vpsubd %ymm0, %ymm1, %ymm2
+vpsubd (%rax), %ymm1, %ymm2
+
+vpsubq %ymm0, %ymm1, %ymm2
+vpsubq (%rax), %ymm1, %ymm2
+
+vpsubsb %ymm0, %ymm1, %ymm2
+vpsubsb (%rax), %ymm1, %ymm2
+
+vpsubsw %ymm0, %ymm1, %ymm2
+vpsubsw (%rax), %ymm1, %ymm2
+
+vpsubusb %ymm0, %ymm1, %ymm2
+vpsubusb (%rax), %ymm1, %ymm2
+
+vpsubusw %ymm0, %ymm1, %ymm2
+vpsubusw (%rax), %ymm1, %ymm2
+
+vpsubw %ymm0, %ymm1, %ymm2
+vpsubw (%rax), %ymm1, %ymm2
+
+vpunpckhbw %ymm0, %ymm1, %ymm2
+vpunpckhbw (%rax), %ymm1, %ymm2
+
+vpunpckhdq %ymm0, %ymm1, %ymm2
+vpunpckhdq (%rax), %ymm1, %ymm2
+
+vpunpckhqdq %ymm0, %ymm1, %ymm2
+vpunpckhqdq (%rax), %ymm1, %ymm2
+
+vpunpckhwd %ymm0, %ymm1, %ymm2
+vpunpckhwd (%rax), %ymm1, %ymm2
+
+vpunpcklbw %ymm0, %ymm1, %ymm2
+vpunpcklbw (%rax), %ymm1, %ymm2
+
+vpunpckldq %ymm0, %ymm1, %ymm2
+vpunpckldq (%rax), %ymm1, %ymm2
+
+vpunpcklqdq %ymm0, %ymm1, %ymm2
+vpunpcklqdq (%rax), %ymm1, %ymm2
+
+vpunpcklwd %ymm0, %ymm1, %ymm2
+vpunpcklwd (%rax), %ymm1, %ymm2
+
+vpxor %ymm0, %ymm1, %ymm2
+vpxor (%rax), %ymm1, %ymm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 8 0.33 * vbroadcasti128 (%rax), %ymm0
+# CHECK-NEXT: 1 3 0.50 vbroadcastsd %xmm0, %ymm0
+# CHECK-NEXT: 1 3 0.50 vbroadcastss %xmm0, %ymm0
+# CHECK-NEXT: 1 3 0.50 vextracti128 $1, %ymm0, %xmm2
+# CHECK-NEXT: 2 1 0.50 * vextracti128 $1, %ymm0, (%rax)
+# CHECK-NEXT: 5 20 0.67 * vgatherdpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 8 29 1.33 * vgatherdpd %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 8 28 1.33 * vgatherdps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 12 30 2.67 * vgatherdps %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 5 20 0.67 * vgatherqpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 8 29 1.33 * vgatherqpd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 5 20 0.67 * vgatherqps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 8 29 1.33 * vgatherqps %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: 1 3 0.50 vinserti128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 8 2.33 * vinserti128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vmovntdqa (%rax), %ymm0
+# CHECK-NEXT: 2 4 1.00 vmpsadbw $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 3 12 1.00 * vmpsadbw $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpabsb %ymm0, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpabsb (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpabsd %ymm0, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpabsd (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpabsw %ymm0, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpabsw (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.50 vpackssdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 2.33 * vpackssdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.50 vpacksswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 2.33 * vpacksswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.50 vpackusdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 2.33 * vpackusdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.50 vpackuswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 2.33 * vpackuswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpaddb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpaddq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpaddsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpaddsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpaddusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpaddusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpaddusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpaddusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vpalignr $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 8 2.33 * vpalignr $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpand %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpand (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpandn %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpandn (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpavgb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpavgb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpavgw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpavgw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpblendd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpblendd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpblendd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 8 2.33 * vpblendd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 3 0.75 vpblendvb %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 9 2.33 * vpblendvb %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpblendw $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 8 2.33 * vpblendw $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vpbroadcastb %xmm0, %xmm0
+# CHECK-NEXT: 2 8 0.50 * vpbroadcastb (%rax), %xmm0
+# CHECK-NEXT: 1 3 0.50 vpbroadcastb %xmm0, %ymm0
+# CHECK-NEXT: 1 8 2.33 * vpbroadcastb (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.33 vpbroadcastd %xmm0, %xmm0
+# CHECK-NEXT: 1 6 2.00 * vpbroadcastd (%rax), %xmm0
+# CHECK-NEXT: 1 3 0.50 vpbroadcastd %xmm0, %ymm0
+# CHECK-NEXT: 1 7 2.33 * vpbroadcastd (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.33 vpbroadcastq %xmm0, %xmm0
+# CHECK-NEXT: 1 6 2.00 * vpbroadcastq (%rax), %xmm0
+# CHECK-NEXT: 1 3 0.50 vpbroadcastq %xmm0, %ymm0
+# CHECK-NEXT: 1 7 2.33 * vpbroadcastq (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.33 vpbroadcastw %xmm0, %xmm0
+# CHECK-NEXT: 1 6 2.00 * vpbroadcastw (%rax), %xmm0
+# CHECK-NEXT: 1 3 0.50 vpbroadcastw %xmm0, %ymm0
+# CHECK-NEXT: 1 7 2.33 * vpbroadcastw (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.50 vpcmpeqb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpcmpeqb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpcmpeqd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpcmpeqd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpcmpeqq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpcmpeqq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpcmpeqw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpcmpeqw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpcmpgtb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpcmpgtb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpcmpgtd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpcmpgtd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.50 vpcmpgtq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 2.33 * vpcmpgtq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpcmpgtw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpcmpgtw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vperm2i128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vperm2i128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpermd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 2.33 * vpermd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpermpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vpermpd $1, (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpermps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vpermps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpermq $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vpermq $1, (%rax), %ymm2
+# CHECK-NEXT: 8 28 1.33 * vpgatherdd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 12 30 2.67 * vpgatherdd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 5 20 0.67 * vpgatherdq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 8 29 1.33 * vpgatherdq %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 5 20 0.67 * vpgatherqd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 8 29 1.33 * vpgatherqd %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: 5 20 0.67 * vpgatherqq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 8 29 1.33 * vpgatherqq %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 3 2 1.00 vphaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 10 1.00 * vphaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 2 1.00 vphaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 9 2.33 * vphaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 2 1.00 vphaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 10 1.00 * vphaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 2 1.00 vphsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 10 1.00 * vphsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 2 1.00 vphsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 9 2.33 * vphsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 2 1.00 vphsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 10 1.00 * vphsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vpmaddubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vpmaddubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vpmaddwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vpmaddwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 7 2.00 * vpmaskmovd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 8 2.33 * vpmaskmovd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 3 14 0.50 * * vpmaskmovd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 3 14 0.50 * * vpmaskmovd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 2 7 2.00 * vpmaskmovq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 8 2.33 * vpmaskmovq (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 3 14 0.50 * * vpmaskmovq %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 3 14 0.50 * * vpmaskmovq %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 1 1 0.50 vpmaxsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpmaxsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpmaxsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpmaxsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpmaxsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpmaxsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpmaxub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpmaxub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpmaxud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpmaxud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpmaxuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpmaxuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpminsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpminsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpminsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpminsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpminsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpminsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpminub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpminub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpminud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpminud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpminuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpminuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.50 vpmovmskb %ymm0, %ecx
+# CHECK-NEXT: 1 3 0.50 vpmovsxbd %xmm0, %ymm2
+# CHECK-NEXT: 2 10 2.33 * vpmovsxbd (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovsxbq %xmm0, %ymm2
+# CHECK-NEXT: 2 10 2.33 * vpmovsxbq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovsxbw %xmm0, %ymm2
+# CHECK-NEXT: 2 10 2.33 * vpmovsxbw (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovsxdq %xmm0, %ymm2
+# CHECK-NEXT: 2 10 2.33 * vpmovsxdq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovsxwd %xmm0, %ymm2
+# CHECK-NEXT: 2 10 2.33 * vpmovsxwd (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovsxwq %xmm0, %ymm2
+# CHECK-NEXT: 2 10 2.33 * vpmovsxwq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxbd %xmm0, %ymm2
+# CHECK-NEXT: 2 10 2.33 * vpmovzxbd (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxbq %xmm0, %ymm2
+# CHECK-NEXT: 2 10 2.33 * vpmovzxbq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxbw %xmm0, %ymm2
+# CHECK-NEXT: 2 10 2.33 * vpmovzxbw (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxdq %xmm0, %ymm2
+# CHECK-NEXT: 2 10 2.33 * vpmovzxdq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxwd %xmm0, %ymm2
+# CHECK-NEXT: 2 10 2.33 * vpmovzxwd (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxwq %xmm0, %ymm2
+# CHECK-NEXT: 2 10 2.33 * vpmovzxwq (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.50 vpmuldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 2.33 * vpmuldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vpmulhrsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vpmulhrsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vpmulhuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vpmulhuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vpmulhw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vpmulhw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 10 0.50 vpmulld %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 3 18 0.50 * vpmulld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vpmullw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vpmullw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.50 vpmuludq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 2.33 * vpmuludq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpor (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpsadbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vpsadbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshufb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 8 2.33 * vpshufb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshufd $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 8 2.33 * vpshufd $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshufhw $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 8 2.33 * vpshufhw $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshuflw $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 8 2.33 * vpshuflw $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsignb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpsignb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsignd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpsignd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsignw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpsignw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpslld $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 4 0.50 vpslld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 2.33 * vpslld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpslldq $1, %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsllq $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 4 0.50 vpsllq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 2.33 * vpsllq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsllvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpsllvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpsllvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsllvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpsllvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpsllvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsllw $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 4 0.50 vpsllw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 2.33 * vpsllw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrad $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 4 0.50 vpsrad %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 2.33 * vpsrad (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsravd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpsravd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsravd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpsravd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsraw $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 4 0.50 vpsraw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 2.33 * vpsraw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrld $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 4 0.50 vpsrld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 2.33 * vpsrld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrldq $1, %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrlq $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 4 0.50 vpsrlq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 2.33 * vpsrlq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrlvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpsrlvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpsrlvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrlvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vpsrlvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpsrlvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrlw $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 4 0.50 vpsrlw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 2.33 * vpsrlw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpsubb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpsubq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsubsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpsubsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsubusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpsubusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsubusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpsubusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpunpckhbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpunpckhdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpunpckhqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpunpckhwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpunpcklbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpunpckldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpunpcklqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpunpcklwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpxor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vpxor (%rax), %ymm1, %ymm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - - 7.00 - 7.00 - 7.00 2.50 2.50 289.67 289.67 289.67 1.67 1.67 1.67 - 113.25 113.25 109.25 109.25
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - vbroadcasti128 (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vbroadcastsd %xmm0, %ymm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vbroadcastss %xmm0, %ymm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vextracti128 $1, %ymm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - vextracti128 $1, %ymm0, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.67 0.67 0.67 - - - - 0.50 0.50 0.50 0.50 vgatherdpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 1.33 1.33 1.33 - - - - 0.50 0.50 1.00 1.00 vgatherdpd %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 1.33 1.33 1.33 - - - - 0.50 0.50 1.00 1.00 vgatherdps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 2.67 2.67 2.67 - - - - 0.50 0.50 1.00 1.00 vgatherdps %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.67 0.67 0.67 - - - - 0.50 0.50 0.50 0.50 vgatherqpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 1.33 1.33 1.33 - - - - 0.50 0.50 1.00 1.00 vgatherqpd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.67 0.67 0.67 - - - - 0.50 0.50 0.50 0.50 vgatherqps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 1.33 1.33 1.33 - - - - 0.50 0.50 1.00 1.00 vgatherqps %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vinserti128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vinserti128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - vmovntdqa (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 1.00 vmpsadbw $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 1.00 1.00 vmpsadbw $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpabsb %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpabsb (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpabsd %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpabsd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpabsw %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpabsw (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.50 1.50 vpackssdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpackssdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.50 1.50 vpacksswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpacksswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.50 1.50 vpackusdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpackusdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.50 1.50 vpackuswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpackuswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpaddb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vpaddb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vpaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpaddq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vpaddq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpaddsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpaddsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpaddusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpaddusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpaddusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpaddusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vpaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - vpalignr $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 0.50 0.50 vpalignr $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpand %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vpand (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpandn %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vpandn (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpavgb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpavgb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpavgw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpavgw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpblendd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vpblendd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpblendd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vpblendd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.75 0.75 0.75 0.75 vpblendvb %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.75 0.75 0.75 0.75 vpblendvb %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpblendw $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 0.50 0.50 vpblendw $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - vpbroadcastb %xmm0, %xmm0
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpbroadcastb (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpbroadcastb %xmm0, %ymm0
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 0.50 0.50 vpbroadcastb (%rax), %ymm0
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - vpbroadcastd %xmm0, %xmm0
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - vpbroadcastd (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpbroadcastd %xmm0, %ymm0
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - - - vpbroadcastd (%rax), %ymm0
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - vpbroadcastq %xmm0, %xmm0
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - vpbroadcastq (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpbroadcastq %xmm0, %ymm0
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - - - vpbroadcastq (%rax), %ymm0
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - vpbroadcastw %xmm0, %xmm0
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - vpbroadcastw (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpbroadcastw %xmm0, %ymm0
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - - - vpbroadcastw (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpcmpeqb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpcmpeqb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpcmpeqd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpcmpeqd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpcmpeqq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpcmpeqq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpcmpeqw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpcmpeqw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpcmpgtb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpcmpgtb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpcmpgtd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpcmpgtd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.50 1.50 vpcmpgtq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpcmpgtq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpcmpgtw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpcmpgtw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vperm2i128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vperm2i128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpermd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpermd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpermpd $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpermpd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpermps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpermps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpermq $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpermq $1, (%rax), %ymm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 1.33 1.33 1.33 - - - - 0.50 0.50 1.00 1.00 vpgatherdd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 2.67 2.67 2.67 - - - - 0.50 0.50 1.00 1.00 vpgatherdd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.67 0.67 0.67 - - - - 0.50 0.50 0.50 0.50 vpgatherdq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 1.33 1.33 1.33 - - - - 0.50 0.50 1.00 1.00 vpgatherdq %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.67 0.67 0.67 - - - - 0.50 0.50 0.50 0.50 vpgatherqd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 1.33 1.33 1.33 - - - - 0.50 0.50 1.00 1.00 vpgatherqd %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.67 0.67 0.67 - - - - 0.50 0.50 0.50 0.50 vpgatherqq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 1.33 1.33 1.33 - - - - 0.50 0.50 1.00 1.00 vpgatherqq %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 1.25 1.25 vphaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 1.25 1.25 vphaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 1.00 1.00 vphaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 1.00 1.00 vphaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 1.25 1.25 vphaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 1.25 1.25 vphaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 1.25 1.25 vphsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 1.25 1.25 vphsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 1.00 1.00 vphsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 1.00 1.00 vphsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 1.25 1.25 vphsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 1.25 1.25 vphsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpmaddubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vpmaddubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpmaddwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vpmaddwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vpmaskmovd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vpmaskmovd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - 0.50 0.50 - - vpmaskmovd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - 0.50 0.50 - - vpmaskmovd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 vpmaskmovq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vpmaskmovq (%rax), %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - 0.50 0.50 - - vpmaskmovq %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - 0.50 0.50 - - vpmaskmovq %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpmaxsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpmaxsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpmaxsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpmaxsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpmaxsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpmaxsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpmaxub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpmaxub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpmaxud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpmaxud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpmaxuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpmaxuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpminsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpminsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpminsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpminsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpminsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpminsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpminub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpminub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpminud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpminud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpminuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpminuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vpmovmskb %ymm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovsxbd %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpmovsxbd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovsxbq %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpmovsxbq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovsxbw %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpmovsxbw (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovsxdq %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpmovsxdq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovsxwd %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpmovsxwd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovsxwq %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpmovsxwq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovzxbd %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpmovzxbd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovzxbq %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpmovzxbq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovzxbw %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpmovzxbw (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovzxdq %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpmovzxdq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovzxwd %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpmovzxwd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpmovzxwq %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpmovzxwq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vpmuldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 1.50 1.50 - - vpmuldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpmulhrsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vpmulhrsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpmulhuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vpmulhuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpmulhw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vpmulhw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpmulld %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 vpmulld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpmullw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vpmullw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - vpmuludq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 1.50 1.50 - - vpmuludq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vpor (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpsadbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpsadbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpshufb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 0.50 0.50 vpshufb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpshufd $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 0.50 0.50 vpshufd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpshufhw $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 0.50 0.50 vpshufhw $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpshuflw $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 0.50 0.50 vpshuflw $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsignb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsignb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsignd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsignd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsignw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsignw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpslld $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpslld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpslld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpslldq $1, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsllq $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpsllq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsllq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsllvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpsllvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsllvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsllvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsllvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpsllvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsllvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsllvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsllw $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpsllw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsllw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsrad $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpsrad %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsrad (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsravd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpsravd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsravd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsravd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsraw $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpsraw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsraw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsrld $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpsrld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsrld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpsrldq $1, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsrlq $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpsrlq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsrlq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsrlvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpsrlvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsrlvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsrlvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsrlvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vpsrlvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsrlvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsrlvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsrlw $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vpsrlw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsrlw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpsubb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vpsubb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vpsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpsubq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vpsubq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsubsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsubsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsubusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsubusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vpsubusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vpsubusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vpsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpunpckhbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpunpckhbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpunpckhdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpunpckhdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpunpckhqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpunpckhqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpunpckhwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpunpckhwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpunpcklbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpunpcklbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpunpckldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpunpckldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpunpcklqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpunpcklqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpunpcklwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 vpunpcklwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 vpxor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.25 0.25 0.25 0.25 vpxor (%rax), %ymm1, %ymm2
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avxgfni.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avxgfni.s
new file mode 100644
index 0000000000000..afebe2ac1e699
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avxgfni.s
@@ -0,0 +1,83 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+vgf2p8affineinvqb $0, %xmm0, %xmm1, %xmm2
+vgf2p8affineinvqb $0, (%rax), %xmm1, %xmm2
+
+vgf2p8affineinvqb $0, %ymm0, %ymm1, %ymm2
+vgf2p8affineinvqb $0, (%rax), %ymm1, %ymm2
+
+vgf2p8affineqb $0, %xmm0, %xmm1, %xmm2
+vgf2p8affineqb $0, (%rax), %xmm1, %xmm2
+
+vgf2p8affineqb $0, %ymm0, %ymm1, %ymm2
+vgf2p8affineqb $0, (%rax), %ymm1, %ymm2
+
+vgf2p8mulb %xmm0, %xmm1, %xmm2
+vgf2p8mulb (%rax), %xmm1, %xmm2
+
+vgf2p8mulb %ymm0, %ymm1, %ymm2
+vgf2p8mulb (%rax), %ymm1, %ymm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 2.00 vgf2p8affineinvqb $0, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vgf2p8affineinvqb $0, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vgf2p8affineinvqb $0, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vgf2p8affineinvqb $0, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vgf2p8affineqb $0, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vgf2p8affineqb $0, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vgf2p8affineqb $0, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vgf2p8affineqb $0, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vgf2p8mulb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 2.00 * vgf2p8mulb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vgf2p8mulb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.33 * vgf2p8mulb (%rax), %ymm1, %ymm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - - - - - - - - - 13.00 13.00 13.00 - - - - 18.00 18.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vgf2p8affineinvqb $0, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vgf2p8affineinvqb $0, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vgf2p8affineinvqb $0, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vgf2p8affineinvqb $0, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vgf2p8affineqb $0, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vgf2p8affineqb $0, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vgf2p8affineqb $0, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vgf2p8affineqb $0, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vgf2p8mulb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - vgf2p8mulb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - vgf2p8mulb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 0.50 0.50 - - vgf2p8mulb (%rax), %ymm1, %ymm2
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avxvnni.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avxvnni.s
new file mode 100644
index 0000000000000..631eee24721c9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avxvnni.s
@@ -0,0 +1,97 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+vpdpbusd %xmm0, %xmm1, %xmm2
+vpdpbusd (%rax), %xmm1, %xmm2
+
+vpdpbusd %ymm0, %ymm1, %ymm2
+vpdpbusd (%rax), %ymm1, %ymm2
+
+vpdpbusds %xmm0, %xmm1, %xmm2
+vpdpbusds (%rax), %xmm1, %xmm2
+
+vpdpbusds %ymm0, %ymm1, %ymm2
+vpdpbusds (%rax), %ymm1, %ymm2
+
+vpdpwssd %xmm0, %xmm1, %xmm2
+vpdpwssd (%rax), %xmm1, %xmm2
+
+vpdpwssd %ymm0, %ymm1, %ymm2
+vpdpwssd (%rax), %ymm1, %ymm2
+
+vpdpwssds %xmm0, %xmm1, %xmm2
+vpdpwssds (%rax), %xmm1, %xmm2
+
+vpdpwssds %ymm0, %ymm1, %ymm2
+vpdpwssds (%rax), %ymm1, %ymm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 2.00 vpdpbusd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vpdpbusd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vpdpbusd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vpdpbusd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vpdpbusds %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vpdpbusds (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vpdpbusds %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vpdpbusds (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vpdpwssd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vpdpwssd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vpdpwssd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vpdpwssd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vpdpwssds %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vpdpwssds (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vpdpwssds %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vpdpwssds (%rax), %ymm1, %ymm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - - - - - - - - - 17.33 17.33 17.33 - - - - 32.00 32.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpdpbusd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vpdpbusd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpdpbusd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vpdpbusd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpdpbusds %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vpdpbusds (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpdpbusds %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vpdpbusds (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpdpwssd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vpdpwssd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpdpwssd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vpdpwssd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpdpwssds %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vpdpwssds (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vpdpwssds %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vpdpwssds (%rax), %ymm1, %ymm2
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-bmi2.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-bmi2.s
new file mode 100644
index 0000000000000..f7356a819794c
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-bmi2.s
@@ -0,0 +1,153 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+bzhi %eax, %ebx, %ecx
+bzhi %eax, (%rbx), %ecx
+
+bzhi %rax, %rbx, %rcx
+bzhi %rax, (%rbx), %rcx
+
+mulx %eax, %ebx, %ecx
+mulx (%rax), %ebx, %ecx
+
+mulx %rax, %rbx, %rcx
+mulx (%rax), %rbx, %rcx
+
+pdep %eax, %ebx, %ecx
+pdep (%rax), %ebx, %ecx
+
+pdep %rax, %rbx, %rcx
+pdep (%rax), %rbx, %rcx
+
+pext %eax, %ebx, %ecx
+pext (%rax), %ebx, %ecx
+
+pext %rax, %rbx, %rcx
+pext (%rax), %rbx, %rcx
+
+rorx $1, %eax, %ecx
+rorx $1, (%rax), %ecx
+
+rorx $1, %rax, %rcx
+rorx $1, (%rax), %rcx
+
+sarx %eax, %ebx, %ecx
+sarx %eax, (%rbx), %ecx
+
+sarx %rax, %rbx, %rcx
+sarx %rax, (%rbx), %rcx
+
+shlx %eax, %ebx, %ecx
+shlx %eax, (%rbx), %ecx
+
+shlx %rax, %rbx, %rcx
+shlx %rax, (%rbx), %rcx
+
+shrx %eax, %ebx, %ecx
+shrx %eax, (%rbx), %ecx
+
+shrx %rax, %rbx, %rcx
+shrx %rax, (%rbx), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.33 bzhil %eax, %ebx, %ecx
+# CHECK-NEXT: 2 7 0.33 * bzhil %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 3 0.33 bzhiq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 7 0.33 * bzhiq %rax, (%rbx), %rcx
+# CHECK-NEXT: 3 4 0.67 mulxl %eax, %ebx, %ecx
+# CHECK-NEXT: 4 8 0.67 * mulxl (%rax), %ebx, %ecx
+# CHECK-NEXT: 2 4 0.67 mulxq %rax, %rbx, %rcx
+# CHECK-NEXT: 3 8 0.67 * mulxq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 3 1.00 pdepl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 7 1.33 * pdepl (%rax), %ebx, %ecx
+# CHECK-NEXT: 1 3 1.00 pdepq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 7 1.33 * pdepq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 3 1.00 pextl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 7 1.33 * pextl (%rax), %ebx, %ecx
+# CHECK-NEXT: 1 3 1.00 pextq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 7 1.33 * pextq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 1 0.33 rorxl $1, %eax, %ecx
+# CHECK-NEXT: 2 6 0.33 * rorxl $1, (%rax), %ecx
+# CHECK-NEXT: 1 1 0.33 rorxq $1, %rax, %rcx
+# CHECK-NEXT: 2 6 0.33 * rorxq $1, (%rax), %rcx
+# CHECK-NEXT: 1 3 0.33 sarxl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 8 0.33 * sarxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 3 0.33 sarxq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 8 0.33 * sarxq %rax, (%rbx), %rcx
+# CHECK-NEXT: 1 3 0.33 shlxl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 8 0.33 * shlxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 3 0.33 shlxq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 8 0.33 * shlxq %rax, (%rbx), %rcx
+# CHECK-NEXT: 1 3 0.33 shrxl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 8 0.33 * shrxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 3 0.33 shrxq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 8 0.33 * shrxq %rax, (%rbx), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - 5.00 13.00 5.00 13.00 5.00 13.00 - - 9.33 9.33 9.33 - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - bzhil %eax, %ebx, %ecx
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - bzhil %eax, (%rbx), %ecx
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - bzhiq %rax, %rbx, %rcx
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - bzhiq %rax, (%rbx), %rcx
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - mulxl %eax, %ebx, %ecx
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - 0.33 0.33 0.33 - - - - - - - - mulxl (%rax), %ebx, %ecx
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - mulxq %rax, %rbx, %rcx
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 0.33 0.33 0.33 - - - - - - - - mulxq (%rax), %rbx, %rcx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - - - - - - - - - - - - pdepl %eax, %ebx, %ecx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - 1.33 1.33 1.33 - - - - - - - - pdepl (%rax), %ebx, %ecx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - - - - - - - - - - - - pdepq %rax, %rbx, %rcx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - 1.33 1.33 1.33 - - - - - - - - pdepq (%rax), %rbx, %rcx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - - - - - - - - - - - - pextl %eax, %ebx, %ecx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - 1.33 1.33 1.33 - - - - - - - - pextl (%rax), %ebx, %ecx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - - - - - - - - - - - - pextq %rax, %rbx, %rcx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - 1.33 1.33 1.33 - - - - - - - - pextq (%rax), %rbx, %rcx
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - rorxl $1, %eax, %ecx
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - 0.33 0.33 0.33 - - - - - - - - rorxl $1, (%rax), %ecx
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - rorxq $1, %rax, %rcx
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - 0.33 0.33 0.33 - - - - - - - - rorxq $1, (%rax), %rcx
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sarxl %eax, %ebx, %ecx
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - 0.33 0.33 0.33 - - - - - - - - sarxl %eax, (%rbx), %ecx
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sarxq %rax, %rbx, %rcx
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - 0.33 0.33 0.33 - - - - - - - - sarxq %rax, (%rbx), %rcx
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - shlxl %eax, %ebx, %ecx
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - 0.33 0.33 0.33 - - - - - - - - shlxl %eax, (%rbx), %ecx
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - shlxq %rax, %rbx, %rcx
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - 0.33 0.33 0.33 - - - - - - - - shlxq %rax, (%rbx), %rcx
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - shrxl %eax, %ebx, %ecx
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - 0.33 0.33 0.33 - - - - - - - - shrxl %eax, (%rbx), %ecx
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - shrxq %rax, %rbx, %rcx
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - 0.33 0.33 0.33 - - - - - - - - shrxq %rax, (%rbx), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-clflushopt.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-clflushopt.s
new file mode 100644
index 0000000000000..d0a3c656ad71b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-clflushopt.s
@@ -0,0 +1,45 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+clflushopt (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 3 2 0.50 * * U clflushopt (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 - - - 0.33 0.33 0.33 - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - clflushopt (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-clwb.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-clwb.s
new file mode 100644
index 0000000000000..aad4836123712
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-clwb.s
@@ -0,0 +1,45 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+clwb (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 3 5 0.50 * * U clwb (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 - - - 0.33 0.33 0.33 - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - clwb (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-cmov.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-cmov.s
new file mode 100644
index 0000000000000..1b1be5de65f90
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-cmov.s
@@ -0,0 +1,335 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+cmovow %si, %di
+cmovnow %si, %di
+cmovbw %si, %di
+cmovaew %si, %di
+cmovew %si, %di
+cmovnew %si, %di
+cmovbew %si, %di
+cmovaw %si, %di
+cmovsw %si, %di
+cmovnsw %si, %di
+cmovpw %si, %di
+cmovnpw %si, %di
+cmovlw %si, %di
+cmovgew %si, %di
+cmovlew %si, %di
+cmovgw %si, %di
+
+cmovow (%rax), %di
+cmovnow (%rax), %di
+cmovbw (%rax), %di
+cmovaew (%rax), %di
+cmovew (%rax), %di
+cmovnew (%rax), %di
+cmovbew (%rax), %di
+cmovaw (%rax), %di
+cmovsw (%rax), %di
+cmovnsw (%rax), %di
+cmovpw (%rax), %di
+cmovnpw (%rax), %di
+cmovlw (%rax), %di
+cmovgew (%rax), %di
+cmovlew (%rax), %di
+cmovgw (%rax), %di
+
+cmovol %esi, %edi
+cmovnol %esi, %edi
+cmovbl %esi, %edi
+cmovael %esi, %edi
+cmovel %esi, %edi
+cmovnel %esi, %edi
+cmovbel %esi, %edi
+cmoval %esi, %edi
+cmovsl %esi, %edi
+cmovnsl %esi, %edi
+cmovpl %esi, %edi
+cmovnpl %esi, %edi
+cmovll %esi, %edi
+cmovgel %esi, %edi
+cmovlel %esi, %edi
+cmovgl %esi, %edi
+
+cmovol (%rax), %edi
+cmovnol (%rax), %edi
+cmovbl (%rax), %edi
+cmovael (%rax), %edi
+cmovel (%rax), %edi
+cmovnel (%rax), %edi
+cmovbel (%rax), %edi
+cmoval (%rax), %edi
+cmovsl (%rax), %edi
+cmovnsl (%rax), %edi
+cmovpl (%rax), %edi
+cmovnpl (%rax), %edi
+cmovll (%rax), %edi
+cmovgel (%rax), %edi
+cmovlel (%rax), %edi
+cmovgl (%rax), %edi
+
+cmovoq %rsi, %rdi
+cmovnoq %rsi, %rdi
+cmovbq %rsi, %rdi
+cmovaeq %rsi, %rdi
+cmoveq %rsi, %rdi
+cmovneq %rsi, %rdi
+cmovbeq %rsi, %rdi
+cmovaq %rsi, %rdi
+cmovsq %rsi, %rdi
+cmovnsq %rsi, %rdi
+cmovpq %rsi, %rdi
+cmovnpq %rsi, %rdi
+cmovlq %rsi, %rdi
+cmovgeq %rsi, %rdi
+cmovleq %rsi, %rdi
+cmovgq %rsi, %rdi
+
+cmovoq (%rax), %rdi
+cmovnoq (%rax), %rdi
+cmovbq (%rax), %rdi
+cmovaeq (%rax), %rdi
+cmoveq (%rax), %rdi
+cmovneq (%rax), %rdi
+cmovbeq (%rax), %rdi
+cmovaq (%rax), %rdi
+cmovsq (%rax), %rdi
+cmovnsq (%rax), %rdi
+cmovpq (%rax), %rdi
+cmovnpq (%rax), %rdi
+cmovlq (%rax), %rdi
+cmovgeq (%rax), %rdi
+cmovleq (%rax), %rdi
+cmovgq (%rax), %rdi
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.17 cmovow %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovnow %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovbw %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovaew %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovew %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovnew %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovbew %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovaw %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovsw %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovnsw %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovpw %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovnpw %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovlw %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovgew %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovlew %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovgw %si, %di
+# CHECK-NEXT: 1 5 1.33 * cmovow (%rax), %di
+# CHECK-NEXT: 1 5 1.33 * cmovnow (%rax), %di
+# CHECK-NEXT: 1 5 1.33 * cmovbw (%rax), %di
+# CHECK-NEXT: 1 5 1.33 * cmovaew (%rax), %di
+# CHECK-NEXT: 1 5 1.33 * cmovew (%rax), %di
+# CHECK-NEXT: 1 5 1.33 * cmovnew (%rax), %di
+# CHECK-NEXT: 1 5 1.33 * cmovbew (%rax), %di
+# CHECK-NEXT: 1 5 1.33 * cmovaw (%rax), %di
+# CHECK-NEXT: 1 5 1.33 * cmovsw (%rax), %di
+# CHECK-NEXT: 1 5 1.33 * cmovnsw (%rax), %di
+# CHECK-NEXT: 1 5 1.33 * cmovpw (%rax), %di
+# CHECK-NEXT: 1 5 1.33 * cmovnpw (%rax), %di
+# CHECK-NEXT: 1 5 1.33 * cmovlw (%rax), %di
+# CHECK-NEXT: 1 5 1.33 * cmovgew (%rax), %di
+# CHECK-NEXT: 1 5 1.33 * cmovlew (%rax), %di
+# CHECK-NEXT: 1 5 1.33 * cmovgw (%rax), %di
+# CHECK-NEXT: 1 1 0.17 cmovol %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovnol %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovbl %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovael %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovel %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovnel %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovbel %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmoval %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovsl %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovnsl %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovpl %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovnpl %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovll %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovgel %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovlel %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovgl %esi, %edi
+# CHECK-NEXT: 1 5 1.33 * cmovol (%rax), %edi
+# CHECK-NEXT: 1 5 1.33 * cmovnol (%rax), %edi
+# CHECK-NEXT: 1 5 1.33 * cmovbl (%rax), %edi
+# CHECK-NEXT: 1 5 1.33 * cmovael (%rax), %edi
+# CHECK-NEXT: 1 5 1.33 * cmovel (%rax), %edi
+# CHECK-NEXT: 1 5 1.33 * cmovnel (%rax), %edi
+# CHECK-NEXT: 1 5 1.33 * cmovbel (%rax), %edi
+# CHECK-NEXT: 1 5 1.33 * cmoval (%rax), %edi
+# CHECK-NEXT: 1 5 1.33 * cmovsl (%rax), %edi
+# CHECK-NEXT: 1 5 1.33 * cmovnsl (%rax), %edi
+# CHECK-NEXT: 1 5 1.33 * cmovpl (%rax), %edi
+# CHECK-NEXT: 1 5 1.33 * cmovnpl (%rax), %edi
+# CHECK-NEXT: 1 5 1.33 * cmovll (%rax), %edi
+# CHECK-NEXT: 1 5 1.33 * cmovgel (%rax), %edi
+# CHECK-NEXT: 1 5 1.33 * cmovlel (%rax), %edi
+# CHECK-NEXT: 1 5 1.33 * cmovgl (%rax), %edi
+# CHECK-NEXT: 1 1 0.17 cmovoq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovnoq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovbq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovaeq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmoveq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovneq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovbeq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovaq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovsq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovnsq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovpq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovnpq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovlq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovgeq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovleq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovgq %rsi, %rdi
+# CHECK-NEXT: 1 5 1.33 * cmovoq (%rax), %rdi
+# CHECK-NEXT: 1 5 1.33 * cmovnoq (%rax), %rdi
+# CHECK-NEXT: 1 5 1.33 * cmovbq (%rax), %rdi
+# CHECK-NEXT: 1 5 1.33 * cmovaeq (%rax), %rdi
+# CHECK-NEXT: 1 5 1.33 * cmoveq (%rax), %rdi
+# CHECK-NEXT: 1 5 1.33 * cmovneq (%rax), %rdi
+# CHECK-NEXT: 1 5 1.33 * cmovbeq (%rax), %rdi
+# CHECK-NEXT: 1 5 1.33 * cmovaq (%rax), %rdi
+# CHECK-NEXT: 1 5 1.33 * cmovsq (%rax), %rdi
+# CHECK-NEXT: 1 5 1.33 * cmovnsq (%rax), %rdi
+# CHECK-NEXT: 1 5 1.33 * cmovpq (%rax), %rdi
+# CHECK-NEXT: 1 5 1.33 * cmovnpq (%rax), %rdi
+# CHECK-NEXT: 1 5 1.33 * cmovlq (%rax), %rdi
+# CHECK-NEXT: 1 5 1.33 * cmovgeq (%rax), %rdi
+# CHECK-NEXT: 1 5 1.33 * cmovleq (%rax), %rdi
+# CHECK-NEXT: 1 5 1.33 * cmovgq (%rax), %rdi
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - 16.00 16.00 16.00 16.00 16.00 16.00 - - 64.00 64.00 64.00 - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovow %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovnow %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovbw %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovaew %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovew %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovnew %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovbew %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovaw %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovsw %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovnsw %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovpw %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovnpw %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovlw %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovgew %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovlew %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovgw %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovow (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovnow (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovbw (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovaew (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovew (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovnew (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovbew (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovaw (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovsw (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovnsw (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovpw (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovnpw (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovlw (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovgew (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovlew (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovgw (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovol %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovnol %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovbl %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovael %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovel %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovnel %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovbel %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmoval %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovsl %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovnsl %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovpl %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovnpl %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovll %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovgel %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovlel %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovgl %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovol (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovnol (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovbl (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovael (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovel (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovnel (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovbel (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmoval (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovsl (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovnsl (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovpl (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovnpl (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovll (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovgel (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovlel (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovgl (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovoq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovnoq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovbq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovaeq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmoveq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovneq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovbeq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovaq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovsq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovnsq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovpq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovnpq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovlq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovgeq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovleq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - cmovgq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovoq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovnoq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovbq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovaeq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmoveq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovneq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovbeq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovaq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovsq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovnsq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovpq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovnpq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovlq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovgeq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovleq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 1.33 1.33 1.33 - - - - - - - - cmovgq (%rax), %rdi
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-cmpxchg.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-cmpxchg.s
new file mode 100644
index 0000000000000..7805834a31728
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-cmpxchg.s
@@ -0,0 +1,54 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+cmpxchg8b (%rax)
+cmpxchg16b (%rax)
+lock cmpxchg8b (%rax)
+lock cmpxchg16b (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 16 25 2.33 * * cmpxchg8b (%rax)
+# CHECK-NEXT: 22 32 2.83 * * cmpxchg16b (%rax)
+# CHECK-NEXT: 16 25 2.33 * * lock cmpxchg8b (%rax)
+# CHECK-NEXT: 22 32 2.83 * * lock cmpxchg16b (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - 16.33 9.00 12.33 5.00 12.33 5.00 2.00 2.00 1.33 1.33 1.33 1.33 1.33 1.33 - - - 2.00 2.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - 3.00 2.67 3.00 0.67 3.00 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - cmpxchg8b (%rax)
+# CHECK-NEXT: - 5.17 1.83 3.17 1.83 3.17 1.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - 1.00 1.00 cmpxchg16b (%rax)
+# CHECK-NEXT: - 3.00 2.67 3.00 0.67 3.00 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock cmpxchg8b (%rax)
+# CHECK-NEXT: - 5.17 1.83 3.17 1.83 3.17 1.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - 1.00 1.00 lock cmpxchg16b (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-f16c.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-f16c.s
new file mode 100644
index 0000000000000..4c1bdeda11d7d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-f16c.s
@@ -0,0 +1,69 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+vcvtph2ps %xmm0, %xmm2
+vcvtph2ps (%rax), %xmm2
+
+vcvtph2ps %xmm0, %ymm2
+vcvtph2ps (%rax), %ymm2
+
+vcvtps2ph $0, %xmm0, %xmm2
+vcvtps2ph $0, %xmm0, (%rax)
+
+vcvtps2ph $0, %ymm0, %xmm2
+vcvtps2ph $0, %ymm0, (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 2 5 0.50 vcvtph2ps %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vcvtph2ps (%rax), %xmm2
+# CHECK-NEXT: 2 7 2.00 vcvtph2ps %xmm0, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vcvtph2ps (%rax), %ymm2
+# CHECK-NEXT: 2 5 2.00 vcvtps2ph $0, %xmm0, %xmm2
+# CHECK-NEXT: 2 5 2.00 * vcvtps2ph $0, %xmm0, (%rax)
+# CHECK-NEXT: 2 7 2.00 vcvtps2ph $0, %ymm0, %xmm2
+# CHECK-NEXT: 3 5 2.00 * vcvtps2ph $0, %ymm0, (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 2.67 2.67 2.67 0.67 0.67 0.67 - 13.00 13.00 4.00 4.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 vcvtph2ps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - vcvtph2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 1.50 1.50 vcvtph2ps %xmm0, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vcvtph2ps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 0.50 0.50 vcvtps2ph $0, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - 2.00 2.00 - - vcvtps2ph $0, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 1.50 1.50 vcvtps2ph $0, %ymm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - 2.00 2.00 - - vcvtps2ph $0, %ymm0, (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-fma.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-fma.s
new file mode 100644
index 0000000000000..587f83b80651d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-fma.s
@@ -0,0 +1,713 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+vfmadd132pd %xmm0, %xmm1, %xmm2
+vfmadd132pd (%rax), %xmm1, %xmm2
+
+vfmadd132pd %ymm0, %ymm1, %ymm2
+vfmadd132pd (%rax), %ymm1, %ymm2
+
+vfmadd213pd %xmm0, %xmm1, %xmm2
+vfmadd213pd (%rax), %xmm1, %xmm2
+
+vfmadd213pd %ymm0, %ymm1, %ymm2
+vfmadd213pd (%rax), %ymm1, %ymm2
+
+vfmadd231pd %xmm0, %xmm1, %xmm2
+vfmadd231pd (%rax), %xmm1, %xmm2
+
+vfmadd231pd %ymm0, %ymm1, %ymm2
+vfmadd231pd (%rax), %ymm1, %ymm2
+
+vfmadd132ps %xmm0, %xmm1, %xmm2
+vfmadd132ps (%rax), %xmm1, %xmm2
+
+vfmadd132ps %ymm0, %ymm1, %ymm2
+vfmadd132ps (%rax), %ymm1, %ymm2
+
+vfmadd213ps %xmm0, %xmm1, %xmm2
+vfmadd213ps (%rax), %xmm1, %xmm2
+
+vfmadd213ps %ymm0, %ymm1, %ymm2
+vfmadd213ps (%rax), %ymm1, %ymm2
+
+vfmadd231ps %xmm0, %xmm1, %xmm2
+vfmadd231ps (%rax), %xmm1, %xmm2
+
+vfmadd231ps %ymm0, %ymm1, %ymm2
+vfmadd231ps (%rax), %ymm1, %ymm2
+
+vfmadd132sd %xmm0, %xmm1, %xmm2
+vfmadd132sd (%rax), %xmm1, %xmm2
+
+vfmadd213sd %xmm0, %xmm1, %xmm2
+vfmadd213sd (%rax), %xmm1, %xmm2
+
+vfmadd231sd %xmm0, %xmm1, %xmm2
+vfmadd231sd (%rax), %xmm1, %xmm2
+
+vfmadd132ss %xmm0, %xmm1, %xmm2
+vfmadd132ss (%rax), %xmm1, %xmm2
+
+vfmadd213ss %xmm0, %xmm1, %xmm2
+vfmadd213ss (%rax), %xmm1, %xmm2
+
+vfmadd231ss %xmm0, %xmm1, %xmm2
+vfmadd231ss (%rax), %xmm1, %xmm2
+
+vfmaddsub132pd %xmm0, %xmm1, %xmm2
+vfmaddsub132pd (%rax), %xmm1, %xmm2
+
+vfmaddsub132pd %ymm0, %ymm1, %ymm2
+vfmaddsub132pd (%rax), %ymm1, %ymm2
+
+vfmaddsub213pd %xmm0, %xmm1, %xmm2
+vfmaddsub213pd (%rax), %xmm1, %xmm2
+
+vfmaddsub213pd %ymm0, %ymm1, %ymm2
+vfmaddsub213pd (%rax), %ymm1, %ymm2
+
+vfmaddsub231pd %xmm0, %xmm1, %xmm2
+vfmaddsub231pd (%rax), %xmm1, %xmm2
+
+vfmaddsub231pd %ymm0, %ymm1, %ymm2
+vfmaddsub231pd (%rax), %ymm1, %ymm2
+
+vfmaddsub132ps %xmm0, %xmm1, %xmm2
+vfmaddsub132ps (%rax), %xmm1, %xmm2
+
+vfmaddsub132ps %ymm0, %ymm1, %ymm2
+vfmaddsub132ps (%rax), %ymm1, %ymm2
+
+vfmaddsub213ps %xmm0, %xmm1, %xmm2
+vfmaddsub213ps (%rax), %xmm1, %xmm2
+
+vfmaddsub213ps %ymm0, %ymm1, %ymm2
+vfmaddsub213ps (%rax), %ymm1, %ymm2
+
+vfmaddsub231ps %xmm0, %xmm1, %xmm2
+vfmaddsub231ps (%rax), %xmm1, %xmm2
+
+vfmaddsub231ps %ymm0, %ymm1, %ymm2
+vfmaddsub231ps (%rax), %ymm1, %ymm2
+
+vfmsub132pd %xmm0, %xmm1, %xmm2
+vfmsub132pd (%rax), %xmm1, %xmm2
+
+vfmsub132pd %ymm0, %ymm1, %ymm2
+vfmsub132pd (%rax), %ymm1, %ymm2
+
+vfmsub213pd %xmm0, %xmm1, %xmm2
+vfmsub213pd (%rax), %xmm1, %xmm2
+
+vfmsub213pd %ymm0, %ymm1, %ymm2
+vfmsub213pd (%rax), %ymm1, %ymm2
+
+vfmsub231pd %xmm0, %xmm1, %xmm2
+vfmsub231pd (%rax), %xmm1, %xmm2
+
+vfmsub231pd %ymm0, %ymm1, %ymm2
+vfmsub231pd (%rax), %ymm1, %ymm2
+
+vfmsub132ps %xmm0, %xmm1, %xmm2
+vfmsub132ps (%rax), %xmm1, %xmm2
+
+vfmsub132ps %ymm0, %ymm1, %ymm2
+vfmsub132ps (%rax), %ymm1, %ymm2
+
+vfmsub213ps %xmm0, %xmm1, %xmm2
+vfmsub213ps (%rax), %xmm1, %xmm2
+
+vfmsub213ps %ymm0, %ymm1, %ymm2
+vfmsub213ps (%rax), %ymm1, %ymm2
+
+vfmsub231ps %xmm0, %xmm1, %xmm2
+vfmsub231ps (%rax), %xmm1, %xmm2
+
+vfmsub231ps %ymm0, %ymm1, %ymm2
+vfmsub231ps (%rax), %ymm1, %ymm2
+
+vfmsub132sd %xmm0, %xmm1, %xmm2
+vfmsub132sd (%rax), %xmm1, %xmm2
+
+vfmsub213sd %xmm0, %xmm1, %xmm2
+vfmsub213sd (%rax), %xmm1, %xmm2
+
+vfmsub231sd %xmm0, %xmm1, %xmm2
+vfmsub231sd (%rax), %xmm1, %xmm2
+
+vfmsub132ss %xmm0, %xmm1, %xmm2
+vfmsub132ss (%rax), %xmm1, %xmm2
+
+vfmsub213ss %xmm0, %xmm1, %xmm2
+vfmsub213ss (%rax), %xmm1, %xmm2
+
+vfmsub231ss %xmm0, %xmm1, %xmm2
+vfmsub231ss (%rax), %xmm1, %xmm2
+
+vfmsubadd132pd %xmm0, %xmm1, %xmm2
+vfmsubadd132pd (%rax), %xmm1, %xmm2
+
+vfmsubadd132pd %ymm0, %ymm1, %ymm2
+vfmsubadd132pd (%rax), %ymm1, %ymm2
+
+vfmsubadd213pd %xmm0, %xmm1, %xmm2
+vfmsubadd213pd (%rax), %xmm1, %xmm2
+
+vfmsubadd213pd %ymm0, %ymm1, %ymm2
+vfmsubadd213pd (%rax), %ymm1, %ymm2
+
+vfmsubadd231pd %xmm0, %xmm1, %xmm2
+vfmsubadd231pd (%rax), %xmm1, %xmm2
+
+vfmsubadd231pd %ymm0, %ymm1, %ymm2
+vfmsubadd231pd (%rax), %ymm1, %ymm2
+
+vfmsubadd132ps %xmm0, %xmm1, %xmm2
+vfmsubadd132ps (%rax), %xmm1, %xmm2
+
+vfmsubadd132ps %ymm0, %ymm1, %ymm2
+vfmsubadd132ps (%rax), %ymm1, %ymm2
+
+vfmsubadd213ps %xmm0, %xmm1, %xmm2
+vfmsubadd213ps (%rax), %xmm1, %xmm2
+
+vfmsubadd213ps %ymm0, %ymm1, %ymm2
+vfmsubadd213ps (%rax), %ymm1, %ymm2
+
+vfmsubadd231ps %xmm0, %xmm1, %xmm2
+vfmsubadd231ps (%rax), %xmm1, %xmm2
+
+vfmsubadd231ps %ymm0, %ymm1, %ymm2
+vfmsubadd231ps (%rax), %ymm1, %ymm2
+
+vfnmadd132pd %xmm0, %xmm1, %xmm2
+vfnmadd132pd (%rax), %xmm1, %xmm2
+
+vfnmadd132pd %ymm0, %ymm1, %ymm2
+vfnmadd132pd (%rax), %ymm1, %ymm2
+
+vfnmadd213pd %xmm0, %xmm1, %xmm2
+vfnmadd213pd (%rax), %xmm1, %xmm2
+
+vfnmadd213pd %ymm0, %ymm1, %ymm2
+vfnmadd213pd (%rax), %ymm1, %ymm2
+
+vfnmadd231pd %xmm0, %xmm1, %xmm2
+vfnmadd231pd (%rax), %xmm1, %xmm2
+
+vfnmadd231pd %ymm0, %ymm1, %ymm2
+vfnmadd231pd (%rax), %ymm1, %ymm2
+
+vfnmadd132ps %xmm0, %xmm1, %xmm2
+vfnmadd132ps (%rax), %xmm1, %xmm2
+
+vfnmadd132ps %ymm0, %ymm1, %ymm2
+vfnmadd132ps (%rax), %ymm1, %ymm2
+
+vfnmadd213ps %xmm0, %xmm1, %xmm2
+vfnmadd213ps (%rax), %xmm1, %xmm2
+
+vfnmadd213ps %ymm0, %ymm1, %ymm2
+vfnmadd213ps (%rax), %ymm1, %ymm2
+
+vfnmadd231ps %xmm0, %xmm1, %xmm2
+vfnmadd231ps (%rax), %xmm1, %xmm2
+
+vfnmadd231ps %ymm0, %ymm1, %ymm2
+vfnmadd231ps (%rax), %ymm1, %ymm2
+
+vfnmadd132sd %xmm0, %xmm1, %xmm2
+vfnmadd132sd (%rax), %xmm1, %xmm2
+
+vfnmadd213sd %xmm0, %xmm1, %xmm2
+vfnmadd213sd (%rax), %xmm1, %xmm2
+
+vfnmadd231sd %xmm0, %xmm1, %xmm2
+vfnmadd231sd (%rax), %xmm1, %xmm2
+
+vfnmadd132ss %xmm0, %xmm1, %xmm2
+vfnmadd132ss (%rax), %xmm1, %xmm2
+
+vfnmadd213ss %xmm0, %xmm1, %xmm2
+vfnmadd213ss (%rax), %xmm1, %xmm2
+
+vfnmadd231ss %xmm0, %xmm1, %xmm2
+vfnmadd231ss (%rax), %xmm1, %xmm2
+
+vfnmsub132pd %xmm0, %xmm1, %xmm2
+vfnmsub132pd (%rax), %xmm1, %xmm2
+
+vfnmsub132pd %ymm0, %ymm1, %ymm2
+vfnmsub132pd (%rax), %ymm1, %ymm2
+
+vfnmsub213pd %xmm0, %xmm1, %xmm2
+vfnmsub213pd (%rax), %xmm1, %xmm2
+
+vfnmsub213pd %ymm0, %ymm1, %ymm2
+vfnmsub213pd (%rax), %ymm1, %ymm2
+
+vfnmsub231pd %xmm0, %xmm1, %xmm2
+vfnmsub231pd (%rax), %xmm1, %xmm2
+
+vfnmsub231pd %ymm0, %ymm1, %ymm2
+vfnmsub231pd (%rax), %ymm1, %ymm2
+
+vfnmsub132ps %xmm0, %xmm1, %xmm2
+vfnmsub132ps (%rax), %xmm1, %xmm2
+
+vfnmsub132ps %ymm0, %ymm1, %ymm2
+vfnmsub132ps (%rax), %ymm1, %ymm2
+
+vfnmsub213ps %xmm0, %xmm1, %xmm2
+vfnmsub213ps (%rax), %xmm1, %xmm2
+
+vfnmsub213ps %ymm0, %ymm1, %ymm2
+vfnmsub213ps (%rax), %ymm1, %ymm2
+
+vfnmsub231ps %xmm0, %xmm1, %xmm2
+vfnmsub231ps (%rax), %xmm1, %xmm2
+
+vfnmsub231ps %ymm0, %ymm1, %ymm2
+vfnmsub231ps (%rax), %ymm1, %ymm2
+
+vfnmsub132sd %xmm0, %xmm1, %xmm2
+vfnmsub132sd (%rax), %xmm1, %xmm2
+
+vfnmsub213sd %xmm0, %xmm1, %xmm2
+vfnmsub213sd (%rax), %xmm1, %xmm2
+
+vfnmsub231sd %xmm0, %xmm1, %xmm2
+vfnmsub231sd (%rax), %xmm1, %xmm2
+
+vfnmsub132ss %xmm0, %xmm1, %xmm2
+vfnmsub132ss (%rax), %xmm1, %xmm2
+
+vfnmsub213ss %xmm0, %xmm1, %xmm2
+vfnmsub213ss (%rax), %xmm1, %xmm2
+
+vfnmsub231ss %xmm0, %xmm1, %xmm2
+vfnmsub231ss (%rax), %xmm1, %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 2.00 vfmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmaddsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmaddsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmaddsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmaddsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmaddsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmaddsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmaddsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmaddsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmaddsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmaddsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmaddsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmaddsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmaddsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmaddsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmaddsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmaddsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmaddsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmaddsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmaddsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmaddsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmaddsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmaddsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmaddsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmaddsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsub231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsubadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsubadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsubadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmsubadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmsubadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsubadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsubadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmsubadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmsubadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsubadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsubadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmsubadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmsubadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsubadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsubadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmsubadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmsubadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsubadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsubadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmsubadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfmsubadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfmsubadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfmsubadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfmsubadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfnmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfnmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfnmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfnmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfnmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfnmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfnmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfnmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfnmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfnmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfnmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.33 * vfnmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vfnmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vfnmsub231ss (%rax), %xmm1, %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - - - - - - - - - 204.00 204.00 204.00 - - - - 384.00 384.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmaddsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmaddsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmaddsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmaddsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmaddsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmaddsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmaddsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmaddsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmaddsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmaddsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmaddsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmaddsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmaddsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmaddsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmaddsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmaddsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmaddsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmaddsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmaddsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmaddsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmaddsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmaddsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmaddsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmaddsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsub231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsubadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsubadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsubadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmsubadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsubadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsubadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsubadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmsubadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsubadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsubadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsubadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmsubadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsubadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsubadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsubadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmsubadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsubadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsubadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsubadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmsubadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsubadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfmsubadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfmsubadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfmsubadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfnmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfnmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfnmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfnmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfnmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfnmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfnmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfnmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfnmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfnmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfnmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vfnmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vfnmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vfnmsub231ss (%rax), %xmm1, %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-fsgsbase.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-fsgsbase.s
new file mode 100644
index 0000000000000..b44952d3a2b71
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-fsgsbase.s
@@ -0,0 +1,69 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+rdfsbase %eax
+rdfsbase %rax
+
+rdgsbase %eax
+rdgsbase %rax
+
+wrfsbase %edi
+wrfsbase %rdi
+
+wrgsbase %edi
+wrgsbase %rdi
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.17 * * U rdfsbasel %eax
+# CHECK-NEXT: 1 100 0.17 * * U rdfsbaseq %rax
+# CHECK-NEXT: 1 100 0.17 * * U rdgsbasel %eax
+# CHECK-NEXT: 1 100 0.17 * * U rdgsbaseq %rax
+# CHECK-NEXT: 1 100 0.17 * * U wrfsbasel %edi
+# CHECK-NEXT: 1 100 0.17 * * U wrfsbaseq %rdi
+# CHECK-NEXT: 1 100 0.17 * * U wrgsbasel %edi
+# CHECK-NEXT: 1 100 0.17 * * U wrgsbaseq %rdi
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - 1.33 1.33 1.33 1.33 1.33 1.33 - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - rdfsbasel %eax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - rdfsbaseq %rax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - rdgsbasel %eax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - rdgsbaseq %rax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - wrfsbasel %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - wrfsbaseq %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - wrgsbasel %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - wrgsbaseq %rdi
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-gfni.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-gfni.s
new file mode 100644
index 0000000000000..9a05282cb27a0
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-gfni.s
@@ -0,0 +1,62 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+gf2p8affineinvqb $0, %xmm0, %xmm1
+gf2p8affineinvqb $0, (%rax), %xmm1
+
+gf2p8affineqb $0, %xmm0, %xmm1
+gf2p8affineqb $0, (%rax), %xmm1
+
+gf2p8mulb %xmm0, %xmm1
+gf2p8mulb (%rax), %xmm1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 2.00 gf2p8affineinvqb $0, %xmm0, %xmm1
+# CHECK-NEXT: 2 10 2.00 * gf2p8affineinvqb $0, (%rax), %xmm1
+# CHECK-NEXT: 1 3 2.00 gf2p8affineqb $0, %xmm0, %xmm1
+# CHECK-NEXT: 2 10 2.00 * gf2p8affineqb $0, (%rax), %xmm1
+# CHECK-NEXT: 1 3 2.00 gf2p8mulb %xmm0, %xmm1
+# CHECK-NEXT: 2 10 2.00 * gf2p8mulb (%rax), %xmm1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - - - - - - - - - 6.00 6.00 6.00 - - - - 12.00 12.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - gf2p8affineinvqb $0, %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - gf2p8affineinvqb $0, (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - gf2p8affineqb $0, %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - gf2p8affineqb $0, (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - gf2p8mulb %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - gf2p8mulb (%rax), %xmm1
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-lea.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-lea.s
new file mode 100644
index 0000000000000..03c2690516f82
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-lea.s
@@ -0,0 +1,449 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+lea 0(), %cx
+lea 0(), %ecx
+lea 0(), %rcx
+lea (%eax), %cx
+lea (%eax), %ecx
+lea (%eax), %rcx
+lea (%rax), %cx
+lea (%rax), %ecx
+lea (%rax), %rcx
+lea (, %ebx), %cx
+lea (, %ebx), %ecx
+lea (, %ebx), %rcx
+lea (, %rbx), %cx
+lea (, %rbx), %ecx
+lea (, %rbx), %rcx
+lea (, %ebx, 1), %cx
+lea (, %ebx, 1), %ecx
+lea (, %ebx, 1), %rcx
+lea (, %rbx, 1), %cx
+lea (, %rbx, 1), %ecx
+lea (, %rbx, 1), %rcx
+lea (, %ebx, 2), %cx
+lea (, %ebx, 2), %ecx
+lea (, %ebx, 2), %rcx
+lea (, %rbx, 2), %cx
+lea (, %rbx, 2), %ecx
+lea (, %rbx, 2), %rcx
+lea (%eax, %ebx), %cx
+lea (%eax, %ebx), %ecx
+lea (%eax, %ebx), %rcx
+lea (%rax, %rbx), %cx
+lea (%rax, %rbx), %ecx
+lea (%rax, %rbx), %rcx
+lea (%eax, %ebx, 1), %cx
+lea (%eax, %ebx, 1), %ecx
+lea (%eax, %ebx, 1), %rcx
+lea (%rax, %rbx, 1), %cx
+lea (%rax, %rbx, 1), %ecx
+lea (%rax, %rbx, 1), %rcx
+lea (%eax, %ebx, 2), %cx
+lea (%eax, %ebx, 2), %ecx
+lea (%eax, %ebx, 2), %rcx
+lea (%rax, %rbx, 2), %cx
+lea (%rax, %rbx, 2), %ecx
+lea (%rax, %rbx, 2), %rcx
+
+lea -16(), %cx
+lea -16(), %ecx
+lea -16(), %rcx
+lea -16(%eax), %cx
+lea -16(%eax), %ecx
+lea -16(%eax), %rcx
+lea -16(%rax), %cx
+lea -16(%rax), %ecx
+lea -16(%rax), %rcx
+lea -16(, %ebx), %cx
+lea -16(, %ebx), %ecx
+lea -16(, %ebx), %rcx
+lea -16(, %rbx), %cx
+lea -16(, %rbx), %ecx
+lea -16(, %rbx), %rcx
+lea -16(, %ebx, 1), %cx
+lea -16(, %ebx, 1), %ecx
+lea -16(, %ebx, 1), %rcx
+lea -16(, %rbx, 1), %cx
+lea -16(, %rbx, 1), %ecx
+lea -16(, %rbx, 1), %rcx
+lea -16(, %ebx, 2), %cx
+lea -16(, %ebx, 2), %ecx
+lea -16(, %ebx, 2), %rcx
+lea -16(, %rbx, 2), %cx
+lea -16(, %rbx, 2), %ecx
+lea -16(, %rbx, 2), %rcx
+lea -16(%eax, %ebx), %cx
+lea -16(%eax, %ebx), %ecx
+lea -16(%eax, %ebx), %rcx
+lea -16(%rax, %rbx), %cx
+lea -16(%rax, %rbx), %ecx
+lea -16(%rax, %rbx), %rcx
+lea -16(%eax, %ebx, 1), %cx
+lea -16(%eax, %ebx, 1), %ecx
+lea -16(%eax, %ebx, 1), %rcx
+lea -16(%rax, %rbx, 1), %cx
+lea -16(%rax, %rbx, 1), %ecx
+lea -16(%rax, %rbx, 1), %rcx
+lea -16(%eax, %ebx, 2), %cx
+lea -16(%eax, %ebx, 2), %ecx
+lea -16(%eax, %ebx, 2), %rcx
+lea -16(%rax, %rbx, 2), %cx
+lea -16(%rax, %rbx, 2), %ecx
+lea -16(%rax, %rbx, 2), %rcx
+
+lea 1024(), %cx
+lea 1024(), %ecx
+lea 1024(), %rcx
+lea 1024(%eax), %cx
+lea 1024(%eax), %ecx
+lea 1024(%eax), %rcx
+lea 1024(%rax), %cx
+lea 1024(%rax), %ecx
+lea 1024(%rax), %rcx
+lea 1024(, %ebx), %cx
+lea 1024(, %ebx), %ecx
+lea 1024(, %ebx), %rcx
+lea 1024(, %rbx), %cx
+lea 1024(, %rbx), %ecx
+lea 1024(, %rbx), %rcx
+lea 1024(, %ebx, 1), %cx
+lea 1024(, %ebx, 1), %ecx
+lea 1024(, %ebx, 1), %rcx
+lea 1024(, %rbx, 1), %cx
+lea 1024(, %rbx, 1), %ecx
+lea 1024(, %rbx, 1), %rcx
+lea 1024(, %ebx, 2), %cx
+lea 1024(, %ebx, 2), %ecx
+lea 1024(, %ebx, 2), %rcx
+lea 1024(, %rbx, 2), %cx
+lea 1024(, %rbx, 2), %ecx
+lea 1024(, %rbx, 2), %rcx
+lea 1024(%eax, %ebx), %cx
+lea 1024(%eax, %ebx), %ecx
+lea 1024(%eax, %ebx), %rcx
+lea 1024(%rax, %rbx), %cx
+lea 1024(%rax, %rbx), %ecx
+lea 1024(%rax, %rbx), %rcx
+lea 1024(%eax, %ebx, 1), %cx
+lea 1024(%eax, %ebx, 1), %ecx
+lea 1024(%eax, %ebx, 1), %rcx
+lea 1024(%rax, %rbx, 1), %cx
+lea 1024(%rax, %rbx, 1), %ecx
+lea 1024(%rax, %rbx, 1), %rcx
+lea 1024(%eax, %ebx, 2), %cx
+lea 1024(%eax, %ebx, 2), %ecx
+lea 1024(%eax, %ebx, 2), %rcx
+lea 1024(%rax, %rbx, 2), %cx
+lea 1024(%rax, %rbx, 2), %ecx
+lea 1024(%rax, %rbx, 2), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 2 2 0.33 leaw 0, %cx
+# CHECK-NEXT: 1 1 1.00 leal 0, %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 0, %rcx
+# CHECK-NEXT: 2 2 0.33 leaw (%eax), %cx
+# CHECK-NEXT: 1 1 1.00 leal (%eax), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (%eax), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw (%rax), %cx
+# CHECK-NEXT: 1 1 1.00 leal (%rax), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (%rax), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw (,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal (,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw (,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal (,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw (,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal (,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw (,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal (,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw (,%ebx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal (,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw (,%rbx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal (,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw (%eax,%ebx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal (%eax,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (%eax,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw (%rax,%rbx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal (%rax,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (%rax,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw -16, %cx
+# CHECK-NEXT: 1 1 1.00 leal -16, %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16, %rcx
+# CHECK-NEXT: 2 2 0.33 leaw -16(%eax), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(%eax), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(%eax), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw -16(%rax), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(%rax), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(%rax), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw -16(,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw -16(,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw -16(,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw -16(,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw -16(,%ebx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw -16(,%rbx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw -16(%eax,%ebx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(%eax,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw -16(%rax,%rbx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(%rax,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(%rax,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw 1024, %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024, %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024, %rcx
+# CHECK-NEXT: 2 2 0.33 leaw 1024(%eax), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(%eax), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(%eax), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw 1024(%rax), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(%rax), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(%rax), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw 1024(,%ebx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw 1024(,%rbx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw 1024(%eax,%ebx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(%eax,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 0.33 leaw 1024(%rax,%rbx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(%rax,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(%rax,%rbx,2), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - 7.50 112.50 7.50 22.50 7.50 22.50 - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw 0, %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal 0, %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq 0, %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw (%eax), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal (%eax), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq (%eax), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw (%rax), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal (%rax), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq (%rax), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw (,%ebx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal (,%ebx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq (,%ebx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw (,%rbx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal (,%rbx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq (,%rbx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw (,%ebx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal (,%ebx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq (,%ebx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw (,%rbx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal (,%rbx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq (,%rbx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw (,%ebx,2), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal (,%ebx,2), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq (,%ebx,2), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw (,%rbx,2), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal (,%rbx,2), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq (,%rbx,2), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw (%eax,%ebx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal (%eax,%ebx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw (%rax,%rbx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal (%rax,%rbx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw (%eax,%ebx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal (%eax,%ebx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw (%rax,%rbx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal (%rax,%rbx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw (%eax,%ebx,2), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal (%eax,%ebx,2), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq (%eax,%ebx,2), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw (%rax,%rbx,2), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal (%rax,%rbx,2), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq (%rax,%rbx,2), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw -16, %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal -16, %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq -16, %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw -16(%eax), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal -16(%eax), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq -16(%eax), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw -16(%rax), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal -16(%rax), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq -16(%rax), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw -16(,%ebx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal -16(,%ebx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq -16(,%ebx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw -16(,%rbx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal -16(,%rbx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq -16(,%rbx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw -16(,%ebx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal -16(,%ebx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq -16(,%ebx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw -16(,%rbx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal -16(,%rbx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq -16(,%rbx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw -16(,%ebx,2), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal -16(,%ebx,2), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq -16(,%ebx,2), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw -16(,%rbx,2), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal -16(,%rbx,2), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq -16(,%rbx,2), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw -16(%eax,%ebx,2), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal -16(%eax,%ebx,2), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq -16(%eax,%ebx,2), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw -16(%rax,%rbx,2), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal -16(%rax,%rbx,2), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq -16(%rax,%rbx,2), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw 1024, %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal 1024, %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq 1024, %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw 1024(%eax), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal 1024(%eax), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq 1024(%eax), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw 1024(%rax), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal 1024(%rax), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq 1024(%rax), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw 1024(,%ebx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal 1024(,%ebx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw 1024(,%rbx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal 1024(,%rbx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw 1024(,%ebx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal 1024(,%ebx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw 1024(,%rbx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal 1024(,%rbx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw 1024(,%ebx,2), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal 1024(,%ebx,2), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq 1024(,%ebx,2), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw 1024(,%rbx,2), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal 1024(,%rbx,2), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq 1024(,%rbx,2), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw 1024(%eax,%ebx,2), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal 1024(%eax,%ebx,2), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq 1024(%eax,%ebx,2), %rcx
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - leaw 1024(%rax,%rbx,2), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leal 1024(%rax,%rbx,2), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - leaq 1024(%rax,%rbx,2), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-lzcnt.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-lzcnt.s
new file mode 100644
index 0000000000000..d3a826f1ba2c1
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-lzcnt.s
@@ -0,0 +1,62 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+lzcntw %cx, %cx
+lzcntw (%rax), %cx
+
+lzcntl %eax, %ecx
+lzcntl (%rax), %ecx
+
+lzcntq %rax, %rcx
+lzcntq (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 lzcntw %cx, %cx
+# CHECK-NEXT: 2 7 1.00 * lzcntw (%rax), %cx
+# CHECK-NEXT: 1 3 1.00 lzcntl %eax, %ecx
+# CHECK-NEXT: 2 7 1.00 * lzcntl (%rax), %ecx
+# CHECK-NEXT: 1 3 1.00 lzcntq %rax, %rcx
+# CHECK-NEXT: 2 7 1.00 * lzcntq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - - 6.00 - - - - - - 1.00 1.00 1.00 - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - lzcntw %cx, %cx
+# CHECK-NEXT: - - 1.00 - - - - - - 0.33 0.33 0.33 - - - - - - - - lzcntw (%rax), %cx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - lzcntl %eax, %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - 0.33 0.33 0.33 - - - - - - - - lzcntl (%rax), %ecx
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - lzcntq %rax, %rcx
+# CHECK-NEXT: - - 1.00 - - - - - - 0.33 0.33 0.33 - - - - - - - - lzcntq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-mmx.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-mmx.s
new file mode 100644
index 0000000000000..ac185e6ec8de9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-mmx.s
@@ -0,0 +1,405 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+emms
+
+movd %eax, %mm2
+movd (%rax), %mm2
+
+movd %mm0, %ecx
+movd %mm0, (%rax)
+
+movq %rax, %mm2
+movq (%rax), %mm2
+
+movq %mm0, %rcx
+movq %mm0, (%rax)
+
+packsswb %mm0, %mm2
+packsswb (%rax), %mm2
+
+packssdw %mm0, %mm2
+packssdw (%rax), %mm2
+
+packuswb %mm0, %mm2
+packuswb (%rax), %mm2
+
+paddb %mm0, %mm2
+paddb (%rax), %mm2
+
+paddd %mm0, %mm2
+paddd (%rax), %mm2
+
+paddsb %mm0, %mm2
+paddsb (%rax), %mm2
+
+paddsw %mm0, %mm2
+paddsw (%rax), %mm2
+
+paddusb %mm0, %mm2
+paddusb (%rax), %mm2
+
+paddusw %mm0, %mm2
+paddusw (%rax), %mm2
+
+paddw %mm0, %mm2
+paddw (%rax), %mm2
+
+pand %mm0, %mm2
+pand (%rax), %mm2
+
+pandn %mm0, %mm2
+pandn (%rax), %mm2
+
+pcmpeqb %mm0, %mm2
+pcmpeqb (%rax), %mm2
+
+pcmpeqd %mm0, %mm2
+pcmpeqd (%rax), %mm2
+
+pcmpeqw %mm0, %mm2
+pcmpeqw (%rax), %mm2
+
+pcmpgtb %mm0, %mm2
+pcmpgtb (%rax), %mm2
+
+pcmpgtd %mm0, %mm2
+pcmpgtd (%rax), %mm2
+
+pcmpgtw %mm0, %mm2
+pcmpgtw (%rax), %mm2
+
+pmaddwd %mm0, %mm2
+pmaddwd (%rax), %mm2
+
+pmulhw %mm0, %mm2
+pmulhw (%rax), %mm2
+
+pmullw %mm0, %mm2
+pmullw (%rax), %mm2
+
+por %mm0, %mm2
+por (%rax), %mm2
+
+pslld $1, %mm2
+pslld %mm0, %mm2
+pslld (%rax), %mm2
+
+psllq $1, %mm2
+psllq %mm0, %mm2
+psllq (%rax), %mm2
+
+psllw $1, %mm2
+psllw %mm0, %mm2
+psllw (%rax), %mm2
+
+psrad $1, %mm2
+psrad %mm0, %mm2
+psrad (%rax), %mm2
+
+psraw $1, %mm2
+psraw %mm0, %mm2
+psraw (%rax), %mm2
+
+psrld $1, %mm2
+psrld %mm0, %mm2
+psrld (%rax), %mm2
+
+psrlq $1, %mm2
+psrlq %mm0, %mm2
+psrlq (%rax), %mm2
+
+psrlw $1, %mm2
+psrlw %mm0, %mm2
+psrlw (%rax), %mm2
+
+psubb %mm0, %mm2
+psubb (%rax), %mm2
+
+psubd %mm0, %mm2
+psubd (%rax), %mm2
+
+psubsb %mm0, %mm2
+psubsb (%rax), %mm2
+
+psubsw %mm0, %mm2
+psubsw (%rax), %mm2
+
+psubusb %mm0, %mm2
+psubusb (%rax), %mm2
+
+psubusw %mm0, %mm2
+psubusw (%rax), %mm2
+
+psubw %mm0, %mm2
+psubw (%rax), %mm2
+
+punpckhbw %mm0, %mm2
+punpckhbw (%rax), %mm2
+
+punpckhdq %mm0, %mm2
+punpckhdq (%rax), %mm2
+
+punpckhwd %mm0, %mm2
+punpckhwd (%rax), %mm2
+
+punpcklbw %mm0, %mm2
+punpcklbw (%rax), %mm2
+
+punpckldq %mm0, %mm2
+punpckldq (%rax), %mm2
+
+punpcklwd %mm0, %mm2
+punpcklwd (%rax), %mm2
+
+pxor %mm0, %mm2
+pxor (%rax), %mm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 10 10 4.00 * * U emms
+# CHECK-NEXT: 1 3 0.33 movd %eax, %mm2
+# CHECK-NEXT: 1 8 0.33 * movd (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 movd %mm0, %ecx
+# CHECK-NEXT: 2 18 0.50 * U movd %mm0, (%rax)
+# CHECK-NEXT: 1 3 0.33 movq %rax, %mm2
+# CHECK-NEXT: 1 8 0.33 * movq (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 movq %mm0, %rcx
+# CHECK-NEXT: 2 12 0.50 * movq %mm0, (%rax)
+# CHECK-NEXT: 2 4 0.67 packsswb %mm0, %mm2
+# CHECK-NEXT: 3 12 0.67 * packsswb (%rax), %mm2
+# CHECK-NEXT: 2 4 0.67 packssdw %mm0, %mm2
+# CHECK-NEXT: 3 12 0.67 * packssdw (%rax), %mm2
+# CHECK-NEXT: 2 4 0.67 packuswb %mm0, %mm2
+# CHECK-NEXT: 3 12 0.67 * packuswb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.33 paddb %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * paddb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.33 paddd %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * paddd (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 paddsb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * paddsb (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 paddsw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * paddsw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 paddusb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * paddusb (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 paddusw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * paddusw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.33 paddw %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * paddw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pand %mm0, %mm2
+# CHECK-NEXT: 2 9 0.33 * pand (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pandn %mm0, %mm2
+# CHECK-NEXT: 2 9 0.33 * pandn (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pcmpeqb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pcmpeqb (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pcmpeqd %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pcmpeqd (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pcmpeqw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pcmpeqw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pcmpgtb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pcmpgtb (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pcmpgtd %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pcmpgtd (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pcmpgtw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pcmpgtw (%rax), %mm2
+# CHECK-NEXT: 1 5 0.50 pmaddwd %mm0, %mm2
+# CHECK-NEXT: 2 13 0.50 * pmaddwd (%rax), %mm2
+# CHECK-NEXT: 1 5 0.50 pmulhw %mm0, %mm2
+# CHECK-NEXT: 2 13 0.50 * pmulhw (%rax), %mm2
+# CHECK-NEXT: 1 5 0.50 pmullw %mm0, %mm2
+# CHECK-NEXT: 2 13 0.50 * pmullw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 por %mm0, %mm2
+# CHECK-NEXT: 2 9 0.33 * por (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pslld $1, %mm2
+# CHECK-NEXT: 1 1 0.50 pslld %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * pslld (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psllq $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psllq %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * psllq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psllw $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psllw %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * psllw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psrad $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psrad %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * psrad (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psraw $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psraw %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * psraw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psrld $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psrld %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * psrld (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psrlq $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psrlq %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * psrlq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psrlw $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psrlw %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * psrlw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.33 psubb %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * psubb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.33 psubd %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * psubd (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psubsb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psubsb (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psubsw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psubsw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psubusb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psubusb (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psubusw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psubusw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.33 psubw %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * psubw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpckhbw %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * punpckhbw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpckhdq %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * punpckhdq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpckhwd %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * punpckhwd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpcklbw %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * punpcklbw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpckldq %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * punpckldq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpcklwd %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * punpcklwd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pxor %mm0, %mm2
+# CHECK-NEXT: 2 9 0.33 * pxor (%rax), %mm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - - 7.67 - 6.67 - 6.67 1.00 1.00 15.33 15.33 15.33 0.67 0.67 0.67 - 53.00 25.00 8.50 8.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - 4.00 4.00 0.50 0.50 emms
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - movd %eax, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - movd %mm0, %ecx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movd %mm0, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - movq %rax, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - movq %mm0, %rcx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movq %mm0, (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - packsswb %mm0, %mm2
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 0.33 0.33 0.33 - - - - - - - - packsswb (%rax), %mm2
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - packssdw %mm0, %mm2
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 0.33 0.33 0.33 - - - - - - - - packssdw (%rax), %mm2
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - packuswb %mm0, %mm2
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 0.33 0.33 0.33 - - - - - - - - packuswb (%rax), %mm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - paddb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - paddb (%rax), %mm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - paddd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - paddd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - paddsb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - paddsb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - paddsw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - paddsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - paddusb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - paddusb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - paddusw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - paddusw (%rax), %mm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - paddw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - paddw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 pand %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 pand (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 pandn %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 pandn (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pcmpeqb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - pcmpeqb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pcmpeqd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - pcmpeqd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pcmpeqw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - pcmpeqw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pcmpgtb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - pcmpgtb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pcmpgtd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - pcmpgtd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pcmpgtw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - pcmpgtw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pmaddwd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - pmaddwd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pmulhw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - pmulhw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pmullw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - pmullw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 por %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 por (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pslld $1, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pslld %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - pslld (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psllq $1, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psllq %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psllq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psllw $1, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psllw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psllw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psrad $1, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psrad %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psrad (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psraw $1, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psraw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psraw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psrld $1, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psrld %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psrld (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psrlq $1, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psrlq %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psrlq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psrlw $1, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psrlw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psrlw (%rax), %mm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - psubb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psubb (%rax), %mm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - psubd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psubd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - psubsb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - psubsb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - psubsw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - psubsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - psubusb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - psubusb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - psubusw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - psubusw (%rax), %mm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - psubw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psubw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 punpckhbw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 punpckhbw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 punpckhdq %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 punpckhdq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 punpckhwd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 punpckhwd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 punpcklbw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 punpcklbw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 punpckldq %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 punpckldq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 punpcklwd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 punpcklwd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 pxor %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 pxor (%rax), %mm2
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-movbe.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-movbe.s
new file mode 100644
index 0000000000000..9b63f05745d82
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-movbe.s
@@ -0,0 +1,62 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+movbe %cx, (%rax)
+movbe (%rax), %cx
+
+movbe %ecx, (%rax)
+movbe (%rax), %ecx
+
+movbe %rcx, (%rax)
+movbe (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 3 12 0.50 * movbew %cx, (%rax)
+# CHECK-NEXT: 3 100 1.33 * movbew (%rax), %cx
+# CHECK-NEXT: 3 12 0.50 * movbel %ecx, (%rax)
+# CHECK-NEXT: 3 100 1.33 * movbel (%rax), %ecx
+# CHECK-NEXT: 4 12 0.50 * movbeq %rcx, (%rax)
+# CHECK-NEXT: 3 100 1.33 * movbeq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - 0.67 2.67 0.67 2.67 0.67 2.67 1.50 1.50 4.00 4.00 4.00 1.00 1.00 1.00 - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movbew %cx, (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 1.33 1.33 1.33 - - - - - - - - movbew (%rax), %cx
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movbel %ecx, (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 1.33 1.33 1.33 - - - - - - - - movbel (%rax), %ecx
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movbeq %rcx, (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 1.33 1.33 1.33 - - - - - - - - movbeq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-pclmul.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-pclmul.s
new file mode 100644
index 0000000000000..8de78d26347c7
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-pclmul.s
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+pclmulqdq $11, %xmm0, %xmm2
+pclmulqdq $11, (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 pclmulqdq $11, %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * pclmulqdq $11, (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 1.00 1.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pclmulqdq $11, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 pclmulqdq $11, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-popcnt.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-popcnt.s
new file mode 100644
index 0000000000000..c2715247a0d73
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-popcnt.s
@@ -0,0 +1,62 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+popcntw %cx, %cx
+popcntw (%rax), %cx
+
+popcntl %eax, %ecx
+popcntl (%rax), %ecx
+
+popcntq %rax, %rcx
+popcntq (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.33 popcntw %cx, %cx
+# CHECK-NEXT: 2 7 0.33 * popcntw (%rax), %cx
+# CHECK-NEXT: 1 3 0.33 popcntl %eax, %ecx
+# CHECK-NEXT: 2 7 0.33 * popcntl (%rax), %ecx
+# CHECK-NEXT: 1 3 0.33 popcntq %rax, %rcx
+# CHECK-NEXT: 2 7 0.33 * popcntq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - - 2.00 - 2.00 - 2.00 - - 1.00 1.00 1.00 - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - popcntw %cx, %cx
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - popcntw (%rax), %cx
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - popcntl %eax, %ecx
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - popcntl (%rax), %ecx
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - popcntq %rax, %rcx
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - popcntq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-prefetchw.s
new file mode 100644
index 0000000000000..f9ccc8f2c97ad
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-prefetchw.s
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+prefetch (%rax)
+prefetchw (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 0.33 * * prefetch (%rax)
+# CHECK-NEXT: 1 4 0.33 * * prefetchw (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - - - - - - - - - 0.67 0.67 0.67 - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - prefetch (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - prefetchw (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-rdrand.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-rdrand.s
new file mode 100644
index 0000000000000..c4ff8886bea73
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-rdrand.s
@@ -0,0 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+rdrand %ax
+rdrand %eax
+rdrand %rax
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.17 U rdrandw %ax
+# CHECK-NEXT: 1 100 0.17 U rdrandl %eax
+# CHECK-NEXT: 1 100 0.17 U rdrandq %rax
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - 0.50 0.50 0.50 0.50 0.50 0.50 - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - rdrandw %ax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - rdrandl %eax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - rdrandq %rax
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-rdseed.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-rdseed.s
new file mode 100644
index 0000000000000..5cd9e051ef90d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-rdseed.s
@@ -0,0 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+rdseed %ax
+rdseed %eax
+rdseed %rax
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.17 U rdseedw %ax
+# CHECK-NEXT: 1 100 0.17 U rdseedl %eax
+# CHECK-NEXT: 1 100 0.17 U rdseedq %rax
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - 0.50 0.50 0.50 0.50 0.50 0.50 - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - rdseedw %ax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - rdseedl %eax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - rdseedq %rax
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse1.s
new file mode 100644
index 0000000000000..c5c21d8fe8494
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse1.s
@@ -0,0 +1,473 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+addps %xmm0, %xmm2
+addps (%rax), %xmm2
+
+addss %xmm0, %xmm2
+addss (%rax), %xmm2
+
+andnps %xmm0, %xmm2
+andnps (%rax), %xmm2
+
+andps %xmm0, %xmm2
+andps (%rax), %xmm2
+
+cmpps $0, %xmm0, %xmm2
+cmpps $0, (%rax), %xmm2
+
+cmpss $0, %xmm0, %xmm2
+cmpss $0, (%rax), %xmm2
+
+comiss %xmm0, %xmm1
+comiss (%rax), %xmm1
+
+cvtpi2ps %mm0, %xmm2
+cvtpi2ps (%rax), %xmm2
+
+cvtps2pi %xmm0, %mm2
+cvtps2pi (%rax), %mm2
+
+cvtsi2ss %ecx, %xmm2
+cvtsi2ss %rcx, %xmm2
+cvtsi2ss (%rax), %xmm2
+cvtsi2ss (%rax), %xmm2
+
+cvtss2si %xmm0, %ecx
+cvtss2si %xmm0, %rcx
+cvtss2si (%rax), %ecx
+cvtss2si (%rax), %rcx
+
+cvttps2pi %xmm0, %mm2
+cvttps2pi (%rax), %mm2
+
+cvttss2si %xmm0, %ecx
+cvttss2si %xmm0, %rcx
+cvttss2si (%rax), %ecx
+cvttss2si (%rax), %rcx
+
+divps %xmm0, %xmm2
+divps (%rax), %xmm2
+
+divss %xmm0, %xmm2
+divss (%rax), %xmm2
+
+ldmxcsr (%rax)
+
+maskmovq %mm0, %mm1
+
+maxps %xmm0, %xmm2
+maxps (%rax), %xmm2
+
+maxss %xmm0, %xmm2
+maxss (%rax), %xmm2
+
+minps %xmm0, %xmm2
+minps (%rax), %xmm2
+
+minss %xmm0, %xmm2
+minss (%rax), %xmm2
+
+movaps %xmm0, %xmm2
+movaps %xmm0, (%rax)
+movaps (%rax), %xmm2
+
+movhlps %xmm0, %xmm2
+movlhps %xmm0, %xmm2
+
+movhps %xmm0, (%rax)
+movhps (%rax), %xmm2
+
+movlps %xmm0, (%rax)
+movlps (%rax), %xmm2
+
+movmskps %xmm0, %rcx
+
+movntps %xmm0, (%rax)
+movntq %mm0, (%rax)
+
+movss %xmm0, %xmm2
+movss %xmm0, (%rax)
+movss (%rax), %xmm2
+
+movups %xmm0, %xmm2
+movups %xmm0, (%rax)
+movups (%rax), %xmm2
+
+mulps %xmm0, %xmm2
+mulps (%rax), %xmm2
+
+mulss %xmm0, %xmm2
+mulss (%rax), %xmm2
+
+orps %xmm0, %xmm2
+orps (%rax), %xmm2
+
+pavgb %mm0, %mm2
+pavgb (%rax), %mm2
+
+pavgw %mm0, %mm2
+pavgw (%rax), %mm2
+
+pextrw $1, %mm0, %rcx
+
+pinsrw $1, %rax, %mm2
+pinsrw $1, (%rax), %mm2
+
+pmaxsw %mm0, %mm2
+pmaxsw (%rax), %mm2
+
+pmaxub %mm0, %mm2
+pmaxub (%rax), %mm2
+
+pminsw %mm0, %mm2
+pminsw (%rax), %mm2
+
+pminub %mm0, %mm2
+pminub (%rax), %mm2
+
+pmovmskb %mm0, %rcx
+
+pmulhuw %mm0, %mm2
+pmulhuw (%rax), %mm2
+
+prefetcht0 (%rax)
+prefetcht1 (%rax)
+prefetcht2 (%rax)
+prefetchnta (%rax)
+
+psadbw %mm0, %mm2
+psadbw (%rax), %mm2
+
+pshufw $1, %mm0, %mm2
+pshufw $1, (%rax), %mm2
+
+rcpps %xmm0, %xmm2
+rcpps (%rax), %xmm2
+
+rcpss %xmm0, %xmm2
+rcpss (%rax), %xmm2
+
+rsqrtps %xmm0, %xmm2
+rsqrtps (%rax), %xmm2
+
+rsqrtss %xmm0, %xmm2
+rsqrtss (%rax), %xmm2
+
+sfence
+
+shufps $1, %xmm0, %xmm2
+shufps $1, (%rax), %xmm2
+
+sqrtps %xmm0, %xmm2
+sqrtps (%rax), %xmm2
+
+sqrtss %xmm0, %xmm2
+sqrtss (%rax), %xmm2
+
+stmxcsr (%rax)
+
+subps %xmm0, %xmm2
+subps (%rax), %xmm2
+
+subss %xmm0, %xmm2
+subss (%rax), %xmm2
+
+ucomiss %xmm0, %xmm1
+ucomiss (%rax), %xmm1
+
+unpckhps %xmm0, %xmm2
+unpckhps (%rax), %xmm2
+
+unpcklps %xmm0, %xmm2
+unpcklps (%rax), %xmm2
+
+xorps %xmm0, %xmm2
+xorps (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 addps %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * addps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.33 addss %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * addss (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 andnps %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * andnps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 andps %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * andps (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 cmpeqps %xmm0, %xmm2
+# CHECK-NEXT: 2 10 2.00 * cmpeqps (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 cmpeqss %xmm0, %xmm2
+# CHECK-NEXT: 2 10 2.00 * cmpeqss (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 comiss %xmm0, %xmm1
+# CHECK-NEXT: 2 9 2.00 * comiss (%rax), %xmm1
+# CHECK-NEXT: 2 100 2.50 cvtpi2ps %mm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * cvtpi2ps (%rax), %xmm2
+# CHECK-NEXT: 2 100 2.00 cvtps2pi %xmm0, %mm2
+# CHECK-NEXT: 2 13 2.67 * cvtps2pi (%rax), %mm2
+# CHECK-NEXT: 2 8 2.00 cvtsi2ss %ecx, %xmm2
+# CHECK-NEXT: 3 9 2.00 cvtsi2ss %rcx, %xmm2
+# CHECK-NEXT: 1 10 2.00 * cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: 1 10 2.00 * cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: 2 7 3.50 cvtss2si %xmm0, %ecx
+# CHECK-NEXT: 3 8 3.50 cvtss2si %xmm0, %rcx
+# CHECK-NEXT: 3 11 3.50 * cvtss2si (%rax), %ecx
+# CHECK-NEXT: 3 11 3.50 * cvtss2si (%rax), %rcx
+# CHECK-NEXT: 2 5 2.00 cvttps2pi %xmm0, %mm2
+# CHECK-NEXT: 2 13 2.67 * cvttps2pi (%rax), %mm2
+# CHECK-NEXT: 2 7 3.50 cvttss2si %xmm0, %ecx
+# CHECK-NEXT: 3 8 3.50 cvttss2si %xmm0, %rcx
+# CHECK-NEXT: 3 11 3.50 * cvttss2si (%rax), %ecx
+# CHECK-NEXT: 3 11 3.50 * cvttss2si (%rax), %rcx
+# CHECK-NEXT: 1 7 3.50 divps %xmm0, %xmm2
+# CHECK-NEXT: 1 13 3.50 * divps (%rax), %xmm2
+# CHECK-NEXT: 1 7 3.50 divss %xmm0, %xmm2
+# CHECK-NEXT: 1 13 3.50 * divss (%rax), %xmm2
+# CHECK-NEXT: 4 7 0.75 * * U ldmxcsr (%rax)
+# CHECK-NEXT: 4 12 1.00 * * U maskmovq %mm0, %mm1
+# CHECK-NEXT: 1 4 2.00 maxps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * maxps (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 maxss %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * maxss (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 minps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * minps (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 minss %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * minss (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 movaps %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movaps %xmm0, (%rax)
+# CHECK-NEXT: 1 7 2.00 * movaps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 movhlps %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 movlhps %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movhps %xmm0, (%rax)
+# CHECK-NEXT: 2 8 0.50 * movhps (%rax), %xmm2
+# CHECK-NEXT: 2 12 0.50 * movlps %xmm0, (%rax)
+# CHECK-NEXT: 2 8 0.33 * movlps (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 movmskps %xmm0, %ecx
+# CHECK-NEXT: 2 518 0.50 * movntps %xmm0, (%rax)
+# CHECK-NEXT: 2 511 0.50 * * U movntq %mm0, (%rax)
+# CHECK-NEXT: 1 1 0.25 movss %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movss %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * movss (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 movups %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movups %xmm0, (%rax)
+# CHECK-NEXT: 1 7 2.00 * movups (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 mulps %xmm0, %xmm2
+# CHECK-NEXT: 1 9 2.00 * mulps (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 mulss %xmm0, %xmm2
+# CHECK-NEXT: 1 9 2.00 * mulss (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 orps %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * orps (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 pavgb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pavgb (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pavgw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pavgw (%rax), %mm2
+# CHECK-NEXT: 2 4 0.50 pextrw $1, %mm0, %ecx
+# CHECK-NEXT: 2 4 0.67 pinsrw $1, %eax, %mm2
+# CHECK-NEXT: 2 9 0.33 * pinsrw $1, (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pmaxsw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pmaxsw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pmaxub %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pmaxub (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pminsw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pminsw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pminub %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pminub (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 pmovmskb %mm0, %ecx
+# CHECK-NEXT: 1 5 0.50 pmulhuw %mm0, %mm2
+# CHECK-NEXT: 2 13 0.50 * pmulhuw (%rax), %mm2
+# CHECK-NEXT: 1 0 0.33 * * prefetcht0 (%rax)
+# CHECK-NEXT: 1 0 0.33 * * prefetcht1 (%rax)
+# CHECK-NEXT: 1 0 0.33 * * prefetcht2 (%rax)
+# CHECK-NEXT: 1 0 0.33 * * prefetchnta (%rax)
+# CHECK-NEXT: 1 3 0.50 psadbw %mm0, %mm2
+# CHECK-NEXT: 2 11 0.50 * psadbw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pshufw $1, %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * pshufw $1, (%rax), %mm2
+# CHECK-NEXT: 1 4 2.00 rcpps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * rcpps (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 rcpss %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * rcpss (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 rsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * rsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 rsqrtss %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * rsqrtss (%rax), %xmm2
+# CHECK-NEXT: 2 2 0.50 * * U sfence
+# CHECK-NEXT: 1 1 0.50 shufps $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 7 2.00 * shufps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 10 5.00 sqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1 16 5.00 * sqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 10 5.00 sqrtss %xmm0, %xmm2
+# CHECK-NEXT: 1 16 5.00 * sqrtss (%rax), %xmm2
+# CHECK-NEXT: 4 100 3.00 * U stmxcsr (%rax)
+# CHECK-NEXT: 1 3 0.50 subps %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * subps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.33 subss %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * subss (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 ucomiss %xmm0, %xmm1
+# CHECK-NEXT: 2 9 2.00 * ucomiss (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.50 unpckhps %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * unpckhps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 unpcklps %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * unpcklps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 xorps %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * xorps (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - 0.33 4.67 0.33 4.67 0.33 4.67 5.00 5.00 74.33 74.33 74.33 3.67 3.67 3.67 - 157.25 145.25 15.25 15.25
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 addps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 addps (%rax), %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - addss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 addss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 andnps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 andnps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 andps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 andps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - cmpeqps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - cmpeqps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - cmpeqss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - cmpeqss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - comiss %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - comiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.50 2.50 - - cvtpi2ps %mm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - cvtpi2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.25 2.25 0.25 0.25 cvtps2pi %xmm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 2.67 2.67 2.67 - - - - 2.00 2.00 - - cvtps2pi (%rax), %mm2
+# CHECK-NEXT: - - 1.33 - 1.33 - 1.33 - - - - - - - - - 2.00 2.00 - - cvtsi2ss %ecx, %xmm2
+# CHECK-NEXT: - - 1.33 - 1.33 - 1.33 - - - - - - - - - 2.00 2.00 0.50 0.50 cvtsi2ss %rcx, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 - - cvtss2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 0.50 0.50 cvtss2si %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - 1.33 1.33 1.33 - - - - 3.50 3.50 - - cvtss2si (%rax), %ecx
+# CHECK-NEXT: - - - - - - - - - 1.33 1.33 1.33 - - - - 3.50 3.50 - - cvtss2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.25 2.25 0.25 0.25 cvttps2pi %xmm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 2.67 2.67 2.67 - - - - 2.00 2.00 - - cvttps2pi (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 - - cvttss2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 0.50 0.50 cvttss2si %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - 1.33 1.33 1.33 - - - - 3.50 3.50 - - cvttss2si (%rax), %ecx
+# CHECK-NEXT: - - - - - - - - - 1.33 1.33 1.33 - - - - 3.50 3.50 - - cvttss2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 - - divps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 3.50 3.50 - - divps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 - - divss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 3.50 3.50 - - divss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - 0.33 0.33 0.33 - 0.75 0.75 0.75 0.75 ldmxcsr (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - 1.00 1.00 - - maskmovq %mm0, %mm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - maxps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - maxps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - maxss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - maxss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - minps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - minps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - minss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - minss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - movaps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movaps %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - movaps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 movhlps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 movlhps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movhps %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 movhps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movlps %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 movlps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - movmskps %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movntps %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movntq %mm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 movss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movss %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - movups %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movups %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - movups (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - mulps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - mulps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - mulss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - mulss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 orps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 orps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pavgb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - pavgb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pavgw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - pavgw (%rax), %mm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - 0.50 0.50 pextrw $1, %mm0, %ecx
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - pinsrw $1, %eax, %mm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - pinsrw $1, (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pmaxsw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - pmaxsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pmaxub %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - pmaxub (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pminsw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - pminsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pminub %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - pminub (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pmovmskb %mm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pmulhuw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - pmulhuw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - prefetcht0 (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - prefetcht1 (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - prefetcht2 (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - prefetchnta (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 psadbw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 psadbw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pshufw $1, %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 pshufw $1, (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - rcpps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - rcpps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - rcpss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - rcpss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - rsqrtps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - rsqrtps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - rsqrtss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - rsqrtss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - sfence
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 shufps $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 shufps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 5.00 5.00 - - sqrtps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 5.00 5.00 - - sqrtps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 5.00 5.00 - - sqrtss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 5.00 5.00 - - sqrtss (%rax), %xmm2
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - 0.50 0.50 - - - 0.33 0.33 0.33 - 3.00 3.00 - - stmxcsr (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 subps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 subps (%rax), %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - subss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 subss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - ucomiss %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - ucomiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 unpckhps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 unpckhps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 unpcklps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 unpcklps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 xorps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 xorps (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse2.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse2.s
new file mode 100644
index 0000000000000..bd4faca7391cc
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse2.s
@@ -0,0 +1,972 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+addpd %xmm0, %xmm2
+addpd (%rax), %xmm2
+
+addsd %xmm0, %xmm2
+addsd (%rax), %xmm2
+
+andnpd %xmm0, %xmm2
+andnpd (%rax), %xmm2
+
+andpd %xmm0, %xmm2
+andpd (%rax), %xmm2
+
+clflush (%rax)
+
+cmppd $0, %xmm0, %xmm2
+cmppd $0, (%rax), %xmm2
+
+cmpsd $0, %xmm0, %xmm2
+cmpsd $0, (%rax), %xmm2
+
+comisd %xmm0, %xmm1
+comisd (%rax), %xmm1
+
+cvtdq2pd %xmm0, %xmm2
+cvtdq2pd (%rax), %xmm2
+
+cvtdq2ps %xmm0, %xmm2
+cvtdq2ps (%rax), %xmm2
+
+cvtpd2dq %xmm0, %xmm2
+cvtpd2dq (%rax), %xmm2
+
+cvtpd2pi %xmm0, %mm2
+cvtpd2pi (%rax), %mm2
+
+cvtpd2ps %xmm0, %xmm2
+cvtpd2ps (%rax), %xmm2
+
+cvtpi2pd %mm0, %xmm2
+cvtpi2pd (%rax), %xmm2
+
+cvtps2dq %xmm0, %xmm2
+cvtps2dq (%rax), %xmm2
+
+cvtps2pd %xmm0, %xmm2
+cvtps2pd (%rax), %xmm2
+
+cvtsd2si %xmm0, %ecx
+cvtsd2si %xmm0, %rcx
+cvtsd2si (%rax), %ecx
+cvtsd2si (%rax), %rcx
+
+cvtsd2ss %xmm0, %xmm2
+cvtsd2ss (%rax), %xmm2
+
+cvtsi2sd %ecx, %xmm2
+cvtsi2sd %rcx, %xmm2
+cvtsi2sd (%rax), %xmm2
+cvtsi2sd (%rax), %xmm2
+
+cvtss2sd %xmm0, %xmm2
+cvtss2sd (%rax), %xmm2
+
+cvttpd2dq %xmm0, %xmm2
+cvttpd2dq (%rax), %xmm2
+
+cvttpd2pi %xmm0, %mm2
+cvttpd2pi (%rax), %mm2
+
+cvttps2dq %xmm0, %xmm2
+cvttps2dq (%rax), %xmm2
+
+cvttsd2si %xmm0, %ecx
+cvttsd2si %xmm0, %rcx
+cvttsd2si (%rax), %ecx
+cvttsd2si (%rax), %rcx
+
+divpd %xmm0, %xmm2
+divpd (%rax), %xmm2
+
+divsd %xmm0, %xmm2
+divsd (%rax), %xmm2
+
+lfence
+
+maskmovdqu %xmm0, %xmm1
+
+maxpd %xmm0, %xmm2
+maxpd (%rax), %xmm2
+
+maxsd %xmm0, %xmm2
+maxsd (%rax), %xmm2
+
+mfence
+
+minpd %xmm0, %xmm2
+minpd (%rax), %xmm2
+
+minsd %xmm0, %xmm2
+minsd (%rax), %xmm2
+
+movapd %xmm0, %xmm2
+movapd %xmm0, (%rax)
+movapd (%rax), %xmm2
+
+movd %eax, %xmm2
+movd (%rax), %xmm2
+
+movd %xmm0, %ecx
+movd %xmm0, (%rax)
+
+movdqa %xmm0, %xmm2
+movdqa %xmm0, (%rax)
+movdqa (%rax), %xmm2
+
+movdqu %xmm0, %xmm2
+movdqu %xmm0, (%rax)
+movdqu (%rax), %xmm2
+
+movdq2q %xmm0, %mm2
+
+movhpd %xmm0, (%rax)
+movhpd (%rax), %xmm2
+
+movlpd %xmm0, (%rax)
+movlpd (%rax), %xmm2
+
+movmskpd %xmm0, %rcx
+
+movntil %eax, (%rax)
+movntiq %rax, (%rax)
+
+movntdq %xmm0, (%rax)
+movntpd %xmm0, (%rax)
+
+movq %xmm0, %xmm2
+
+movq %rax, %xmm2
+movq (%rax), %xmm2
+
+movq %xmm0, %rcx
+movq %xmm0, (%rax)
+
+movq2dq %mm0, %xmm2
+
+movsd %xmm0, %xmm2
+movsd %xmm0, (%rax)
+movsd (%rax), %xmm2
+
+movupd %xmm0, %xmm2
+movupd %xmm0, (%rax)
+movupd (%rax), %xmm2
+
+mulpd %xmm0, %xmm2
+mulpd (%rax), %xmm2
+
+mulsd %xmm0, %xmm2
+mulsd (%rax), %xmm2
+
+orpd %xmm0, %xmm2
+orpd (%rax), %xmm2
+
+packssdw %xmm0, %xmm2
+packssdw (%rax), %xmm2
+
+packsswb %xmm0, %xmm2
+packsswb (%rax), %xmm2
+
+packuswb %xmm0, %xmm2
+packuswb (%rax), %xmm2
+
+paddb %xmm0, %xmm2
+paddb (%rax), %xmm2
+
+paddd %xmm0, %xmm2
+paddd (%rax), %xmm2
+
+paddq %mm0, %mm2
+paddq (%rax), %mm2
+
+paddq %xmm0, %xmm2
+paddq (%rax), %xmm2
+
+paddsb %xmm0, %xmm2
+paddsb (%rax), %xmm2
+
+paddsw %xmm0, %xmm2
+paddsw (%rax), %xmm2
+
+paddusb %xmm0, %xmm2
+paddusb (%rax), %xmm2
+
+paddusw %xmm0, %xmm2
+paddusw (%rax), %xmm2
+
+paddw %xmm0, %xmm2
+paddw (%rax), %xmm2
+
+pand %xmm0, %xmm2
+pand (%rax), %xmm2
+
+pandn %xmm0, %xmm2
+pandn (%rax), %xmm2
+
+pavgb %xmm0, %xmm2
+pavgb (%rax), %xmm2
+
+pavgw %xmm0, %xmm2
+pavgw (%rax), %xmm2
+
+pcmpeqb %xmm0, %xmm2
+pcmpeqb (%rax), %xmm2
+
+pcmpeqd %xmm0, %xmm2
+pcmpeqd (%rax), %xmm2
+
+pcmpeqw %xmm0, %xmm2
+pcmpeqw (%rax), %xmm2
+
+pcmpgtb %xmm0, %xmm2
+pcmpgtb (%rax), %xmm2
+
+pcmpgtd %xmm0, %xmm2
+pcmpgtd (%rax), %xmm2
+
+pcmpgtw %xmm0, %xmm2
+pcmpgtw (%rax), %xmm2
+
+pextrw $1, %xmm0, %rcx
+
+pinsrw $1, %rax, %xmm0
+pinsrw $1, (%rax), %xmm0
+
+pmaddwd %xmm0, %xmm2
+pmaddwd (%rax), %xmm2
+
+pmaxsw %xmm0, %xmm2
+pmaxsw (%rax), %xmm2
+
+pmaxub %xmm0, %xmm2
+pmaxub (%rax), %xmm2
+
+pminsw %xmm0, %xmm2
+pminsw (%rax), %xmm2
+
+pminub %xmm0, %xmm2
+pminub (%rax), %xmm2
+
+pmovmskb %xmm0, %rcx
+
+pmulhuw %xmm0, %xmm2
+pmulhuw (%rax), %xmm2
+
+pmulhw %xmm0, %xmm2
+pmulhw (%rax), %xmm2
+
+pmullw %xmm0, %xmm2
+pmullw (%rax), %xmm2
+
+pmuludq %mm0, %mm2
+pmuludq (%rax), %mm2
+
+pmuludq %xmm0, %xmm2
+pmuludq (%rax), %xmm2
+
+por %xmm0, %xmm2
+por (%rax), %xmm2
+
+psadbw %xmm0, %xmm2
+psadbw (%rax), %xmm2
+
+pshufd $1, %xmm0, %xmm2
+pshufd $1, (%rax), %xmm2
+
+pshufhw $1, %xmm0, %xmm2
+pshufhw $1, (%rax), %xmm2
+
+pshuflw $1, %xmm0, %xmm2
+pshuflw $1, (%rax), %xmm2
+
+pslld $1, %xmm2
+pslld %xmm0, %xmm2
+pslld (%rax), %xmm2
+
+pslldq $1, %xmm2
+
+psllq $1, %xmm2
+psllq %xmm0, %xmm2
+psllq (%rax), %xmm2
+
+psllw $1, %xmm2
+psllw %xmm0, %xmm2
+psllw (%rax), %xmm2
+
+psrad $1, %xmm2
+psrad %xmm0, %xmm2
+psrad (%rax), %xmm2
+
+psraw $1, %xmm2
+psraw %xmm0, %xmm2
+psraw (%rax), %xmm2
+
+psrld $1, %xmm2
+psrld %xmm0, %xmm2
+psrld (%rax), %xmm2
+
+psrldq $1, %xmm2
+
+psrlq $1, %xmm2
+psrlq %xmm0, %xmm2
+psrlq (%rax), %xmm2
+
+psrlw $1, %xmm2
+psrlw %xmm0, %xmm2
+psrlw (%rax), %xmm2
+
+psubb %xmm0, %xmm2
+psubb (%rax), %xmm2
+
+psubd %xmm0, %xmm2
+psubd (%rax), %xmm2
+
+psubq %mm0, %mm2
+psubq (%rax), %mm2
+
+psubq %xmm0, %xmm2
+psubq (%rax), %xmm2
+
+psubsb %xmm0, %xmm2
+psubsb (%rax), %xmm2
+
+psubsw %xmm0, %xmm2
+psubsw (%rax), %xmm2
+
+psubusb %xmm0, %xmm2
+psubusb (%rax), %xmm2
+
+psubusw %xmm0, %xmm2
+psubusw (%rax), %xmm2
+
+psubw %xmm0, %xmm2
+psubw (%rax), %xmm2
+
+punpckhbw %xmm0, %xmm2
+punpckhbw (%rax), %xmm2
+
+punpckhdq %xmm0, %xmm2
+punpckhdq (%rax), %xmm2
+
+punpckhqdq %xmm0, %xmm2
+punpckhqdq (%rax), %xmm2
+
+punpckhwd %xmm0, %xmm2
+punpckhwd (%rax), %xmm2
+
+punpcklbw %xmm0, %xmm2
+punpcklbw (%rax), %xmm2
+
+punpckldq %xmm0, %xmm2
+punpckldq (%rax), %xmm2
+
+punpcklqdq %xmm0, %xmm2
+punpcklqdq (%rax), %xmm2
+
+punpcklwd %xmm0, %xmm2
+punpcklwd (%rax), %xmm2
+
+pxor %xmm0, %xmm2
+pxor (%rax), %xmm2
+
+shufpd $1, %xmm0, %xmm2
+shufpd $1, (%rax), %xmm2
+
+sqrtpd %xmm0, %xmm2
+sqrtpd (%rax), %xmm2
+
+sqrtsd %xmm0, %xmm2
+sqrtsd (%rax), %xmm2
+
+subpd %xmm0, %xmm2
+subpd (%rax), %xmm2
+
+subsd %xmm0, %xmm2
+subsd (%rax), %xmm2
+
+ucomisd %xmm0, %xmm1
+ucomisd (%rax), %xmm1
+
+unpckhpd %xmm0, %xmm2
+unpckhpd (%rax), %xmm2
+
+unpcklpd %xmm0, %xmm2
+unpcklpd (%rax), %xmm2
+
+xorpd %xmm0, %xmm2
+xorpd (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 addpd %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * addpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 addsd %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * addsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 andnpd %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * andnpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 andpd %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * andpd (%rax), %xmm2
+# CHECK-NEXT: 4 2 0.50 * * U clflush (%rax)
+# CHECK-NEXT: 1 4 2.00 cmpeqpd %xmm0, %xmm2
+# CHECK-NEXT: 2 10 2.00 * cmpeqpd (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 cmpeqsd %xmm0, %xmm2
+# CHECK-NEXT: 2 10 2.00 * cmpeqsd (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 comisd %xmm0, %xmm1
+# CHECK-NEXT: 2 9 2.00 * comisd (%rax), %xmm1
+# CHECK-NEXT: 2 5 0.50 cvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * cvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 cvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * cvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: 2 5 0.50 cvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 3 12 0.50 * cvtpd2dq (%rax), %xmm2
+# CHECK-NEXT: 2 100 2.00 cvtpd2pi %xmm0, %mm2
+# CHECK-NEXT: 3 13 2.67 * cvtpd2pi (%rax), %mm2
+# CHECK-NEXT: 2 5 0.50 cvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: 3 12 0.50 * cvtpd2ps (%rax), %xmm2
+# CHECK-NEXT: 2 100 2.00 cvtpi2pd %mm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * cvtpi2pd (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 cvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: 2 10 2.00 * cvtps2dq (%rax), %xmm2
+# CHECK-NEXT: 2 5 2.00 cvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * cvtps2pd (%rax), %xmm2
+# CHECK-NEXT: 2 7 3.50 cvtsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 7 3.50 cvtsd2si %xmm0, %rcx
+# CHECK-NEXT: 3 11 3.50 * cvtsd2si (%rax), %ecx
+# CHECK-NEXT: 3 11 3.50 * cvtsd2si (%rax), %rcx
+# CHECK-NEXT: 2 5 0.50 cvtsd2ss %xmm0, %xmm2
+# CHECK-NEXT: 3 11 2.00 * cvtsd2ss (%rax), %xmm2
+# CHECK-NEXT: 2 8 2.00 cvtsi2sd %ecx, %xmm2
+# CHECK-NEXT: 2 8 2.00 cvtsi2sd %rcx, %xmm2
+# CHECK-NEXT: 1 10 2.00 * cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: 1 10 2.00 * cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: 2 5 2.00 cvtss2sd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * cvtss2sd (%rax), %xmm2
+# CHECK-NEXT: 2 5 0.50 cvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 3 12 0.50 * cvttpd2dq (%rax), %xmm2
+# CHECK-NEXT: 2 100 2.00 cvttpd2pi %xmm0, %mm2
+# CHECK-NEXT: 3 13 2.67 * cvttpd2pi (%rax), %mm2
+# CHECK-NEXT: 1 4 2.00 cvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: 2 10 2.00 * cvttps2dq (%rax), %xmm2
+# CHECK-NEXT: 2 7 3.50 cvttsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 7 3.50 cvttsd2si %xmm0, %rcx
+# CHECK-NEXT: 3 11 3.50 * cvttsd2si (%rax), %ecx
+# CHECK-NEXT: 3 11 3.50 * cvttsd2si (%rax), %rcx
+# CHECK-NEXT: 1 10 5.00 divpd %xmm0, %xmm2
+# CHECK-NEXT: 1 16 5.00 * divpd (%rax), %xmm2
+# CHECK-NEXT: 1 10 5.00 divsd %xmm0, %xmm2
+# CHECK-NEXT: 2 20 0.50 * divsd (%rax), %xmm2
+# CHECK-NEXT: 2 2 0.50 * * U lfence
+# CHECK-NEXT: 2 1 0.50 * * U maskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: 1 4 2.00 maxpd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * maxpd (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 maxsd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * maxsd (%rax), %xmm2
+# CHECK-NEXT: 2 3 0.50 * * U mfence
+# CHECK-NEXT: 1 4 2.00 minpd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * minpd (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 minsd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * minsd (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 movapd %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movapd %xmm0, (%rax)
+# CHECK-NEXT: 1 7 2.00 * movapd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.33 movd %eax, %xmm2
+# CHECK-NEXT: 1 6 0.33 * movd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 movd %xmm0, %ecx
+# CHECK-NEXT: 2 12 0.50 * movd %xmm0, (%rax)
+# CHECK-NEXT: 2 1 0.50 movdqa %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movdqa %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * movdqa (%rax), %xmm2
+# CHECK-NEXT: 2 1 0.50 movdqu %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movdqu %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * movdqu (%rax), %xmm2
+# CHECK-NEXT: 2 3 0.50 movdq2q %xmm0, %mm2
+# CHECK-NEXT: 2 12 0.50 * movhpd %xmm0, (%rax)
+# CHECK-NEXT: 2 8 0.50 * movhpd (%rax), %xmm2
+# CHECK-NEXT: 2 12 0.50 * movlpd %xmm0, (%rax)
+# CHECK-NEXT: 2 8 0.33 * movlpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 movmskpd %xmm0, %ecx
+# CHECK-NEXT: 2 518 0.50 * movntil %eax, (%rax)
+# CHECK-NEXT: 2 512 0.50 * movntiq %rax, (%rax)
+# CHECK-NEXT: 2 512 0.50 * movntdq %xmm0, (%rax)
+# CHECK-NEXT: 2 518 0.50 * movntpd %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.25 movq %xmm0, %xmm2
+# CHECK-NEXT: 1 3 0.33 movq %rax, %xmm2
+# CHECK-NEXT: 1 6 0.33 * movq (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 movq %xmm0, %rcx
+# CHECK-NEXT: 2 12 0.50 * movq %xmm0, (%rax)
+# CHECK-NEXT: 2 3 0.50 movq2dq %mm0, %xmm2
+# CHECK-NEXT: 1 1 0.25 movsd %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movsd %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * movsd (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 movupd %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movupd %xmm0, (%rax)
+# CHECK-NEXT: 1 7 2.00 * movupd (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 mulpd %xmm0, %xmm2
+# CHECK-NEXT: 1 9 2.00 * mulpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 mulsd %xmm0, %xmm2
+# CHECK-NEXT: 1 9 2.00 * mulsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 orpd %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * orpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 packssdw %xmm0, %xmm2
+# CHECK-NEXT: 1 9 2.00 * packssdw (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 packsswb %xmm0, %xmm2
+# CHECK-NEXT: 1 9 2.00 * packsswb (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 packuswb %xmm0, %xmm2
+# CHECK-NEXT: 1 9 2.00 * packuswb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddb %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * paddb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddd %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * paddd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 paddq %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * paddq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddq %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * paddq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 paddsb %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * paddsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 paddsw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * paddsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 paddusb %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * paddusb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 paddusw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * paddusw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * paddw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pand %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pand (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pandn %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pandn (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pavgb %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pavgb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pavgw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pavgw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpeqb %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pcmpeqb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpeqd %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pcmpeqd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpeqw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pcmpeqw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpgtb %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pcmpgtb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpgtd %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pcmpgtd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpgtw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pcmpgtw (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.50 pextrw $1, %xmm0, %ecx
+# CHECK-NEXT: 2 5 1.33 pinsrw $1, %eax, %xmm0
+# CHECK-NEXT: 2 7 2.00 * pinsrw $1, (%rax), %xmm0
+# CHECK-NEXT: 1 4 2.00 pmaddwd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * pmaddwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmaxsw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pmaxsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmaxub %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pmaxub (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pminsw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pminsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pminub %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pminub (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 pmovmskb %xmm0, %ecx
+# CHECK-NEXT: 1 4 2.00 pmulhuw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * pmulhuw (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 pmulhw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * pmulhw (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 pmullw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * pmullw (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.50 pmuludq %mm0, %mm2
+# CHECK-NEXT: 2 13 0.50 * pmuludq (%rax), %mm2
+# CHECK-NEXT: 1 3 1.50 pmuludq %xmm0, %xmm2
+# CHECK-NEXT: 1 9 2.00 * pmuludq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 por %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * por (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 psadbw %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * psadbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 7 2.00 * pshufd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 7 2.00 * pshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 7 2.00 * pshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pslld $1, %xmm2
+# CHECK-NEXT: 2 2 0.50 pslld %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pslld (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pslldq $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psllq $1, %xmm2
+# CHECK-NEXT: 2 2 0.50 psllq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psllq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psllw $1, %xmm2
+# CHECK-NEXT: 2 2 0.50 psllw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psllw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psrad $1, %xmm2
+# CHECK-NEXT: 2 2 0.50 psrad %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psrad (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psraw $1, %xmm2
+# CHECK-NEXT: 2 2 0.50 psraw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psraw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psrld $1, %xmm2
+# CHECK-NEXT: 2 2 0.50 psrld %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psrld (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psrldq $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psrlq $1, %xmm2
+# CHECK-NEXT: 2 2 0.50 psrlq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psrlq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psrlw $1, %xmm2
+# CHECK-NEXT: 2 2 0.50 psrlw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psrlw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubb %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * psubb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubd %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * psubd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 psubq %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * psubq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubq %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * psubq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psubsb %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * psubsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psubsw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * psubsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psubusb %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * psubusb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psubusw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * psubusw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * psubw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhbw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * punpckhbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhdq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * punpckhdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhqdq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * punpckhqdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhwd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * punpckhwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpcklbw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * punpcklbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckldq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * punpckldq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpcklqdq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * punpcklqdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpcklwd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * punpcklwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pxor %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pxor (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 shufpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 7 2.00 * shufpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 15 7.50 sqrtpd %xmm0, %xmm2
+# CHECK-NEXT: 1 21 7.50 * sqrtpd (%rax), %xmm2
+# CHECK-NEXT: 1 15 7.50 sqrtsd %xmm0, %xmm2
+# CHECK-NEXT: 2 24 1.00 * sqrtsd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 subpd %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * subpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 subsd %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * subsd (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 ucomisd %xmm0, %xmm1
+# CHECK-NEXT: 2 9 2.00 * ucomisd (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.50 unpckhpd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * unpckhpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 unpcklpd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * unpcklpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 xorpd %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * xorpd (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: 1.00 0.50 5.50 0.50 5.50 0.50 5.50 8.50 8.50 166.33 166.33 166.33 5.33 5.33 5.33 - 216.25 216.25 53.75 53.75
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 addpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 addpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 addsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 addsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 andnpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 andnpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 andpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 andpd (%rax), %xmm2
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - clflush (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - cmpeqpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - cmpeqpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - cmpeqsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - cmpeqsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - comisd %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - comisd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 cvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - cvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - cvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - cvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 cvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 cvtpd2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 0.50 0.50 cvtpd2pi %xmm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 2.67 2.67 2.67 - - - - 2.00 2.00 0.50 0.50 cvtpd2pi (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 cvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 cvtpd2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 0.50 0.50 cvtpi2pd %mm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - cvtpi2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - cvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - cvtps2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 0.50 0.50 cvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - cvtps2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 - - cvtsd2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 - - cvtsd2si %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - 1.33 1.33 1.33 - - - - 3.50 3.50 - - cvtsd2si (%rax), %ecx
+# CHECK-NEXT: - - - - - - - - - 1.33 1.33 1.33 - - - - 3.50 3.50 - - cvtsd2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 cvtsd2ss %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 0.50 0.50 cvtsd2ss (%rax), %xmm2
+# CHECK-NEXT: - - 1.33 - 1.33 - 1.33 - - - - - - - - - 2.00 2.00 - - cvtsi2sd %ecx, %xmm2
+# CHECK-NEXT: - - 1.33 - 1.33 - 1.33 - - - - - - - - - 2.00 2.00 - - cvtsi2sd %rcx, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 0.50 0.50 cvtss2sd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - cvtss2sd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 cvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 cvttpd2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 0.50 0.50 cvttpd2pi %xmm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 2.67 2.67 2.67 - - - - 2.00 2.00 0.50 0.50 cvttpd2pi (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - cvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - cvttps2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 - - cvttsd2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 3.50 3.50 - - cvttsd2si %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - - - 1.33 1.33 1.33 - - - - 3.50 3.50 - - cvttsd2si (%rax), %ecx
+# CHECK-NEXT: - - - - - - - - - 1.33 1.33 1.33 - - - - 3.50 3.50 - - cvttsd2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 5.00 5.00 - - divpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 5.00 5.00 - - divpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 5.00 5.00 - - divsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 divsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - lfence
+# CHECK-NEXT: - - - - - - - 0.50 0.50 0.33 0.33 0.33 - - - - - - - - maskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - maxpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - maxpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - maxsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - maxsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - mfence
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - minpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - minpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - minsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - minsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - movapd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movapd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - movapd (%rax), %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - movd %eax, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - movd %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 movdqa %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movdqa %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movdqa (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 movdqu %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movdqu %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movdqu (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.75 0.75 0.25 0.25 movdq2q %xmm0, %mm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movhpd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 movhpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movlpd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 movlpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - movmskpd %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movntil %eax, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movntiq %rax, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movntdq %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movntpd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 movq %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - movq %rax, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - movq %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movq %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.75 0.75 0.25 0.25 movq2dq %mm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 movsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movsd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - movupd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - movupd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - movupd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - mulpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - mulpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - mulsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - mulsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 orpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 orpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.50 1.50 packssdw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 1.50 1.50 packssdw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.50 1.50 packsswb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 1.50 1.50 packsswb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.50 1.50 packuswb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 1.50 1.50 packuswb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 paddb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 paddb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 paddd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 paddd (%rax), %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - paddq %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - paddq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 paddq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 paddq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - paddsb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - paddsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - paddsw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - paddsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - paddusb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - paddusb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - paddusw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - paddusw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 paddw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 paddw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 pand %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 pand (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 pandn %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 pandn (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pavgb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pavgb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pavgw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pavgw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pcmpeqb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pcmpeqb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pcmpeqd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pcmpeqd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pcmpeqw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pcmpeqw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pcmpgtb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pcmpgtb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pcmpgtd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pcmpgtd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pcmpgtw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pcmpgtw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 0.50 0.50 pextrw $1, %xmm0, %ecx
+# CHECK-NEXT: - - 1.33 - 1.33 - 1.33 - - - - - - - - - - - 0.50 0.50 pinsrw $1, %eax, %xmm0
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 pinsrw $1, (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - pmaddwd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - pmaddwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pmaxsw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pmaxsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pmaxub %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pmaxub (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pminsw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pminsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pminub %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pminub (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - pmovmskb %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - pmulhuw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - pmulhuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - pmulhw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - pmulhw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - pmullw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - pmullw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pmuludq %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - pmuludq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - pmuludq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - pmuludq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 por %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 por (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 psadbw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 psadbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 pshufd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 pshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 pshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pslld $1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 pslld %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - pslld (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pslldq $1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psllq $1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 psllq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psllq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psllw $1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 psllw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psllw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psrad $1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 psrad %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psrad (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psraw $1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 psraw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psraw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psrld $1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 psrld %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psrld (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 psrldq $1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psrlq $1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 psrlq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psrlq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psrlw $1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 psrlw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psrlw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 psubb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 psubb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 psubd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 psubd (%rax), %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - psubq %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - psubq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 psubq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 psubq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psubsb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - psubsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psubsw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - psubsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psubusb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - psubusb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psubusw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - psubusw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 psubw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 psubw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 punpckhbw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 punpckhbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 punpckhdq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 punpckhdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 punpckhqdq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 punpckhqdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 punpckhwd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 punpckhwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 punpcklbw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 punpcklbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 punpckldq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 punpckldq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 punpcklqdq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 punpcklqdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 punpcklwd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 punpcklwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 pxor %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 pxor (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 shufpd $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 shufpd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 7.50 7.50 - - sqrtpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 7.50 7.50 - - sqrtpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 7.50 7.50 - - sqrtsd %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - 0.33 0.33 0.33 - - - - - - - - sqrtsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 subpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 subpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 subsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 subsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 - - ucomisd %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 - - ucomisd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 unpckhpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 unpckhpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 unpcklpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 unpcklpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 xorpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 xorpd (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse3.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse3.s
new file mode 100644
index 0000000000000..26b7337c979d5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse3.s
@@ -0,0 +1,116 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+addsubpd %xmm0, %xmm2
+addsubpd (%rax), %xmm2
+
+addsubps %xmm0, %xmm2
+addsubps (%rax), %xmm2
+
+haddpd %xmm0, %xmm2
+haddpd (%rax), %xmm2
+
+haddps %xmm0, %xmm2
+haddps (%rax), %xmm2
+
+hsubpd %xmm0, %xmm2
+hsubpd (%rax), %xmm2
+
+hsubps %xmm0, %xmm2
+hsubps (%rax), %xmm2
+
+lddqu (%rax), %xmm2
+
+monitor
+
+movddup %xmm0, %xmm2
+movddup (%rax), %xmm2
+
+movshdup %xmm0, %xmm2
+movshdup (%rax), %xmm2
+
+movsldup %xmm0, %xmm2
+movsldup (%rax), %xmm2
+
+mwait
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 addsubpd %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * addsubpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 addsubps %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * addsubps (%rax), %xmm2
+# CHECK-NEXT: 3 4 2.50 haddpd %xmm0, %xmm2
+# CHECK-NEXT: 4 10 2.50 * haddpd (%rax), %xmm2
+# CHECK-NEXT: 3 4 2.50 haddps %xmm0, %xmm2
+# CHECK-NEXT: 4 10 2.50 * haddps (%rax), %xmm2
+# CHECK-NEXT: 3 4 2.50 hsubpd %xmm0, %xmm2
+# CHECK-NEXT: 4 10 2.50 * hsubpd (%rax), %xmm2
+# CHECK-NEXT: 3 4 2.50 hsubps %xmm0, %xmm2
+# CHECK-NEXT: 4 10 2.50 * hsubps (%rax), %xmm2
+# CHECK-NEXT: 1 6 0.33 * lddqu (%rax), %xmm2
+# CHECK-NEXT: 1 100 0.17 U monitor
+# CHECK-NEXT: 1 1 0.50 movddup %xmm0, %xmm2
+# CHECK-NEXT: 1 6 2.00 * movddup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 movshdup %xmm0, %xmm2
+# CHECK-NEXT: 1 6 2.00 * movshdup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 movsldup %xmm0, %xmm2
+# CHECK-NEXT: 1 6 2.00 * movsldup (%rax), %xmm2
+# CHECK-NEXT: 1 100 0.17 * * U mwait
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 - - 15.00 15.00 15.00 - - - - - - 23.50 23.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 addsubpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 addsubpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 addsubps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 addsubps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.50 2.50 haddpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 2.50 2.50 haddpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.50 2.50 haddps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 2.50 2.50 haddps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.50 2.50 hsubpd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 2.50 2.50 hsubpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.50 2.50 hsubps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 2.50 2.50 hsubps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - lddqu (%rax), %xmm2
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - monitor
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 movddup %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - movddup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 movshdup %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - movshdup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 movsldup %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - - - movsldup (%rax), %xmm2
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - mwait
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse41.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse41.s
new file mode 100644
index 0000000000000..3c1404e9252d4
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse41.s
@@ -0,0 +1,378 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+blendpd $11, %xmm0, %xmm2
+blendpd $11, (%rax), %xmm2
+
+blendps $11, %xmm0, %xmm2
+blendps $11, (%rax), %xmm2
+
+blendvpd %xmm0, %xmm2
+blendvpd (%rax), %xmm2
+
+blendvps %xmm0, %xmm2
+blendvps (%rax), %xmm2
+
+dppd $22, %xmm0, %xmm2
+dppd $22, (%rax), %xmm2
+
+dpps $22, %xmm0, %xmm2
+dpps $22, (%rax), %xmm2
+
+extractps $1, %xmm0, %rcx
+extractps $1, %xmm0, (%rax)
+
+insertps $1, %xmm0, %xmm2
+insertps $1, (%rax), %xmm2
+
+movntdqa (%rax), %xmm2
+
+mpsadbw $1, %xmm0, %xmm2
+mpsadbw $1, (%rax), %xmm2
+
+packusdw %xmm0, %xmm2
+packusdw (%rax), %xmm2
+
+pblendvb %xmm0, %xmm2
+pblendvb (%rax), %xmm2
+
+pblendw $11, %xmm0, %xmm2
+pblendw $11, (%rax), %xmm2
+
+pcmpeqq %xmm0, %xmm2
+pcmpeqq (%rax), %xmm2
+
+pextrb $1, %xmm0, %ecx
+pextrb $1, %xmm0, (%rax)
+
+pextrd $1, %xmm0, %ecx
+pextrd $1, %xmm0, (%rax)
+
+pextrq $1, %xmm0, %rcx
+pextrq $1, %xmm0, (%rax)
+
+pextrw $1, %xmm0, (%rax)
+
+phminposuw %xmm0, %xmm2
+phminposuw (%rax), %xmm2
+
+pinsrb $1, %eax, %xmm1
+pinsrb $1, (%rax), %xmm1
+
+pinsrd $1, %eax, %xmm1
+pinsrd $1, (%rax), %xmm1
+
+pinsrq $1, %rax, %xmm1
+pinsrq $1, (%rax), %xmm1
+
+pmaxsb %xmm0, %xmm2
+pmaxsb (%rax), %xmm2
+
+pmaxsd %xmm0, %xmm2
+pmaxsd (%rax), %xmm2
+
+pmaxud %xmm0, %xmm2
+pmaxud (%rax), %xmm2
+
+pmaxuw %xmm0, %xmm2
+pmaxuw (%rax), %xmm2
+
+pminsb %xmm0, %xmm2
+pminsb (%rax), %xmm2
+
+pminsd %xmm0, %xmm2
+pminsd (%rax), %xmm2
+
+pminud %xmm0, %xmm2
+pminud (%rax), %xmm2
+
+pminuw %xmm0, %xmm2
+pminuw (%rax), %xmm2
+
+pmovsxbd %xmm0, %xmm2
+pmovsxbd (%rax), %xmm2
+
+pmovsxbq %xmm0, %xmm2
+pmovsxbq (%rax), %xmm2
+
+pmovsxbw %xmm0, %xmm2
+pmovsxbw (%rax), %xmm2
+
+pmovsxdq %xmm0, %xmm2
+pmovsxdq (%rax), %xmm2
+
+pmovsxwd %xmm0, %xmm2
+pmovsxwd (%rax), %xmm2
+
+pmovsxwq %xmm0, %xmm2
+pmovsxwq (%rax), %xmm2
+
+pmovzxbd %xmm0, %xmm2
+pmovzxbd (%rax), %xmm2
+
+pmovzxbq %xmm0, %xmm2
+pmovzxbq (%rax), %xmm2
+
+pmovzxbw %xmm0, %xmm2
+pmovzxbw (%rax), %xmm2
+
+pmovzxdq %xmm0, %xmm2
+pmovzxdq (%rax), %xmm2
+
+pmovzxwd %xmm0, %xmm2
+pmovzxwd (%rax), %xmm2
+
+pmovzxwq %xmm0, %xmm2
+pmovzxwq (%rax), %xmm2
+
+pmuldq %xmm0, %xmm2
+pmuldq (%rax), %xmm2
+
+pmulld %xmm0, %xmm2
+pmulld (%rax), %xmm2
+
+ptest %xmm0, %xmm1
+ptest (%rax), %xmm1
+
+roundpd $1, %xmm0, %xmm2
+roundpd $1, (%rax), %xmm2
+
+roundps $1, %xmm0, %xmm2
+roundps $1, (%rax), %xmm2
+
+roundsd $1, %xmm0, %xmm2
+roundsd $1, (%rax), %xmm2
+
+roundss $1, %xmm0, %xmm2
+roundss $1, (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 blendpd $11, %xmm0, %xmm2
+# CHECK-NEXT: 2 7 2.00 * blendpd $11, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 blendps $11, %xmm0, %xmm2
+# CHECK-NEXT: 2 7 2.00 * blendps $11, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 blendvpd %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * blendvpd %xmm0, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 blendvps %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * blendvps %xmm0, (%rax), %xmm2
+# CHECK-NEXT: 3 8 1.00 dppd $22, %xmm0, %xmm2
+# CHECK-NEXT: 4 13 1.00 * dppd $22, (%rax), %xmm2
+# CHECK-NEXT: 5 11 1.50 dpps $22, %xmm0, %xmm2
+# CHECK-NEXT: 6 18 1.50 * dpps $22, (%rax), %xmm2
+# CHECK-NEXT: 2 4 0.50 extractps $1, %xmm0, %ecx
+# CHECK-NEXT: 3 12 0.50 * extractps $1, %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.50 insertps $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * insertps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 7 0.33 * movntdqa (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 mpsadbw $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 11 1.00 * mpsadbw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 packusdw %xmm0, %xmm2
+# CHECK-NEXT: 1 9 2.00 * packusdw (%rax), %xmm2
+# CHECK-NEXT: 3 3 0.75 pblendvb %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 4 8 2.00 * pblendvb %xmm0, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pblendw $11, %xmm0, %xmm2
+# CHECK-NEXT: 2 7 2.00 * pblendw $11, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpeqq %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pcmpeqq (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.50 pextrb $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 0.50 * pextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 4 1.50 pextrd $1, %xmm0, %ecx
+# CHECK-NEXT: 3 12 0.50 * pextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 4 1.50 pextrq $1, %xmm0, %rcx
+# CHECK-NEXT: 3 12 0.50 * pextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 2 0.50 * pextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: 1 5 0.50 phminposuw %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * phminposuw (%rax), %xmm2
+# CHECK-NEXT: 2 5 1.33 pinsrb $1, %eax, %xmm1
+# CHECK-NEXT: 2 7 2.00 * pinsrb $1, (%rax), %xmm1
+# CHECK-NEXT: 2 5 1.33 pinsrd $1, %eax, %xmm1
+# CHECK-NEXT: 2 7 2.00 * pinsrd $1, (%rax), %xmm1
+# CHECK-NEXT: 2 5 1.33 pinsrq $1, %rax, %xmm1
+# CHECK-NEXT: 2 7 2.00 * pinsrq $1, (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.50 pmaxsb %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pmaxsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmaxsd %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pmaxsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmaxud %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pmaxud (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmaxuw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pmaxuw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pminsb %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pminsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pminsd %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pminsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pminud %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pminud (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pminuw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pminuw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovsxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovsxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovsxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovsxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovsxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovsxwq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovzxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovzxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovzxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovzxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovzxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovzxwq (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 pmuldq %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * pmuldq (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 pmulld %xmm0, %xmm2
+# CHECK-NEXT: 3 18 0.50 * pmulld (%rax), %xmm2
+# CHECK-NEXT: 2 4 0.50 ptest %xmm0, %xmm1
+# CHECK-NEXT: 3 10 2.00 * ptest (%rax), %xmm1
+# CHECK-NEXT: 2 8 4.00 roundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 14 4.00 * roundpd $1, (%rax), %xmm2
+# CHECK-NEXT: 2 8 4.00 roundps $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 14 4.00 * roundps $1, (%rax), %xmm2
+# CHECK-NEXT: 2 8 4.00 roundsd $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 14 4.00 * roundsd $1, (%rax), %xmm2
+# CHECK-NEXT: 2 8 4.00 roundss $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 14 4.00 * roundss $1, (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - - 4.67 - 4.67 - 4.67 2.50 2.50 53.00 53.00 53.00 1.67 1.67 1.67 - 62.50 62.50 35.00 35.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 blendpd $11, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 blendpd $11, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 blendps $11, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 blendps $11, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 blendvpd %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 blendvpd %xmm0, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 blendvps %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 blendvps %xmm0, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 1.00 0.50 0.50 dppd $22, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 1.00 0.50 0.50 dppd $22, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 1.50 1.50 dpps $22, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.50 1.50 1.50 1.50 dpps $22, (%rax), %xmm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - 0.50 0.50 extractps $1, %xmm0, %ecx
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - extractps $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 insertps $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 insertps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movntdqa (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 1.00 mpsadbw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 1.00 1.00 mpsadbw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.50 1.50 packusdw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 1.50 1.50 packusdw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.75 0.75 0.75 0.75 pblendvb %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.75 0.75 0.75 0.75 pblendvb %xmm0, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 pblendw $11, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.25 0.25 0.25 0.25 pblendw $11, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pcmpeqq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pcmpeqq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 0.50 0.50 pextrb $1, %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - 0.50 0.50 pextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 0.50 0.50 pextrd $1, %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - 0.50 0.50 pextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.50 1.50 0.50 0.50 pextrq $1, %xmm0, %rcx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - 0.50 0.50 pextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - 0.50 0.50 pextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - phminposuw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - phminposuw (%rax), %xmm2
+# CHECK-NEXT: - - 1.33 - 1.33 - 1.33 - - - - - - - - - - - 0.50 0.50 pinsrb $1, %eax, %xmm1
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 pinsrb $1, (%rax), %xmm1
+# CHECK-NEXT: - - 1.33 - 1.33 - 1.33 - - - - - - - - - - - 0.50 0.50 pinsrd $1, %eax, %xmm1
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 pinsrd $1, (%rax), %xmm1
+# CHECK-NEXT: - - 1.33 - 1.33 - 1.33 - - - - - - - - - - - 0.50 0.50 pinsrq $1, %rax, %xmm1
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 pinsrq $1, (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pmaxsb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pmaxsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pmaxsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pmaxsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pmaxud %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pmaxud (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pmaxuw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pmaxuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pminsb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pminsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pminsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pminsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pminud %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pminud (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pminuw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pminuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 pmovsxbd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 pmovsxbq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 pmovsxbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 pmovsxdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 pmovsxwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 pmovsxwq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 pmovzxbd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 pmovzxbq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 pmovzxbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 pmovzxdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 pmovzxwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 pmovzxwq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - pmuldq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - pmuldq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 pmulld %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 pmulld (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 ptest %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 1.50 1.50 0.50 0.50 ptest (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 4.00 - - roundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 4.00 4.00 - - roundpd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 4.00 - - roundps $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 4.00 4.00 - - roundps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 4.00 - - roundsd $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 4.00 4.00 - - roundsd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 4.00 - - roundss $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 4.00 4.00 - - roundss $1, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse42.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse42.s
new file mode 100644
index 0000000000000..8c9fe99ba3c57
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-sse42.s
@@ -0,0 +1,111 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+crc32b %al, %ecx
+crc32b (%rax), %ecx
+
+crc32l %eax, %ecx
+crc32l (%rax), %ecx
+
+crc32w %ax, %ecx
+crc32w (%rax), %ecx
+
+crc32b %al, %rcx
+crc32b (%rax), %rcx
+
+crc32q %rax, %rcx
+crc32q (%rax), %rcx
+
+pcmpestri $1, %xmm0, %xmm2
+pcmpestri $1, (%rax), %xmm2
+
+pcmpestrm $1, %xmm0, %xmm2
+pcmpestrm $1, (%rax), %xmm2
+
+pcmpistri $1, %xmm0, %xmm2
+pcmpistri $1, (%rax), %xmm2
+
+pcmpistrm $1, %xmm0, %xmm2
+pcmpistrm $1, (%rax), %xmm2
+
+pcmpgtq %xmm0, %xmm2
+pcmpgtq (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 crc32b %al, %ecx
+# CHECK-NEXT: 1 7 1.33 * crc32b (%rax), %ecx
+# CHECK-NEXT: 1 3 1.00 crc32l %eax, %ecx
+# CHECK-NEXT: 1 7 1.33 * crc32l (%rax), %ecx
+# CHECK-NEXT: 1 3 1.00 crc32w %ax, %ecx
+# CHECK-NEXT: 1 7 1.33 * crc32w (%rax), %ecx
+# CHECK-NEXT: 1 3 1.00 crc32b %al, %rcx
+# CHECK-NEXT: 1 7 1.33 * crc32b (%rax), %rcx
+# CHECK-NEXT: 1 3 1.00 crc32q %rax, %rcx
+# CHECK-NEXT: 1 7 1.33 * crc32q (%rax), %rcx
+# CHECK-NEXT: 8 16 3.00 pcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 31 3.00 * pcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: 9 16 3.00 pcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 9 17 3.00 * pcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: 3 11 3.00 pcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: 4 31 3.00 * pcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: 3 11 3.00 pcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 4 15 3.00 * pcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.50 pcmpgtq %xmm0, %xmm2
+# CHECK-NEXT: 1 9 2.00 * pcmpgtq (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - 25.67 15.00 1.67 15.00 1.67 15.00 - - 10.00 10.00 10.00 - - - - - - 3.00 3.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - - - - - - - - - - - - crc32b %al, %ecx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - 1.33 1.33 1.33 - - - - - - - - crc32b (%rax), %ecx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - - - - - - - - - - - - crc32l %eax, %ecx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - 1.33 1.33 1.33 - - - - - - - - crc32l (%rax), %ecx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - - - - - - - - - - - - crc32w %ax, %ecx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - 1.33 1.33 1.33 - - - - - - - - crc32w (%rax), %ecx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - - - - - - - - - - - - crc32b %al, %rcx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - 1.33 1.33 1.33 - - - - - - - - crc32b (%rax), %rcx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - - - - - - - - - - - - crc32q %rax, %rcx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - 1.33 1.33 1.33 - - - - - - - - crc32q (%rax), %rcx
+# CHECK-NEXT: - 3.67 1.00 0.67 1.00 0.67 1.00 - - - - - - - - - - - - - pcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: - 3.17 1.17 0.17 1.17 0.17 1.17 - - 0.33 0.33 0.33 - - - - - - - - pcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: - 3.50 1.50 0.50 1.50 0.50 1.50 - - - - - - - - - - - - - pcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: - 3.33 1.33 0.33 1.33 0.33 1.33 - - 0.33 0.33 0.33 - - - - - - - - pcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: - 3.00 - - - - - - - - - - - - - - - - - - pcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: - 3.00 - - - - - - - 0.33 0.33 0.33 - - - - - - - - pcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: - 3.00 - - - - - - - - - - - - - - - - - - pcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: - 3.00 - - - - - - - 0.33 0.33 0.33 - - - - - - - - pcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.50 1.50 pcmpgtq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 1.50 1.50 pcmpgtq (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-ssse3.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-ssse3.s
new file mode 100644
index 0000000000000..4ce11e6eb8b1c
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-ssse3.s
@@ -0,0 +1,265 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+pabsb %mm0, %mm2
+pabsb (%rax), %mm2
+
+pabsb %xmm0, %xmm2
+pabsb (%rax), %xmm2
+
+pabsd %mm0, %mm2
+pabsd (%rax), %mm2
+
+pabsd %xmm0, %xmm2
+pabsd (%rax), %xmm2
+
+pabsw %mm0, %mm2
+pabsw (%rax), %mm2
+
+pabsw %xmm0, %xmm2
+pabsw (%rax), %xmm2
+
+palignr $1, %mm0, %mm2
+palignr $1, (%rax), %mm2
+
+palignr $1, %xmm0, %xmm2
+palignr $1, (%rax), %xmm2
+
+phaddd %mm0, %mm2
+phaddd (%rax), %mm2
+
+phaddd %xmm0, %xmm2
+phaddd (%rax), %xmm2
+
+phaddsw %mm0, %mm2
+phaddsw (%rax), %mm2
+
+phaddsw %xmm0, %xmm2
+phaddsw (%rax), %xmm2
+
+phaddw %mm0, %mm2
+phaddw (%rax), %mm2
+
+phaddw %xmm0, %xmm2
+phaddw (%rax), %xmm2
+
+phsubd %mm0, %mm2
+phsubd (%rax), %mm2
+
+phsubd %xmm0, %xmm2
+phsubd (%rax), %xmm2
+
+phsubsw %mm0, %mm2
+phsubsw (%rax), %mm2
+
+phsubsw %xmm0, %xmm2
+phsubsw (%rax), %xmm2
+
+phsubw %mm0, %mm2
+phsubw (%rax), %mm2
+
+phsubw %xmm0, %xmm2
+phsubw (%rax), %xmm2
+
+pmaddubsw %mm0, %mm2
+pmaddubsw (%rax), %mm2
+
+pmaddubsw %xmm0, %xmm2
+pmaddubsw (%rax), %xmm2
+
+pmulhrsw %mm0, %mm2
+pmulhrsw (%rax), %mm2
+
+pmulhrsw %xmm0, %xmm2
+pmulhrsw (%rax), %xmm2
+
+pshufb %mm0, %mm2
+pshufb (%rax), %mm2
+
+pshufb %xmm0, %xmm2
+pshufb (%rax), %xmm2
+
+psignb %mm0, %mm2
+psignb (%rax), %mm2
+
+psignb %xmm0, %xmm2
+psignb (%rax), %xmm2
+
+psignd %mm0, %mm2
+psignd (%rax), %mm2
+
+psignd %xmm0, %xmm2
+psignd (%rax), %xmm2
+
+psignw %mm0, %mm2
+psignw (%rax), %mm2
+
+psignw %xmm0, %xmm2
+psignw (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 pabsb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pabsb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pabsb %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pabsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 pabsd %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pabsd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pabsd %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pabsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 pabsw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pabsw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pabsw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * pabsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 palignr $1, %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * palignr $1, (%rax), %mm2
+# CHECK-NEXT: 1 1 0.33 palignr $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 7 2.00 * palignr $1, (%rax), %xmm2
+# CHECK-NEXT: 3 3 1.00 phaddd %mm0, %mm2
+# CHECK-NEXT: 4 11 1.00 * phaddd (%rax), %mm2
+# CHECK-NEXT: 3 2 1.00 phaddd %xmm0, %xmm2
+# CHECK-NEXT: 4 9 1.00 * phaddd (%rax), %xmm2
+# CHECK-NEXT: 3 3 0.67 phaddsw %mm0, %mm2
+# CHECK-NEXT: 4 11 0.67 * phaddsw (%rax), %mm2
+# CHECK-NEXT: 3 2 1.00 phaddsw %xmm0, %xmm2
+# CHECK-NEXT: 4 9 1.00 * phaddsw (%rax), %xmm2
+# CHECK-NEXT: 3 3 1.00 phaddw %mm0, %mm2
+# CHECK-NEXT: 4 11 1.00 * phaddw (%rax), %mm2
+# CHECK-NEXT: 3 2 1.00 phaddw %xmm0, %xmm2
+# CHECK-NEXT: 4 9 1.00 * phaddw (%rax), %xmm2
+# CHECK-NEXT: 3 3 1.00 phsubd %mm0, %mm2
+# CHECK-NEXT: 4 11 1.00 * phsubd (%rax), %mm2
+# CHECK-NEXT: 3 2 1.00 phsubd %xmm0, %xmm2
+# CHECK-NEXT: 4 9 1.00 * phsubd (%rax), %xmm2
+# CHECK-NEXT: 3 3 0.67 phsubsw %mm0, %mm2
+# CHECK-NEXT: 4 11 0.67 * phsubsw (%rax), %mm2
+# CHECK-NEXT: 3 2 1.00 phsubsw %xmm0, %xmm2
+# CHECK-NEXT: 4 9 1.00 * phsubsw (%rax), %xmm2
+# CHECK-NEXT: 3 3 1.00 phsubw %mm0, %mm2
+# CHECK-NEXT: 4 11 1.00 * phsubw (%rax), %mm2
+# CHECK-NEXT: 3 2 1.00 phsubw %xmm0, %xmm2
+# CHECK-NEXT: 4 9 1.00 * phsubw (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.50 pmaddubsw %mm0, %mm2
+# CHECK-NEXT: 2 13 0.50 * pmaddubsw (%rax), %mm2
+# CHECK-NEXT: 1 4 2.00 pmaddubsw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * pmaddubsw (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.50 pmulhrsw %mm0, %mm2
+# CHECK-NEXT: 2 13 0.50 * pmulhrsw (%rax), %mm2
+# CHECK-NEXT: 1 4 2.00 pmulhrsw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 2.00 * pmulhrsw (%rax), %xmm2
+# CHECK-NEXT: 2 3 0.50 pshufb %mm0, %mm2
+# CHECK-NEXT: 3 11 0.50 * pshufb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pshufb %xmm0, %xmm2
+# CHECK-NEXT: 2 7 2.00 * pshufb (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 psignb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psignb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psignb %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * psignb (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 psignd %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psignd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psignd %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * psignd (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 psignw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psignw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psignw %xmm0, %xmm2
+# CHECK-NEXT: 1 7 2.00 * psignw (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - - 3.00 - 3.00 - 3.00 - - 27.33 27.33 27.33 - - - - 36.50 24.50 28.00 28.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pabsb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - pabsb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pabsb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pabsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pabsd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - pabsd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pabsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pabsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pabsw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - pabsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pabsw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - pabsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 palignr $1, %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 palignr $1, (%rax), %mm2
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - palignr $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 palignr $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 1.25 1.25 phaddd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 1.25 1.25 phaddd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 1.25 1.25 phaddd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 1.25 1.25 phaddd (%rax), %xmm2
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - 0.25 0.25 0.25 0.25 phaddsw %mm0, %mm2
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - phaddsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 1.00 1.00 phaddsw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 1.00 1.00 phaddsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 1.25 1.25 phaddw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 1.25 1.25 phaddw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 1.25 1.25 phaddw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 1.25 1.25 phaddw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 1.25 1.25 phsubd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 1.25 1.25 phsubd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 1.25 1.25 phsubd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 1.25 1.25 phsubd (%rax), %xmm2
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - 0.25 0.25 0.25 0.25 phsubsw %mm0, %mm2
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - phsubsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 1.00 1.00 phsubsw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 1.00 1.00 phsubsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 1.25 1.25 phsubw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 1.25 1.25 phsubw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 1.25 1.25 phsubw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.25 0.25 1.25 1.25 phsubw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pmaddubsw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - pmaddubsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - pmaddubsw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - pmaddubsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - pmulhrsw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - pmulhrsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - pmulhrsw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - pmulhrsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 pshufb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 pshufb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 pshufb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - - - 0.50 0.50 pshufb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - psignb %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - psignb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psignb %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - psignb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - psignd %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - psignd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psignd %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - psignd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - psignw %mm0, %mm2
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 1.00 - - - psignw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - psignw %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 2.00 - - - - 0.50 0.50 - - psignw (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-vaes.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-vaes.s
new file mode 100644
index 0000000000000..ea5a559db163f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-vaes.s
@@ -0,0 +1,69 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+vaesdec %ymm0, %ymm1, %ymm3
+vaesdec (%rax), %ymm1, %ymm3
+
+vaesdeclast %ymm0, %ymm1, %ymm3
+vaesdeclast (%rax), %ymm1, %ymm3
+
+vaesenc %ymm0, %ymm1, %ymm3
+vaesenc (%rax), %ymm1, %ymm3
+
+vaesenclast %ymm0, %ymm1, %ymm3
+vaesenclast (%rax), %ymm1, %ymm3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 2.00 vaesdec %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 2 11 2.33 * vaesdec (%rax), %ymm1, %ymm3
+# CHECK-NEXT: 1 3 2.00 vaesdeclast %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 2 11 2.33 * vaesdeclast (%rax), %ymm1, %ymm3
+# CHECK-NEXT: 1 3 2.00 vaesenc %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 2 11 2.33 * vaesenc (%rax), %ymm1, %ymm3
+# CHECK-NEXT: 1 3 2.00 vaesenclast %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 2 11 2.33 * vaesenclast (%rax), %ymm1, %ymm3
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - - - - - - - - - 9.33 9.33 9.33 - - - - 16.00 16.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vaesdec %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vaesdec (%rax), %ymm1, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vaesdeclast %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vaesdeclast (%rax), %ymm1, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vaesenc %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vaesenc (%rax), %ymm1, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 2.00 - - vaesenclast %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vaesenclast (%rax), %ymm1, %ymm3
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-vpclmulqdq.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-vpclmulqdq.s
new file mode 100644
index 0000000000000..da095842613ad
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-vpclmulqdq.s
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+vpclmulqdq $11, (%rax), %ymm1, %ymm3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 2 10 2.33 * vpclmulqdq $11, (%rax), %ymm1, %ymm3
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 2.00 2.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: - - - - - - - - - 2.33 2.33 2.33 - - - - - - 1.50 1.50 vpclmulqdq $11, (%rax), %ymm1, %ymm3
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-x86_32.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-x86_32.s
new file mode 100644
index 0000000000000..680f1892c5c29
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-x86_32.s
@@ -0,0 +1,90 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+aaa
+
+aad
+aad $7
+
+aam
+aam $7
+
+aas
+
+bound %bx, (%eax)
+bound %ebx, (%eax)
+
+daa
+
+das
+
+into
+
+leave
+
+salc
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.17 aaa
+# CHECK-NEXT: 1 100 0.17 aad
+# CHECK-NEXT: 1 100 0.17 aad $7
+# CHECK-NEXT: 1 100 0.17 aam
+# CHECK-NEXT: 1 100 0.17 aam $7
+# CHECK-NEXT: 1 100 0.17 aas
+# CHECK-NEXT: 1 100 0.17 U bound %bx, (%eax)
+# CHECK-NEXT: 1 100 0.17 U bound %ebx, (%eax)
+# CHECK-NEXT: 1 100 0.17 daa
+# CHECK-NEXT: 1 100 0.17 das
+# CHECK-NEXT: 1 100 0.17 U into
+# CHECK-NEXT: 1 1 0.33 * leave
+# CHECK-NEXT: 1 1 0.17 U salc
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - 2.00 2.33 2.00 2.33 2.00 2.33 - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - aaa
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - aad
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - aad $7
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - aam
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - aam $7
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - aas
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - bound %bx, (%eax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - bound %ebx, (%eax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - daa
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - das
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - into
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - leave
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - salc
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-x86_64.s
new file mode 100644
index 0000000000000..94e5b46f5be16
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-x86_64.s
@@ -0,0 +1,2887 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+adcb $0, %al
+adcb $0, %dil
+adcb $0, (%rax)
+lock adcb $0, (%rax)
+adcb $7, %al
+adcb $7, %dil
+adcb $7, (%rax)
+lock adcb $7, (%rax)
+adcb %sil, %dil
+adcb %sil, (%rax)
+lock adcb %sil, (%rax)
+adcb (%rax), %dil
+
+adcw $0, %ax
+adcw $0, %di
+adcw $0, (%rax)
+lock adcw $0, (%rax)
+adcw $511, %ax
+adcw $511, %di
+adcw $511, (%rax)
+lock adcw $511, (%rax)
+adcw $7, %di
+adcw $7, (%rax)
+lock adcw $7, (%rax)
+adcw %si, %di
+adcw %si, (%rax)
+lock adcw %si, (%rax)
+adcw (%rax), %di
+
+adcl $0, %eax
+adcl $0, %edi
+adcl $0, (%rax)
+lock adcl $0, (%rax)
+adcl $665536, %eax
+adcl $665536, %edi
+adcl $665536, (%rax)
+lock adcl $665536, (%rax)
+adcl $7, %edi
+adcl $7, (%rax)
+lock adcl $7, (%rax)
+adcl %esi, %edi
+adcl %esi, (%rax)
+lock adcl %esi, (%rax)
+adcl (%rax), %edi
+
+adcq $0, %rax
+adcq $0, %rdi
+adcq $0, (%rax)
+lock adcq $0, (%rax)
+adcq $665536, %rax
+adcq $665536, %rdi
+adcq $665536, (%rax)
+lock adcq $665536, (%rax)
+adcq $7, %rdi
+adcq $7, (%rax)
+lock adcq $7, (%rax)
+adcq %rsi, %rdi
+adcq %rsi, (%rax)
+lock adcq %rsi, (%rax)
+adcq (%rax), %rdi
+
+addb $7, %al
+addb $7, %dil
+addb $7, (%rax)
+lock addb $7, (%rax)
+addb %sil, %dil
+addb %sil, (%rax)
+lock addb %sil, (%rax)
+addb (%rax), %dil
+
+addw $511, %ax
+addw $511, %di
+addw $511, (%rax)
+lock addw $511, (%rax)
+addw $7, %di
+addw $7, (%rax)
+lock addw $7, (%rax)
+addw %si, %di
+addw %si, (%rax)
+lock addw %si, (%rax)
+addw (%rax), %di
+
+addl $665536, %eax
+addl $665536, %edi
+addl $665536, (%rax)
+lock addl $665536, (%rax)
+addl $7, %edi
+addl $7, (%rax)
+lock addl $7, (%rax)
+addl %esi, %edi
+addl %esi, (%rax)
+lock addl %esi, (%rax)
+addl (%rax), %edi
+
+addq $665536, %rax
+addq $665536, %rdi
+addq $665536, (%rax)
+lock addq $665536, (%rax)
+addq $7, %rdi
+addq $7, (%rax)
+lock addq $7, (%rax)
+addq %rsi, %rdi
+addq %rsi, (%rax)
+lock addq %rsi, (%rax)
+addq (%rax), %rdi
+
+andb $7, %al
+andb $7, %dil
+andb $7, (%rax)
+lock andb $7, (%rax)
+andb %sil, %dil
+andb %sil, (%rax)
+lock andb %sil, (%rax)
+andb (%rax), %dil
+
+andw $511, %ax
+andw $511, %di
+andw $511, (%rax)
+lock andw $511, (%rax)
+andw $7, %di
+andw $7, (%rax)
+lock andw $7, (%rax)
+andw %si, %di
+andw %si, (%rax)
+lock andw %si, (%rax)
+andw (%rax), %di
+
+andl $665536, %eax
+andl $665536, %edi
+andl $665536, (%rax)
+lock andl $665536, (%rax)
+andl $7, %edi
+andl $7, (%rax)
+lock andl $7, (%rax)
+andl %esi, %edi
+andl %esi, (%rax)
+lock andl %esi, (%rax)
+andl (%rax), %edi
+
+andq $665536, %rax
+andq $665536, %rdi
+andq $665536, (%rax)
+lock andq $665536, (%rax)
+andq $7, %rdi
+andq $7, (%rax)
+lock andq $7, (%rax)
+andq %rsi, %rdi
+andq %rsi, (%rax)
+lock andq %rsi, (%rax)
+andq (%rax), %rdi
+
+bsfw %si, %di
+bsrw %si, %di
+bsfw (%rax), %di
+bsrw (%rax), %di
+
+bsfl %esi, %edi
+bsrl %esi, %edi
+bsfl (%rax), %edi
+bsrl (%rax), %edi
+
+bsfq %rsi, %rdi
+bsrq %rsi, %rdi
+bsfq (%rax), %rdi
+bsrq (%rax), %rdi
+
+bswap %eax
+bswap %rax
+
+btw %si, %di
+btcw %si, %di
+btrw %si, %di
+btsw %si, %di
+btw %si, (%rax)
+btcw %si, (%rax)
+btrw %si, (%rax)
+btsw %si, (%rax)
+lock btcw %si, (%rax)
+lock btrw %si, (%rax)
+lock btsw %si, (%rax)
+btw $7, %di
+btcw $7, %di
+btrw $7, %di
+btsw $7, %di
+btw $7, (%rax)
+btcw $7, (%rax)
+btrw $7, (%rax)
+btsw $7, (%rax)
+lock btcw $7, (%rax)
+lock btrw $7, (%rax)
+lock btsw $7, (%rax)
+
+btl %esi, %edi
+btcl %esi, %edi
+btrl %esi, %edi
+btsl %esi, %edi
+btl %esi, (%rax)
+btcl %esi, (%rax)
+btrl %esi, (%rax)
+btsl %esi, (%rax)
+lock btcl %esi, (%rax)
+lock btrl %esi, (%rax)
+lock btsl %esi, (%rax)
+btl $7, %edi
+btcl $7, %edi
+btrl $7, %edi
+btsl $7, %edi
+btl $7, (%rax)
+btcl $7, (%rax)
+btrl $7, (%rax)
+btsl $7, (%rax)
+lock btcl $7, (%rax)
+lock btrl $7, (%rax)
+lock btsl $7, (%rax)
+
+btq %rsi, %rdi
+btcq %rsi, %rdi
+btrq %rsi, %rdi
+btsq %rsi, %rdi
+btq %rsi, (%rax)
+btcq %rsi, (%rax)
+btrq %rsi, (%rax)
+btsq %rsi, (%rax)
+lock btcq %rsi, (%rax)
+lock btrq %rsi, (%rax)
+lock btsq %rsi, (%rax)
+btq $7, %rdi
+btcq $7, %rdi
+btrq $7, %rdi
+btsq $7, %rdi
+btq $7, (%rax)
+btcq $7, (%rax)
+btrq $7, (%rax)
+btsq $7, (%rax)
+lock btcq $7, (%rax)
+lock btrq $7, (%rax)
+lock btsq $7, (%rax)
+
+cbw
+cwde
+cdqe
+cwd
+cdq
+cqo
+
+clc
+cld
+cmc
+
+cmpb $7, %al
+cmpb $7, %dil
+cmpb $7, (%rax)
+cmpb %sil, %dil
+cmpb %sil, (%rax)
+cmpb (%rax), %dil
+
+cmpw $511, %ax
+cmpw $511, %di
+cmpw $511, (%rax)
+cmpw $7, %di
+cmpw $7, (%rax)
+cmpw %si, %di
+cmpw %si, (%rax)
+cmpw (%rax), %di
+
+cmpl $665536, %eax
+cmpl $665536, %edi
+cmpl $665536, (%rax)
+cmpl $7, %edi
+cmpl $7, (%rax)
+cmpl %esi, %edi
+cmpl %esi, (%rax)
+cmpl (%rax), %edi
+
+cmpq $665536, %rax
+cmpq $665536, %rdi
+cmpq $665536, (%rax)
+cmpq $7, %rdi
+cmpq $7, (%rax)
+cmpq %rsi, %rdi
+cmpq %rsi, (%rax)
+cmpq (%rax), %rdi
+
+cmpsb
+cmpsw
+cmpsl
+cmpsq
+
+cmpxchgb %cl, %bl
+cmpxchgb %cl, (%rbx)
+lock cmpxchgb %cl, (%rbx)
+
+cmpxchgw %cx, %bx
+cmpxchgw %cx, (%rbx)
+lock cmpxchgw %cx, (%rbx)
+
+cmpxchgl %ecx, %ebx
+cmpxchgl %ecx, (%rbx)
+lock cmpxchgl %ecx, (%rbx)
+
+cmpxchgq %rcx, %rbx
+cmpxchgq %rcx, (%rbx)
+lock cmpxchgq %rcx, (%rbx)
+
+cpuid
+
+decb %dil
+decb (%rax)
+lock decb (%rax)
+decw %di
+decw (%rax)
+lock decw (%rax)
+decl %edi
+decl (%rax)
+lock decl (%rax)
+decq %rdi
+decq (%rax)
+lock decq (%rax)
+
+divb %dil
+divb (%rax)
+divw %si
+divw (%rax)
+divl %edx
+divl (%rax)
+divq %rcx
+divq (%rax)
+
+enter $7, $4095
+
+idivb %dil
+idivb (%rax)
+idivw %si
+idivw (%rax)
+idivl %edx
+idivl (%rax)
+idivq %rcx
+idivq (%rax)
+
+imulb %dil
+imulb (%rax)
+
+imulw %di
+imulw (%rax)
+imulw %si, %di
+imulw (%rax), %di
+imulw $511, %si, %di
+imulw $511, (%rax), %di
+imulw $7, %si, %di
+imulw $7, (%rax), %di
+
+imull %edi
+imull (%rax)
+imull %esi, %edi
+imull (%rax), %edi
+imull $665536, %esi, %edi
+imull $665536, (%rax), %edi
+imull $7, %esi, %edi
+imull $7, (%rax), %edi
+
+imulq %rdi
+imulq (%rax)
+imulq %rsi, %rdi
+imulq (%rax), %rdi
+imulq $665536, %rsi, %rdi
+imulq $665536, (%rax), %rdi
+imulq $7, %rsi, %rdi
+imulq $7, (%rax), %rdi
+
+inb $7, %al
+inb %dx, %al
+inw $7, %ax
+inw %dx, %ax
+inl $7, %eax
+inl %dx, %eax
+
+incb %dil
+incb (%rax)
+lock incb (%rax)
+incw %di
+incw (%rax)
+lock incw (%rax)
+incl %edi
+incl (%rax)
+lock incl (%rax)
+incq %rdi
+incq (%rax)
+lock incq (%rax)
+
+insb
+insw
+insl
+
+int $7
+
+invlpg (%rax)
+invlpga %rax, %ecx
+
+leave
+
+lodsb
+lodsw
+lodsl
+lodsq
+
+loop 0
+loope 0
+loopne 0
+
+movsb
+movsw
+movsl
+movsq
+
+movsbw %al, %di
+movzbw %al, %di
+movsbw (%rax), %di
+movzbw (%rax), %di
+movsbl %al, %edi
+movzbl %al, %edi
+movsbl (%rax), %edi
+movzbl (%rax), %edi
+movsbq %al, %rdi
+movzbq %al, %rdi
+movsbq (%rax), %rdi
+movzbq (%rax), %rdi
+
+movswl %ax, %edi
+movzwl %ax, %edi
+movswl (%rax), %edi
+movzwl (%rax), %edi
+movswq %ax, %rdi
+movzwq %ax, %rdi
+movswq (%rax), %rdi
+movzwq (%rax), %rdi
+
+movslq %eax, %rdi
+movslq (%rax), %rdi
+
+mulb %dil
+mulb (%rax)
+mulw %si
+mulw (%rax)
+mull %edx
+mull (%rax)
+mulq %rcx
+mulq (%rax)
+
+negb %dil
+negb (%r8)
+lock negb (%r8)
+negw %si
+negw (%r9)
+lock negw (%r9)
+negl %edx
+negl (%rax)
+lock negl (%rax)
+negq %rcx
+negq (%r10)
+lock negq (%r10)
+
+nop
+nopw %di
+nopw (%rcx)
+nopl %esi
+nopl (%r8)
+nopq %rdx
+nopq (%r9)
+
+notb %dil
+notb (%r8)
+lock notb (%r8)
+notw %si
+notw (%r9)
+lock notw (%r9)
+notl %edx
+notl (%rax)
+lock notl (%rax)
+notq %rcx
+notq (%r10)
+lock notq (%r10)
+
+orb $7, %al
+orb $7, %dil
+orb $7, (%rax)
+lock orb $7, (%rax)
+orb %sil, %dil
+orb %sil, (%rax)
+lock orb %sil, (%rax)
+orb (%rax), %dil
+
+orw $511, %ax
+orw $511, %di
+orw $511, (%rax)
+lock orw $511, (%rax)
+orw $7, %di
+orw $7, (%rax)
+lock orw $7, (%rax)
+orw %si, %di
+orw %si, (%rax)
+lock orw %si, (%rax)
+orw (%rax), %di
+
+orl $665536, %eax
+orl $665536, %edi
+orl $665536, (%rax)
+lock orl $665536, (%rax)
+orl $7, %edi
+orl $7, (%rax)
+lock orl $7, (%rax)
+orl %esi, %edi
+orl %esi, (%rax)
+lock orl %esi, (%rax)
+orl (%rax), %edi
+
+orq $665536, %rax
+orq $665536, %rdi
+orq $665536, (%rax)
+lock orq $665536, (%rax)
+orq $7, %rdi
+orq $7, (%rax)
+lock orq $7, (%rax)
+orq %rsi, %rdi
+orq %rsi, (%rax)
+lock orq %rsi, (%rax)
+orq (%rax), %rdi
+
+outb %al, $7
+outb %al, %dx
+outw %ax, $7
+outw %ax, %dx
+outl %eax, $7
+outl %eax, %dx
+
+outsb
+outsw
+outsl
+
+pause
+
+rclb %dil
+rcrb %dil
+rclb (%rax)
+rcrb (%rax)
+rclb $7, %dil
+rcrb $7, %dil
+rclb $7, (%rax)
+rcrb $7, (%rax)
+rclb %cl, %dil
+rcrb %cl, %dil
+rclb %cl, (%rax)
+rcrb %cl, (%rax)
+
+rclw %di
+rcrw %di
+rclw (%rax)
+rcrw (%rax)
+rclw $7, %di
+rcrw $7, %di
+rclw $7, (%rax)
+rcrw $7, (%rax)
+rclw %cl, %di
+rcrw %cl, %di
+rclw %cl, (%rax)
+rcrw %cl, (%rax)
+
+rcll %edi
+rcrl %edi
+rcll (%rax)
+rcrl (%rax)
+rcll $7, %edi
+rcrl $7, %edi
+rcll $7, (%rax)
+rcrl $7, (%rax)
+rcll %cl, %edi
+rcrl %cl, %edi
+rcll %cl, (%rax)
+rcrl %cl, (%rax)
+
+rclq %rdi
+rcrq %rdi
+rclq (%rax)
+rcrq (%rax)
+rclq $7, %rdi
+rcrq $7, %rdi
+rclq $7, (%rax)
+rcrq $7, (%rax)
+rclq %cl, %rdi
+rcrq %cl, %rdi
+rclq %cl, (%rax)
+rcrq %cl, (%rax)
+
+rdmsr
+rdpmc
+rdtsc
+rdtscp
+
+rolb %dil
+rorb %dil
+rolb (%rax)
+rorb (%rax)
+rolb $7, %dil
+rorb $7, %dil
+rolb $7, (%rax)
+rorb $7, (%rax)
+rolb %cl, %dil
+rorb %cl, %dil
+rolb %cl, (%rax)
+rorb %cl, (%rax)
+
+rolw %di
+rorw %di
+rolw (%rax)
+rorw (%rax)
+rolw $7, %di
+rorw $7, %di
+rolw $7, (%rax)
+rorw $7, (%rax)
+rolw %cl, %di
+rorw %cl, %di
+rolw %cl, (%rax)
+rorw %cl, (%rax)
+
+roll %edi
+rorl %edi
+roll (%rax)
+rorl (%rax)
+roll $7, %edi
+rorl $7, %edi
+roll $7, (%rax)
+rorl $7, (%rax)
+roll %cl, %edi
+rorl %cl, %edi
+roll %cl, (%rax)
+rorl %cl, (%rax)
+
+rolq %rdi
+rorq %rdi
+rolq (%rax)
+rorq (%rax)
+rolq $7, %rdi
+rorq $7, %rdi
+rolq $7, (%rax)
+rorq $7, (%rax)
+rolq %cl, %rdi
+rorq %cl, %rdi
+rolq %cl, (%rax)
+rorq %cl, (%rax)
+
+sahf
+
+sarb %dil
+shlb %dil
+shrb %dil
+sarb (%rax)
+shlb (%rax)
+shrb (%rax)
+sarb $7, %dil
+shlb $7, %dil
+shrb $7, %dil
+sarb $7, (%rax)
+shlb $7, (%rax)
+shrb $7, (%rax)
+sarb %cl, %dil
+shlb %cl, %dil
+shrb %cl, %dil
+sarb %cl, (%rax)
+shlb %cl, (%rax)
+shrb %cl, (%rax)
+
+sarw %di
+shlw %di
+shrw %di
+sarw (%rax)
+shlw (%rax)
+shrw (%rax)
+sarw $7, %di
+shlw $7, %di
+shrw $7, %di
+sarw $7, (%rax)
+shlw $7, (%rax)
+shrw $7, (%rax)
+sarw %cl, %di
+shlw %cl, %di
+shrw %cl, %di
+sarw %cl, (%rax)
+shlw %cl, (%rax)
+shrw %cl, (%rax)
+
+sarl %edi
+shll %edi
+shrl %edi
+sarl (%rax)
+shll (%rax)
+shrl (%rax)
+sarl $7, %edi
+shll $7, %edi
+shrl $7, %edi
+sarl $7, (%rax)
+shll $7, (%rax)
+shrl $7, (%rax)
+sarl %cl, %edi
+shll %cl, %edi
+shrl %cl, %edi
+sarl %cl, (%rax)
+shll %cl, (%rax)
+shrl %cl, (%rax)
+
+sarq %rdi
+shlq %rdi
+shrq %rdi
+sarq (%rax)
+shlq (%rax)
+shrq (%rax)
+sarq $7, %rdi
+shlq $7, %rdi
+shrq $7, %rdi
+sarq $7, (%rax)
+shlq $7, (%rax)
+shrq $7, (%rax)
+sarq %cl, %rdi
+shlq %cl, %rdi
+shrq %cl, %rdi
+sarq %cl, (%rax)
+shlq %cl, (%rax)
+shrq %cl, (%rax)
+
+sbbb $0, %al
+sbbb $0, %dil
+sbbb $0, (%rax)
+lock sbbb $0, (%rax)
+sbbb $7, %al
+sbbb $7, %dil
+sbbb $7, (%rax)
+lock sbbb $7, (%rax)
+sbbb %sil, %dil
+sbbb %sil, (%rax)
+lock sbbb %sil, (%rax)
+sbbb (%rax), %dil
+
+sbbw $0, %ax
+sbbw $0, %di
+sbbw $0, (%rax)
+lock sbbw $0, (%rax)
+sbbw $511, %ax
+sbbw $511, %di
+sbbw $511, (%rax)
+lock sbbw $511, (%rax)
+sbbw $7, %di
+sbbw $7, (%rax)
+lock sbbw $7, (%rax)
+sbbw %si, %di
+sbbw %si, (%rax)
+lock sbbw %si, (%rax)
+sbbw (%rax), %di
+
+sbbl $0, %eax
+sbbl $0, %edi
+sbbl $0, (%rax)
+lock sbbl $0, (%rax)
+sbbl $665536, %eax
+sbbl $665536, %edi
+sbbl $665536, (%rax)
+lock sbbl $665536, (%rax)
+sbbl $7, %edi
+sbbl $7, (%rax)
+lock sbbl $7, (%rax)
+sbbl %esi, %edi
+sbbl %esi, (%rax)
+lock sbbl %esi, (%rax)
+sbbl (%rax), %edi
+
+sbbq $0, %rax
+sbbq $0, %rdi
+sbbq $0, (%rax)
+lock sbbq $0, (%rax)
+sbbq $665536, %rax
+sbbq $665536, %rdi
+sbbq $665536, (%rax)
+lock sbbq $665536, (%rax)
+sbbq $7, %rdi
+sbbq $7, (%rax)
+lock sbbq $7, (%rax)
+sbbq %rsi, %rdi
+sbbq %rsi, (%rax)
+lock sbbq %rsi, (%rax)
+sbbq (%rax), %rdi
+
+scasb
+scasw
+scasl
+scasq
+
+seto %al
+seto (%rax)
+setno %al
+setno (%rax)
+setb %al
+setb (%rax)
+setnb %al
+setnb (%rax)
+setz %al
+setz (%rax)
+setnz %al
+setnz (%rax)
+seta %al
+seta (%rax)
+setna %al
+setna (%rax)
+sets %al
+sets (%rax)
+setns %al
+setns (%rax)
+setp %al
+setp (%rax)
+setnp %al
+setnp (%rax)
+setl %al
+setl (%rax)
+setnl %al
+setnl (%rax)
+setg %al
+setg (%rax)
+setng %al
+setng (%rax)
+
+shldw %cl, %si, %di
+shrdw %cl, %si, %di
+shldw %cl, %si, (%rax)
+shrdw %cl, %si, (%rax)
+shldw $7, %si, %di
+shrdw $7, %si, %di
+shldw $7, %si, (%rax)
+shrdw $7, %si, (%rax)
+
+shldl %cl, %esi, %edi
+shrdl %cl, %esi, %edi
+shldl %cl, %esi, (%rax)
+shrdl %cl, %esi, (%rax)
+shldl $7, %esi, %edi
+shrdl $7, %esi, %edi
+shldl $7, %esi, (%rax)
+shrdl $7, %esi, (%rax)
+
+shldq %cl, %rsi, %rdi
+shrdq %cl, %rsi, %rdi
+shldq %cl, %rsi, (%rax)
+shrdq %cl, %rsi, (%rax)
+shldq $7, %rsi, %rdi
+shrdq $7, %rsi, %rdi
+shldq $7, %rsi, (%rax)
+shrdq $7, %rsi, (%rax)
+
+stc
+std
+
+stosb
+stosw
+stosl
+stosq
+
+subb $7, %al
+subb $7, %dil
+subb $7, (%rax)
+lock subb $7, (%rax)
+subb %sil, %dil
+subb %sil, (%rax)
+lock subb %sil, (%rax)
+subb (%rax), %dil
+
+subw $511, %ax
+subw $511, %di
+subw $511, (%rax)
+lock subw $511, (%rax)
+subw $7, %di
+subw $7, (%rax)
+lock subw $7, (%rax)
+subw %si, %di
+subw %si, (%rax)
+lock subw %si, (%rax)
+subw (%rax), %di
+
+subl $665536, %eax
+subl $665536, %edi
+subl $665536, (%rax)
+lock subl $665536, (%rax)
+subl $7, %edi
+subl $7, (%rax)
+lock subl $7, (%rax)
+subl %esi, %edi
+subl %esi, (%rax)
+lock subl %esi, (%rax)
+subl (%rax), %edi
+
+subq $665536, %rax
+subq $665536, %rdi
+subq $665536, (%rax)
+lock subq $665536, (%rax)
+subq $7, %rdi
+subq $7, (%rax)
+lock subq $7, (%rax)
+subq %rsi, %rdi
+subq %rsi, (%rax)
+lock subq %rsi, (%rax)
+subq (%rax), %rdi
+
+testb $7, %al
+testb $7, %dil
+testb $7, (%rax)
+testb %sil, %dil
+testb %sil, (%rax)
+
+testw $511, %ax
+testw $511, %di
+testw $511, (%rax)
+testw $7, %di
+testw $7, (%rax)
+testw %si, %di
+testw %si, (%rax)
+
+testl $665536, %eax
+testl $665536, %edi
+testl $665536, (%rax)
+testl $7, %edi
+testl $7, (%rax)
+testl %esi, %edi
+testl %esi, (%rax)
+
+testq $665536, %rax
+testq $665536, %rdi
+testq $665536, (%rax)
+testq $7, %rdi
+testq $7, (%rax)
+testq %rsi, %rdi
+testq %rsi, (%rax)
+
+ud2
+
+wrmsr
+
+xaddb %bl, %cl
+xaddb %bl, (%rcx)
+lock xaddb %bl, (%rcx)
+
+xaddw %bx, %cx
+xaddw %ax, (%rbx)
+lock xaddw %ax, (%rbx)
+
+xaddl %ebx, %ecx
+xaddl %eax, (%rbx)
+lock xaddl %eax, (%rbx)
+
+xaddq %rbx, %rcx
+xaddq %rax, (%rbx)
+lock xaddq %rax, (%rbx)
+
+xchgb %bl, %cl
+xchgb %bl, (%rbx)
+lock xchgb %bl, (%rbx)
+
+xchgw %ax, %bx
+xchgw %bx, %cx
+xchgw %ax, (%rbx)
+lock xchgw %ax, (%rbx)
+
+xchgl %eax, %ebx
+xchgl %ebx, %ecx
+xchgl %eax, (%rbx)
+lock xchgl %eax, (%rbx)
+
+xchgq %rax, %rbx
+xchgq %rbx, %rcx
+xchgq %rax, (%rbx)
+lock xchgq %rax, (%rbx)
+
+xlatb
+
+xorb $7, %al
+xorb $7, %dil
+xorb $7, (%rax)
+lock xorb $7, (%rax)
+xorb %sil, %dil
+xorb %sil, (%rax)
+lock xorb %sil, (%rax)
+xorb (%rax), %dil
+
+xorw $511, %ax
+xorw $511, %di
+xorw $511, (%rax)
+lock xorw $511, (%rax)
+xorw $7, %di
+xorw $7, (%rax)
+lock xorw $7, (%rax)
+xorw %si, %di
+xorw %si, (%rax)
+lock xorw %si, (%rax)
+xorw (%rax), %di
+
+xorl $665536, %eax
+xorl $665536, %edi
+xorl $665536, (%rax)
+lock xorl $665536, (%rax)
+xorl $7, %edi
+xorl $7, (%rax)
+lock xorl $7, (%rax)
+xorl %esi, %edi
+xorl %esi, (%rax)
+lock xorl %esi, (%rax)
+xorl (%rax), %edi
+
+xorq $665536, %rax
+xorq $665536, %rdi
+xorq $665536, (%rax)
+lock xorq $665536, (%rax)
+xorq $7, %rdi
+xorq $7, (%rax)
+lock xorq $7, (%rax)
+xorq %rsi, %rdi
+xorq %rsi, (%rax)
+lock xorq %rsi, (%rax)
+xorq (%rax), %rdi
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.33 adcb $0, %al
+# CHECK-NEXT: 1 1 0.33 adcb $0, %dil
+# CHECK-NEXT: 5 12 0.50 * * adcb $0, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcb $0, (%rax)
+# CHECK-NEXT: 1 1 0.33 adcb $7, %al
+# CHECK-NEXT: 1 1 0.33 adcb $7, %dil
+# CHECK-NEXT: 5 12 0.50 * * adcb $7, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcb $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 adcb %sil, %dil
+# CHECK-NEXT: 5 12 0.50 * * adcb %sil, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.33 * adcb (%rax), %dil
+# CHECK-NEXT: 1 1 0.33 adcw $0, %ax
+# CHECK-NEXT: 1 1 0.33 adcw $0, %di
+# CHECK-NEXT: 5 12 0.50 * * adcw $0, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcw $0, (%rax)
+# CHECK-NEXT: 1 1 0.33 adcw $511, %ax
+# CHECK-NEXT: 1 1 0.33 adcw $511, %di
+# CHECK-NEXT: 5 12 0.50 * * adcw $511, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcw $511, (%rax)
+# CHECK-NEXT: 1 1 0.33 adcw $7, %di
+# CHECK-NEXT: 5 12 0.50 * * adcw $7, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcw $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 adcw %si, %di
+# CHECK-NEXT: 6 12 0.50 * * adcw %si, (%rax)
+# CHECK-NEXT: 6 12 0.50 * * lock adcw %si, (%rax)
+# CHECK-NEXT: 2 6 0.33 * adcw (%rax), %di
+# CHECK-NEXT: 1 1 0.33 adcl $0, %eax
+# CHECK-NEXT: 1 1 0.33 adcl $0, %edi
+# CHECK-NEXT: 5 12 0.50 * * adcl $0, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcl $0, (%rax)
+# CHECK-NEXT: 1 1 0.33 adcl $665536, %eax
+# CHECK-NEXT: 1 1 0.33 adcl $665536, %edi
+# CHECK-NEXT: 5 12 0.50 * * adcl $665536, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.33 adcl $7, %edi
+# CHECK-NEXT: 5 12 0.50 * * adcl $7, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcl $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 adcl %esi, %edi
+# CHECK-NEXT: 6 12 0.50 * * adcl %esi, (%rax)
+# CHECK-NEXT: 6 12 0.50 * * lock adcl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * adcl (%rax), %edi
+# CHECK-NEXT: 1 1 0.33 adcq $0, %rax
+# CHECK-NEXT: 1 1 0.33 adcq $0, %rdi
+# CHECK-NEXT: 5 12 0.50 * * adcq $0, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcq $0, (%rax)
+# CHECK-NEXT: 1 1 0.33 adcq $665536, %rax
+# CHECK-NEXT: 1 1 0.33 adcq $665536, %rdi
+# CHECK-NEXT: 5 12 0.50 * * adcq $665536, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.33 adcq $7, %rdi
+# CHECK-NEXT: 5 12 0.50 * * adcq $7, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcq $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 adcq %rsi, %rdi
+# CHECK-NEXT: 6 12 0.50 * * adcq %rsi, (%rax)
+# CHECK-NEXT: 6 12 0.50 * * lock adcq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * adcq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.33 addb $7, %al
+# CHECK-NEXT: 1 1 0.33 addb $7, %dil
+# CHECK-NEXT: 4 13 0.50 * * addb $7, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock addb $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 addb %sil, %dil
+# CHECK-NEXT: 4 13 0.50 * * addb %sil, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock addb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.33 * addb (%rax), %dil
+# CHECK-NEXT: 1 1 0.33 addw $511, %ax
+# CHECK-NEXT: 1 1 0.33 addw $511, %di
+# CHECK-NEXT: 4 12 0.67 * * addw $511, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock addw $511, (%rax)
+# CHECK-NEXT: 1 1 0.33 addw $7, %di
+# CHECK-NEXT: 4 12 0.67 * * addw $7, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock addw $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 addw %si, %di
+# CHECK-NEXT: 4 12 0.67 * * addw %si, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock addw %si, (%rax)
+# CHECK-NEXT: 2 6 0.33 * addw (%rax), %di
+# CHECK-NEXT: 1 1 0.33 addl $665536, %eax
+# CHECK-NEXT: 1 1 0.33 addl $665536, %edi
+# CHECK-NEXT: 4 12 0.67 * * addl $665536, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock addl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.33 addl $7, %edi
+# CHECK-NEXT: 4 12 0.67 * * addl $7, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock addl $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 addl %esi, %edi
+# CHECK-NEXT: 4 12 0.67 * * addl %esi, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock addl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * addl (%rax), %edi
+# CHECK-NEXT: 1 1 0.33 addq $665536, %rax
+# CHECK-NEXT: 1 1 0.33 addq $665536, %rdi
+# CHECK-NEXT: 4 12 0.67 * * addq $665536, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock addq $665536, (%rax)
+# CHECK-NEXT: 0 1 0.00 addq $7, %rdi
+# CHECK-NEXT: 4 12 0.67 * * addq $7, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock addq $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 addq %rsi, %rdi
+# CHECK-NEXT: 4 12 0.67 * * addq %rsi, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock addq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * addq (%rax), %rdi
+# CHECK-NEXT: 1 2 0.17 andb $7, %al
+# CHECK-NEXT: 1 2 0.17 andb $7, %dil
+# CHECK-NEXT: 4 13 0.50 * * andb $7, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock andb $7, (%rax)
+# CHECK-NEXT: 1 2 0.17 andb %sil, %dil
+# CHECK-NEXT: 4 13 0.50 * * andb %sil, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock andb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.33 * andb (%rax), %dil
+# CHECK-NEXT: 1 1 0.33 andw $511, %ax
+# CHECK-NEXT: 1 1 0.33 andw $511, %di
+# CHECK-NEXT: 4 12 0.67 * * andw $511, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock andw $511, (%rax)
+# CHECK-NEXT: 1 2 0.17 andw $7, %di
+# CHECK-NEXT: 4 12 0.67 * * andw $7, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock andw $7, (%rax)
+# CHECK-NEXT: 1 2 0.17 andw %si, %di
+# CHECK-NEXT: 4 12 0.67 * * andw %si, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock andw %si, (%rax)
+# CHECK-NEXT: 2 6 0.33 * andw (%rax), %di
+# CHECK-NEXT: 1 2 0.17 andl $665536, %eax
+# CHECK-NEXT: 1 2 0.17 andl $665536, %edi
+# CHECK-NEXT: 4 12 0.67 * * andl $665536, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock andl $665536, (%rax)
+# CHECK-NEXT: 1 2 0.17 andl $7, %edi
+# CHECK-NEXT: 4 12 0.67 * * andl $7, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock andl $7, (%rax)
+# CHECK-NEXT: 1 2 0.17 andl %esi, %edi
+# CHECK-NEXT: 4 12 0.67 * * andl %esi, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock andl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * andl (%rax), %edi
+# CHECK-NEXT: 1 2 0.17 andq $665536, %rax
+# CHECK-NEXT: 1 2 0.17 andq $665536, %rdi
+# CHECK-NEXT: 4 12 0.67 * * andq $665536, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock andq $665536, (%rax)
+# CHECK-NEXT: 1 2 0.17 andq $7, %rdi
+# CHECK-NEXT: 4 12 0.67 * * andq $7, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock andq $7, (%rax)
+# CHECK-NEXT: 1 2 0.17 andq %rsi, %rdi
+# CHECK-NEXT: 4 12 0.67 * * andq %rsi, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock andq %rsi, (%rax)
+# CHECK-NEXT: 2 7 0.33 * andq (%rax), %rdi
+# CHECK-NEXT: 1 3 0.33 bsfw %si, %di
+# CHECK-NEXT: 1 3 0.33 bsrw %si, %di
+# CHECK-NEXT: 2 7 0.33 * bsfw (%rax), %di
+# CHECK-NEXT: 2 7 0.33 * bsrw (%rax), %di
+# CHECK-NEXT: 1 3 0.33 bsfl %esi, %edi
+# CHECK-NEXT: 1 3 0.33 bsrl %esi, %edi
+# CHECK-NEXT: 2 7 0.33 * bsfl (%rax), %edi
+# CHECK-NEXT: 2 7 0.33 * bsrl (%rax), %edi
+# CHECK-NEXT: 1 3 0.33 bsfq %rsi, %rdi
+# CHECK-NEXT: 1 3 0.33 bsrq %rsi, %rdi
+# CHECK-NEXT: 2 7 0.33 * bsfq (%rax), %rdi
+# CHECK-NEXT: 2 7 0.33 * bsrq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.33 bswapl %eax
+# CHECK-NEXT: 2 2 0.67 bswapq %rax
+# CHECK-NEXT: 1 1 0.33 btw %si, %di
+# CHECK-NEXT: 1 1 0.33 btcw %si, %di
+# CHECK-NEXT: 1 1 0.33 btrw %si, %di
+# CHECK-NEXT: 1 1 0.33 btsw %si, %di
+# CHECK-NEXT: 10 11 1.50 * btw %si, (%rax)
+# CHECK-NEXT: 11 18 1.33 * * btcw %si, (%rax)
+# CHECK-NEXT: 11 18 1.33 * * btrw %si, (%rax)
+# CHECK-NEXT: 11 18 1.33 * * btsw %si, (%rax)
+# CHECK-NEXT: 11 18 1.33 * * lock btcw %si, (%rax)
+# CHECK-NEXT: 11 18 1.33 * * lock btrw %si, (%rax)
+# CHECK-NEXT: 11 18 1.33 * * lock btsw %si, (%rax)
+# CHECK-NEXT: 1 1 0.33 btw $7, %di
+# CHECK-NEXT: 1 1 0.33 btcw $7, %di
+# CHECK-NEXT: 1 1 0.33 btrw $7, %di
+# CHECK-NEXT: 1 1 0.33 btsw $7, %di
+# CHECK-NEXT: 2 6 0.33 * btw $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * btcw $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * btrw $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * btsw $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock btcw $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock btrw $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock btsw $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 btl %esi, %edi
+# CHECK-NEXT: 1 1 0.33 btcl %esi, %edi
+# CHECK-NEXT: 1 1 0.33 btrl %esi, %edi
+# CHECK-NEXT: 1 1 0.33 btsl %esi, %edi
+# CHECK-NEXT: 10 11 1.50 * btl %esi, (%rax)
+# CHECK-NEXT: 11 18 1.33 * * btcl %esi, (%rax)
+# CHECK-NEXT: 11 18 1.33 * * btrl %esi, (%rax)
+# CHECK-NEXT: 11 18 1.33 * * btsl %esi, (%rax)
+# CHECK-NEXT: 11 18 1.33 * * lock btcl %esi, (%rax)
+# CHECK-NEXT: 11 18 1.33 * * lock btrl %esi, (%rax)
+# CHECK-NEXT: 11 18 1.33 * * lock btsl %esi, (%rax)
+# CHECK-NEXT: 1 1 0.33 btl $7, %edi
+# CHECK-NEXT: 1 1 0.33 btcl $7, %edi
+# CHECK-NEXT: 1 1 0.33 btrl $7, %edi
+# CHECK-NEXT: 1 1 0.33 btsl $7, %edi
+# CHECK-NEXT: 2 6 0.33 * btl $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * btcl $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * btrl $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * btsl $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock btcl $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock btrl $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock btsl $7, (%rax)
+# CHECK-NEXT: 1 3 1.00 btq %rsi, %rdi
+# CHECK-NEXT: 1 3 1.00 btcq %rsi, %rdi
+# CHECK-NEXT: 1 3 1.00 btrq %rsi, %rdi
+# CHECK-NEXT: 1 3 1.00 btsq %rsi, %rdi
+# CHECK-NEXT: 9 10 1.33 * btq %rsi, (%rax)
+# CHECK-NEXT: 10 17 1.17 * * btcq %rsi, (%rax)
+# CHECK-NEXT: 10 17 1.17 * * btrq %rsi, (%rax)
+# CHECK-NEXT: 10 17 1.17 * * btsq %rsi, (%rax)
+# CHECK-NEXT: 10 17 1.17 * * lock btcq %rsi, (%rax)
+# CHECK-NEXT: 10 17 1.17 * * lock btrq %rsi, (%rax)
+# CHECK-NEXT: 10 17 1.17 * * lock btsq %rsi, (%rax)
+# CHECK-NEXT: 1 1 0.33 btq $7, %rdi
+# CHECK-NEXT: 1 1 0.33 btcq $7, %rdi
+# CHECK-NEXT: 1 1 0.33 btrq $7, %rdi
+# CHECK-NEXT: 1 1 0.33 btsq $7, %rdi
+# CHECK-NEXT: 2 6 0.33 * btq $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * btcq $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * btrq $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * btsq $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock btcq $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock btrq $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock btsq $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 cbtw
+# CHECK-NEXT: 1 1 0.50 cwtl
+# CHECK-NEXT: 1 1 0.50 cltq
+# CHECK-NEXT: 2 2 0.33 cwtd
+# CHECK-NEXT: 1 1 0.33 cltd
+# CHECK-NEXT: 1 1 0.33 cqto
+# CHECK-NEXT: 0 1 0.00 U clc
+# CHECK-NEXT: 2 3 0.33 U cld
+# CHECK-NEXT: 1 1 0.33 U cmc
+# CHECK-NEXT: 1 1 0.33 cmpb $7, %al
+# CHECK-NEXT: 1 1 0.33 cmpb $7, %dil
+# CHECK-NEXT: 2 6 0.33 * cmpb $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 cmpb %sil, %dil
+# CHECK-NEXT: 2 6 0.33 * cmpb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.33 * cmpb (%rax), %dil
+# CHECK-NEXT: 1 1 0.33 cmpw $511, %ax
+# CHECK-NEXT: 1 1 0.33 cmpw $511, %di
+# CHECK-NEXT: 2 6 0.33 * cmpw $511, (%rax)
+# CHECK-NEXT: 1 1 0.33 cmpw $7, %di
+# CHECK-NEXT: 2 6 0.33 * cmpw $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 cmpw %si, %di
+# CHECK-NEXT: 2 6 0.33 * cmpw %si, (%rax)
+# CHECK-NEXT: 2 6 0.33 * cmpw (%rax), %di
+# CHECK-NEXT: 1 1 0.33 cmpl $665536, %eax
+# CHECK-NEXT: 1 1 0.33 cmpl $665536, %edi
+# CHECK-NEXT: 2 6 0.33 * cmpl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.33 cmpl $7, %edi
+# CHECK-NEXT: 2 6 0.33 * cmpl $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 cmpl %esi, %edi
+# CHECK-NEXT: 2 6 0.33 * cmpl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * cmpl (%rax), %edi
+# CHECK-NEXT: 1 1 0.33 cmpq $665536, %rax
+# CHECK-NEXT: 1 1 0.33 cmpq $665536, %rdi
+# CHECK-NEXT: 2 6 0.33 * cmpq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.33 cmpq $7, %rdi
+# CHECK-NEXT: 2 6 0.33 * cmpq $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 cmpq %rsi, %rdi
+# CHECK-NEXT: 2 6 0.33 * cmpq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * cmpq (%rax), %rdi
+# CHECK-NEXT: 7 6 0.83 U cmpsb %es:(%rdi), (%rsi)
+# CHECK-NEXT: 7 6 0.83 U cmpsw %es:(%rdi), (%rsi)
+# CHECK-NEXT: 7 6 0.83 U cmpsl %es:(%rdi), (%rsi)
+# CHECK-NEXT: 7 6 0.83 U cmpsq %es:(%rdi), (%rsi)
+# CHECK-NEXT: 5 3 0.83 cmpxchgb %cl, %bl
+# CHECK-NEXT: 6 13 0.67 * * cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: 6 13 0.67 * * lock cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: 5 3 0.83 cmpxchgw %cx, %bx
+# CHECK-NEXT: 6 12 0.67 * * cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: 6 12 0.67 * * lock cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: 5 3 0.83 cmpxchgl %ecx, %ebx
+# CHECK-NEXT: 6 12 0.67 * * cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: 6 12 0.67 * * lock cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: 5 3 0.83 cmpxchgq %rcx, %rbx
+# CHECK-NEXT: 6 12 0.67 * * cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: 6 12 0.67 * * lock cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: 26 18 6.00 U cpuid
+# CHECK-NEXT: 1 1 0.33 decb %dil
+# CHECK-NEXT: 4 13 0.50 * * decb (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock decb (%rax)
+# CHECK-NEXT: 1 1 0.33 decw %di
+# CHECK-NEXT: 4 12 0.67 * * decw (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock decw (%rax)
+# CHECK-NEXT: 1 1 0.33 decl %edi
+# CHECK-NEXT: 4 12 0.67 * * decl (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock decl (%rax)
+# CHECK-NEXT: 0 1 0.00 decq %rdi
+# CHECK-NEXT: 4 12 0.67 * * decq (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock decq (%rax)
+# CHECK-NEXT: 3 17 3.00 U divb %dil
+# CHECK-NEXT: 3 22 3.00 * U divb (%rax)
+# CHECK-NEXT: 4 16 3.00 U divw %si
+# CHECK-NEXT: 5 20 3.00 * U divw (%rax)
+# CHECK-NEXT: 4 15 3.00 U divl %edx
+# CHECK-NEXT: 5 19 3.00 * U divl (%rax)
+# CHECK-NEXT: 3 18 3.00 U divq %rcx
+# CHECK-NEXT: 4 22 3.00 * U divq (%rax)
+# CHECK-NEXT: 57 126 7.67 U enter $7, $4095
+# CHECK-NEXT: 3 17 1.00 U idivb %dil
+# CHECK-NEXT: 3 22 1.00 * U idivb (%rax)
+# CHECK-NEXT: 4 16 1.00 U idivw %si
+# CHECK-NEXT: 5 20 1.00 * U idivw (%rax)
+# CHECK-NEXT: 4 15 1.00 U idivl %edx
+# CHECK-NEXT: 5 19 1.00 * U idivl (%rax)
+# CHECK-NEXT: 3 18 1.00 U idivq %rcx
+# CHECK-NEXT: 4 22 1.00 * U idivq (%rax)
+# CHECK-NEXT: 1 3 0.33 imulb %dil
+# CHECK-NEXT: 2 7 0.33 * imulb (%rax)
+# CHECK-NEXT: 4 5 0.67 imulw %di
+# CHECK-NEXT: 5 9 0.67 * imulw (%rax)
+# CHECK-NEXT: 1 3 0.33 imulw %si, %di
+# CHECK-NEXT: 2 7 0.33 * imulw (%rax), %di
+# CHECK-NEXT: 2 4 0.33 imulw $511, %si, %di
+# CHECK-NEXT: 3 8 0.33 * imulw $511, (%rax), %di
+# CHECK-NEXT: 2 4 0.33 imulw $7, %si, %di
+# CHECK-NEXT: 3 8 0.33 * imulw $7, (%rax), %di
+# CHECK-NEXT: 3 4 0.33 imull %edi
+# CHECK-NEXT: 4 8 0.33 * imull (%rax)
+# CHECK-NEXT: 1 3 0.33 imull %esi, %edi
+# CHECK-NEXT: 2 7 0.33 * imull (%rax), %edi
+# CHECK-NEXT: 1 2 0.33 imull $665536, %esi, %edi
+# CHECK-NEXT: 2 6 0.33 * imull $665536, (%rax), %edi
+# CHECK-NEXT: 1 2 0.33 imull $7, %esi, %edi
+# CHECK-NEXT: 2 6 0.33 * imull $7, (%rax), %edi
+# CHECK-NEXT: 2 4 0.33 imulq %rdi
+# CHECK-NEXT: 3 8 0.33 * imulq (%rax)
+# CHECK-NEXT: 1 3 0.33 imulq %rsi, %rdi
+# CHECK-NEXT: 2 7 0.33 * imulq (%rax), %rdi
+# CHECK-NEXT: 1 2 0.33 imulq $665536, %rsi, %rdi
+# CHECK-NEXT: 2 6 0.33 * imulq $665536, (%rax), %rdi
+# CHECK-NEXT: 1 2 0.33 imulq $7, %rsi, %rdi
+# CHECK-NEXT: 2 6 0.33 * imulq $7, (%rax), %rdi
+# CHECK-NEXT: 1 100 0.17 U inb $7, %al
+# CHECK-NEXT: 1 100 0.17 U inb %dx, %al
+# CHECK-NEXT: 1 100 0.17 U inw $7, %ax
+# CHECK-NEXT: 1 100 0.17 U inw %dx, %ax
+# CHECK-NEXT: 1 100 0.17 U inl $7, %eax
+# CHECK-NEXT: 1 100 0.17 U inl %dx, %eax
+# CHECK-NEXT: 1 1 0.33 incb %dil
+# CHECK-NEXT: 4 13 0.50 * * incb (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock incb (%rax)
+# CHECK-NEXT: 1 1 0.33 incw %di
+# CHECK-NEXT: 4 12 0.67 * * incw (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock incw (%rax)
+# CHECK-NEXT: 1 1 0.33 incl %edi
+# CHECK-NEXT: 4 12 0.67 * * incl (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock incl (%rax)
+# CHECK-NEXT: 0 1 0.00 incq %rdi
+# CHECK-NEXT: 4 12 0.67 * * incq (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock incq (%rax)
+# CHECK-NEXT: 1 100 0.17 U insb %dx, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.17 U insw %dx, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.17 U insl %dx, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.17 * * U int $7
+# CHECK-NEXT: 1 100 0.17 U invlpg (%rax)
+# CHECK-NEXT: 1 100 0.17 U invlpga
+# CHECK-NEXT: 1 1 0.33 * leave
+# CHECK-NEXT: 1 100 0.17 U lodsb (%rsi), %al
+# CHECK-NEXT: 1 100 0.17 U lodsw (%rsi), %ax
+# CHECK-NEXT: 1 100 0.17 U lodsl (%rsi), %eax
+# CHECK-NEXT: 1 100 0.17 U lodsq (%rsi), %rax
+# CHECK-NEXT: 1 1 0.33 U loop 0
+# CHECK-NEXT: 11 3 2.00 U loope 0
+# CHECK-NEXT: 11 2 2.00 U loopne 0
+# CHECK-NEXT: 7 8 0.67 U movsb (%rsi), %es:(%rdi)
+# CHECK-NEXT: 7 7 0.67 U movsw (%rsi), %es:(%rdi)
+# CHECK-NEXT: 7 7 0.67 U movsl (%rsi), %es:(%rdi)
+# CHECK-NEXT: 7 7 0.67 U movsq (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 1 0.33 movsbw %al, %di
+# CHECK-NEXT: 1 1 0.33 movzbw %al, %di
+# CHECK-NEXT: 2 6 0.33 * movsbw (%rax), %di
+# CHECK-NEXT: 2 6 0.33 * movzbw (%rax), %di
+# CHECK-NEXT: 1 1 0.33 movsbl %al, %edi
+# CHECK-NEXT: 1 0 0.17 movzbl %al, %edi
+# CHECK-NEXT: 1 6 0.33 * movsbl (%rax), %edi
+# CHECK-NEXT: 1 4 0.33 * movzbl (%rax), %edi
+# CHECK-NEXT: 1 1 0.33 movsbq %al, %rdi
+# CHECK-NEXT: 1 0 0.17 movzbq %al, %rdi
+# CHECK-NEXT: 1 6 0.33 * movsbq (%rax), %rdi
+# CHECK-NEXT: 1 4 0.33 * movzbq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.33 movswl %ax, %edi
+# CHECK-NEXT: 1 1 0.33 movzwl %ax, %edi
+# CHECK-NEXT: 1 6 0.33 * movswl (%rax), %edi
+# CHECK-NEXT: 1 4 0.33 * movzwl (%rax), %edi
+# CHECK-NEXT: 1 1 0.33 movswq %ax, %rdi
+# CHECK-NEXT: 1 1 0.33 movzwq %ax, %rdi
+# CHECK-NEXT: 1 6 0.33 * movswq (%rax), %rdi
+# CHECK-NEXT: 1 4 0.33 * movzwq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.33 movslq %eax, %rdi
+# CHECK-NEXT: 1 6 0.33 * movslq (%rax), %rdi
+# CHECK-NEXT: 1 3 0.33 mulb %dil
+# CHECK-NEXT: 2 7 0.33 * mulb (%rax)
+# CHECK-NEXT: 4 5 0.67 mulw %si
+# CHECK-NEXT: 5 9 0.67 * mulw (%rax)
+# CHECK-NEXT: 3 4 0.33 mull %edx
+# CHECK-NEXT: 4 8 0.33 * mull (%rax)
+# CHECK-NEXT: 2 4 0.33 mulq %rcx
+# CHECK-NEXT: 3 8 0.33 * mulq (%rax)
+# CHECK-NEXT: 1 1 0.33 negb %dil
+# CHECK-NEXT: 4 13 0.50 * * negb (%r8)
+# CHECK-NEXT: 4 13 0.50 * * lock negb (%r8)
+# CHECK-NEXT: 1 1 0.33 negw %si
+# CHECK-NEXT: 4 12 0.67 * * negw (%r9)
+# CHECK-NEXT: 4 12 0.67 * * lock negw (%r9)
+# CHECK-NEXT: 1 1 0.33 negl %edx
+# CHECK-NEXT: 4 12 0.67 * * negl (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock negl (%rax)
+# CHECK-NEXT: 1 1 0.33 negq %rcx
+# CHECK-NEXT: 4 12 0.67 * * negq (%r10)
+# CHECK-NEXT: 4 12 0.67 * * lock negq (%r10)
+# CHECK-NEXT: 0 1 0.00 nop
+# CHECK-NEXT: 0 1 0.00 nopw %di
+# CHECK-NEXT: 0 1 0.00 nopw (%rcx)
+# CHECK-NEXT: 0 1 0.00 nopl %esi
+# CHECK-NEXT: 0 1 0.00 nopl (%r8)
+# CHECK-NEXT: 0 1 0.00 nopq %rdx
+# CHECK-NEXT: 0 1 0.00 nopq (%r9)
+# CHECK-NEXT: 1 1 0.33 notb %dil
+# CHECK-NEXT: 4 13 0.50 * * notb (%r8)
+# CHECK-NEXT: 4 13 0.50 * * lock notb (%r8)
+# CHECK-NEXT: 1 1 0.33 notw %si
+# CHECK-NEXT: 4 12 0.67 * * notw (%r9)
+# CHECK-NEXT: 4 12 0.67 * * lock notw (%r9)
+# CHECK-NEXT: 1 1 0.33 notl %edx
+# CHECK-NEXT: 4 12 0.67 * * notl (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock notl (%rax)
+# CHECK-NEXT: 1 1 0.33 notq %rcx
+# CHECK-NEXT: 4 12 0.67 * * notq (%r10)
+# CHECK-NEXT: 4 12 0.67 * * lock notq (%r10)
+# CHECK-NEXT: 1 2 0.17 orb $7, %al
+# CHECK-NEXT: 1 2 0.17 orb $7, %dil
+# CHECK-NEXT: 4 13 0.50 * * orb $7, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock orb $7, (%rax)
+# CHECK-NEXT: 1 2 0.17 orb %sil, %dil
+# CHECK-NEXT: 4 13 0.50 * * orb %sil, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock orb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.33 * orb (%rax), %dil
+# CHECK-NEXT: 1 1 0.33 orw $511, %ax
+# CHECK-NEXT: 1 1 0.33 orw $511, %di
+# CHECK-NEXT: 4 12 0.67 * * orw $511, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock orw $511, (%rax)
+# CHECK-NEXT: 1 2 0.17 orw $7, %di
+# CHECK-NEXT: 4 12 0.67 * * orw $7, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock orw $7, (%rax)
+# CHECK-NEXT: 1 2 0.17 orw %si, %di
+# CHECK-NEXT: 4 12 0.67 * * orw %si, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock orw %si, (%rax)
+# CHECK-NEXT: 2 6 0.33 * orw (%rax), %di
+# CHECK-NEXT: 1 2 0.17 orl $665536, %eax
+# CHECK-NEXT: 1 2 0.17 orl $665536, %edi
+# CHECK-NEXT: 4 12 0.67 * * orl $665536, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock orl $665536, (%rax)
+# CHECK-NEXT: 1 2 0.17 orl $7, %edi
+# CHECK-NEXT: 4 12 0.67 * * orl $7, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock orl $7, (%rax)
+# CHECK-NEXT: 1 2 0.17 orl %esi, %edi
+# CHECK-NEXT: 4 12 0.67 * * orl %esi, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock orl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * orl (%rax), %edi
+# CHECK-NEXT: 1 2 0.17 orq $665536, %rax
+# CHECK-NEXT: 1 2 0.17 orq $665536, %rdi
+# CHECK-NEXT: 4 12 0.67 * * orq $665536, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock orq $665536, (%rax)
+# CHECK-NEXT: 1 2 0.17 orq $7, %rdi
+# CHECK-NEXT: 4 12 0.67 * * orq $7, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock orq $7, (%rax)
+# CHECK-NEXT: 1 2 0.17 orq %rsi, %rdi
+# CHECK-NEXT: 4 12 0.67 * * orq %rsi, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock orq %rsi, (%rax)
+# CHECK-NEXT: 2 7 0.33 * orq (%rax), %rdi
+# CHECK-NEXT: 1 100 0.17 U outb %al, $7
+# CHECK-NEXT: 1 100 0.17 U outb %al, %dx
+# CHECK-NEXT: 1 100 0.17 U outw %ax, $7
+# CHECK-NEXT: 1 100 0.17 U outw %ax, %dx
+# CHECK-NEXT: 1 100 0.17 U outl %eax, $7
+# CHECK-NEXT: 1 100 0.17 U outl %eax, %dx
+# CHECK-NEXT: 1 100 0.17 U outsb (%rsi), %dx
+# CHECK-NEXT: 1 100 0.17 U outsw (%rsi), %dx
+# CHECK-NEXT: 1 100 0.17 U outsl (%rsi), %dx
+# CHECK-NEXT: 0 1 0.00 * * U pause
+# CHECK-NEXT: 3 2 0.67 rclb %dil
+# CHECK-NEXT: 3 2 0.67 rcrb %dil
+# CHECK-NEXT: 6 13 0.67 * * rclb (%rax)
+# CHECK-NEXT: 6 13 0.67 * * rcrb (%rax)
+# CHECK-NEXT: 3 2 0.67 rclb $7, %dil
+# CHECK-NEXT: 3 2 0.67 rcrb $7, %dil
+# CHECK-NEXT: 6 13 0.67 * * rclb $7, (%rax)
+# CHECK-NEXT: 6 13 0.67 * * rcrb $7, (%rax)
+# CHECK-NEXT: 9 7 1.67 rclb %cl, %dil
+# CHECK-NEXT: 10 9 1.67 rcrb %cl, %dil
+# CHECK-NEXT: 11 20 1.67 * * rclb %cl, (%rax)
+# CHECK-NEXT: 12 20 1.50 * * rcrb %cl, (%rax)
+# CHECK-NEXT: 3 2 0.67 rclw %di
+# CHECK-NEXT: 3 2 0.67 rcrw %di
+# CHECK-NEXT: 6 12 0.67 * * rclw (%rax)
+# CHECK-NEXT: 6 12 0.67 * * rcrw (%rax)
+# CHECK-NEXT: 3 2 0.67 rclw $7, %di
+# CHECK-NEXT: 3 2 0.67 rcrw $7, %di
+# CHECK-NEXT: 6 12 0.67 * * rclw $7, (%rax)
+# CHECK-NEXT: 6 12 0.67 * * rcrw $7, (%rax)
+# CHECK-NEXT: 7 8 1.17 rclw %cl, %di
+# CHECK-NEXT: 7 8 1.17 rcrw %cl, %di
+# CHECK-NEXT: 10 19 1.67 * * rclw %cl, (%rax)
+# CHECK-NEXT: 10 19 1.67 * * rcrw %cl, (%rax)
+# CHECK-NEXT: 3 2 0.67 rcll %edi
+# CHECK-NEXT: 3 2 0.67 rcrl %edi
+# CHECK-NEXT: 6 12 0.67 * * rcll (%rax)
+# CHECK-NEXT: 6 12 0.67 * * rcrl (%rax)
+# CHECK-NEXT: 3 2 0.67 rcll $7, %edi
+# CHECK-NEXT: 3 2 0.67 rcrl $7, %edi
+# CHECK-NEXT: 6 12 0.67 * * rcll $7, (%rax)
+# CHECK-NEXT: 6 12 0.67 * * rcrl $7, (%rax)
+# CHECK-NEXT: 7 8 1.17 rcll %cl, %edi
+# CHECK-NEXT: 7 8 1.17 rcrl %cl, %edi
+# CHECK-NEXT: 10 19 1.67 * * rcll %cl, (%rax)
+# CHECK-NEXT: 10 19 1.67 * * rcrl %cl, (%rax)
+# CHECK-NEXT: 3 2 0.67 rclq %rdi
+# CHECK-NEXT: 3 2 0.67 rcrq %rdi
+# CHECK-NEXT: 6 12 0.67 * * rclq (%rax)
+# CHECK-NEXT: 6 12 0.67 * * rcrq (%rax)
+# CHECK-NEXT: 3 2 0.67 rclq $7, %rdi
+# CHECK-NEXT: 3 2 0.67 rcrq $7, %rdi
+# CHECK-NEXT: 6 12 0.67 * * rclq $7, (%rax)
+# CHECK-NEXT: 6 12 0.67 * * rcrq $7, (%rax)
+# CHECK-NEXT: 7 8 1.17 rclq %cl, %rdi
+# CHECK-NEXT: 7 8 1.17 rcrq %cl, %rdi
+# CHECK-NEXT: 10 19 1.67 * * rclq %cl, (%rax)
+# CHECK-NEXT: 10 19 1.67 * * rcrq %cl, (%rax)
+# CHECK-NEXT: 1 100 0.17 U rdmsr
+# CHECK-NEXT: 1 100 0.17 U rdpmc
+# CHECK-NEXT: 15 18 2.50 U rdtsc
+# CHECK-NEXT: 1 100 0.17 U rdtscp
+# CHECK-NEXT: 2 1 0.67 rolb %dil
+# CHECK-NEXT: 2 1 0.67 rorb %dil
+# CHECK-NEXT: 5 13 0.67 * * rolb (%rax)
+# CHECK-NEXT: 5 13 0.67 * * rorb (%rax)
+# CHECK-NEXT: 2 1 0.67 rolb $7, %dil
+# CHECK-NEXT: 2 1 0.67 rorb $7, %dil
+# CHECK-NEXT: 5 13 0.67 * * rolb $7, (%rax)
+# CHECK-NEXT: 5 13 0.67 * * rorb $7, (%rax)
+# CHECK-NEXT: 2 2 0.67 rolb %cl, %dil
+# CHECK-NEXT: 2 2 0.67 rorb %cl, %dil
+# CHECK-NEXT: 5 13 0.67 * * rolb %cl, (%rax)
+# CHECK-NEXT: 5 13 0.67 * * rorb %cl, (%rax)
+# CHECK-NEXT: 2 1 0.67 rolw %di
+# CHECK-NEXT: 2 1 0.67 rorw %di
+# CHECK-NEXT: 5 12 0.67 * * rolw (%rax)
+# CHECK-NEXT: 5 12 0.67 * * rorw (%rax)
+# CHECK-NEXT: 2 1 0.67 rolw $7, %di
+# CHECK-NEXT: 2 1 0.67 rorw $7, %di
+# CHECK-NEXT: 5 12 0.67 * * rolw $7, (%rax)
+# CHECK-NEXT: 5 12 0.67 * * rorw $7, (%rax)
+# CHECK-NEXT: 2 2 0.67 rolw %cl, %di
+# CHECK-NEXT: 2 2 0.67 rorw %cl, %di
+# CHECK-NEXT: 5 12 0.67 * * rolw %cl, (%rax)
+# CHECK-NEXT: 5 12 0.67 * * rorw %cl, (%rax)
+# CHECK-NEXT: 2 1 0.67 roll %edi
+# CHECK-NEXT: 2 1 0.67 rorl %edi
+# CHECK-NEXT: 5 12 0.67 * * roll (%rax)
+# CHECK-NEXT: 5 12 0.67 * * rorl (%rax)
+# CHECK-NEXT: 2 1 0.67 roll $7, %edi
+# CHECK-NEXT: 2 1 0.67 rorl $7, %edi
+# CHECK-NEXT: 5 12 0.67 * * roll $7, (%rax)
+# CHECK-NEXT: 5 12 0.67 * * rorl $7, (%rax)
+# CHECK-NEXT: 2 2 0.67 roll %cl, %edi
+# CHECK-NEXT: 2 2 0.67 rorl %cl, %edi
+# CHECK-NEXT: 5 12 0.67 * * roll %cl, (%rax)
+# CHECK-NEXT: 5 12 0.67 * * rorl %cl, (%rax)
+# CHECK-NEXT: 2 1 0.67 rolq %rdi
+# CHECK-NEXT: 2 1 0.67 rorq %rdi
+# CHECK-NEXT: 5 12 0.67 * * rolq (%rax)
+# CHECK-NEXT: 5 12 0.67 * * rorq (%rax)
+# CHECK-NEXT: 2 1 0.67 rolq $7, %rdi
+# CHECK-NEXT: 2 1 0.67 rorq $7, %rdi
+# CHECK-NEXT: 5 12 0.67 * * rolq $7, (%rax)
+# CHECK-NEXT: 5 12 0.67 * * rorq $7, (%rax)
+# CHECK-NEXT: 2 2 0.67 rolq %cl, %rdi
+# CHECK-NEXT: 2 2 0.67 rorq %cl, %rdi
+# CHECK-NEXT: 5 12 0.67 * * rolq %cl, (%rax)
+# CHECK-NEXT: 5 12 0.67 * * rorq %cl, (%rax)
+# CHECK-NEXT: 2 4 0.67 sahf
+# CHECK-NEXT: 1 1 0.33 sarb %dil
+# CHECK-NEXT: 1 1 0.33 shlb %dil
+# CHECK-NEXT: 1 1 0.33 shrb %dil
+# CHECK-NEXT: 4 13 0.50 * * sarb (%rax)
+# CHECK-NEXT: 4 13 0.50 * * shlb (%rax)
+# CHECK-NEXT: 4 13 0.50 * * shrb (%rax)
+# CHECK-NEXT: 1 1 0.33 sarb $7, %dil
+# CHECK-NEXT: 1 1 0.33 shlb $7, %dil
+# CHECK-NEXT: 1 1 0.33 shrb $7, %dil
+# CHECK-NEXT: 4 13 0.50 * * sarb $7, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * shlb $7, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * shrb $7, (%rax)
+# CHECK-NEXT: 2 2 0.67 sarb %cl, %dil
+# CHECK-NEXT: 2 2 0.67 shlb %cl, %dil
+# CHECK-NEXT: 2 2 0.67 shrb %cl, %dil
+# CHECK-NEXT: 5 13 0.67 * * sarb %cl, (%rax)
+# CHECK-NEXT: 5 13 0.67 * * shlb %cl, (%rax)
+# CHECK-NEXT: 5 13 0.67 * * shrb %cl, (%rax)
+# CHECK-NEXT: 1 1 0.33 sarw %di
+# CHECK-NEXT: 1 1 0.33 shlw %di
+# CHECK-NEXT: 1 1 0.33 shrw %di
+# CHECK-NEXT: 5 5 1.67 * * sarw (%rax)
+# CHECK-NEXT: 5 5 1.67 * * shlw (%rax)
+# CHECK-NEXT: 5 5 1.67 * * shrw (%rax)
+# CHECK-NEXT: 1 1 0.33 sarw $7, %di
+# CHECK-NEXT: 1 1 0.33 shlw $7, %di
+# CHECK-NEXT: 1 1 0.33 shrw $7, %di
+# CHECK-NEXT: 5 5 1.67 * * sarw $7, (%rax)
+# CHECK-NEXT: 5 5 1.67 * * shlw $7, (%rax)
+# CHECK-NEXT: 5 5 1.67 * * shrw $7, (%rax)
+# CHECK-NEXT: 2 2 0.67 sarw %cl, %di
+# CHECK-NEXT: 2 2 0.67 shlw %cl, %di
+# CHECK-NEXT: 2 2 0.67 shrw %cl, %di
+# CHECK-NEXT: 5 12 0.67 * * sarw %cl, (%rax)
+# CHECK-NEXT: 5 12 0.67 * * shlw %cl, (%rax)
+# CHECK-NEXT: 5 12 0.67 * * shrw %cl, (%rax)
+# CHECK-NEXT: 1 1 0.33 sarl %edi
+# CHECK-NEXT: 1 1 0.33 shll %edi
+# CHECK-NEXT: 1 1 0.33 shrl %edi
+# CHECK-NEXT: 5 5 1.67 * * sarl (%rax)
+# CHECK-NEXT: 5 5 1.67 * * shll (%rax)
+# CHECK-NEXT: 5 5 1.67 * * shrl (%rax)
+# CHECK-NEXT: 1 1 0.33 sarl $7, %edi
+# CHECK-NEXT: 1 1 0.33 shll $7, %edi
+# CHECK-NEXT: 1 1 0.33 shrl $7, %edi
+# CHECK-NEXT: 5 5 1.67 * * sarl $7, (%rax)
+# CHECK-NEXT: 5 5 1.67 * * shll $7, (%rax)
+# CHECK-NEXT: 5 5 1.67 * * shrl $7, (%rax)
+# CHECK-NEXT: 2 2 0.67 sarl %cl, %edi
+# CHECK-NEXT: 2 2 0.67 shll %cl, %edi
+# CHECK-NEXT: 2 2 0.67 shrl %cl, %edi
+# CHECK-NEXT: 5 12 0.67 * * sarl %cl, (%rax)
+# CHECK-NEXT: 5 12 0.67 * * shll %cl, (%rax)
+# CHECK-NEXT: 5 12 0.67 * * shrl %cl, (%rax)
+# CHECK-NEXT: 1 1 0.33 sarq %rdi
+# CHECK-NEXT: 1 1 0.33 shlq %rdi
+# CHECK-NEXT: 1 1 0.33 shrq %rdi
+# CHECK-NEXT: 5 5 1.67 * * sarq (%rax)
+# CHECK-NEXT: 5 5 1.67 * * shlq (%rax)
+# CHECK-NEXT: 5 5 1.67 * * shrq (%rax)
+# CHECK-NEXT: 1 1 0.33 sarq $7, %rdi
+# CHECK-NEXT: 1 1 0.33 shlq $7, %rdi
+# CHECK-NEXT: 1 1 0.33 shrq $7, %rdi
+# CHECK-NEXT: 5 5 1.67 * * sarq $7, (%rax)
+# CHECK-NEXT: 5 5 1.67 * * shlq $7, (%rax)
+# CHECK-NEXT: 5 5 1.67 * * shrq $7, (%rax)
+# CHECK-NEXT: 2 2 0.67 sarq %cl, %rdi
+# CHECK-NEXT: 2 2 0.67 shlq %cl, %rdi
+# CHECK-NEXT: 2 2 0.67 shrq %cl, %rdi
+# CHECK-NEXT: 5 12 0.67 * * sarq %cl, (%rax)
+# CHECK-NEXT: 5 12 0.67 * * shlq %cl, (%rax)
+# CHECK-NEXT: 5 12 0.67 * * shrq %cl, (%rax)
+# CHECK-NEXT: 1 1 0.33 sbbb $0, %al
+# CHECK-NEXT: 1 1 0.33 sbbb $0, %dil
+# CHECK-NEXT: 5 12 0.50 * * sbbb $0, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbb $0, (%rax)
+# CHECK-NEXT: 1 1 0.33 sbbb $7, %al
+# CHECK-NEXT: 1 1 0.33 sbbb $7, %dil
+# CHECK-NEXT: 5 12 0.50 * * sbbb $7, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbb $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 sbbb %sil, %dil
+# CHECK-NEXT: 5 12 0.50 * * sbbb %sil, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.33 * sbbb (%rax), %dil
+# CHECK-NEXT: 1 1 0.33 sbbw $0, %ax
+# CHECK-NEXT: 1 1 0.33 sbbw $0, %di
+# CHECK-NEXT: 5 12 0.50 * * sbbw $0, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbw $0, (%rax)
+# CHECK-NEXT: 1 1 0.33 sbbw $511, %ax
+# CHECK-NEXT: 1 1 0.33 sbbw $511, %di
+# CHECK-NEXT: 5 12 0.50 * * sbbw $511, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbw $511, (%rax)
+# CHECK-NEXT: 1 1 0.33 sbbw $7, %di
+# CHECK-NEXT: 5 12 0.50 * * sbbw $7, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbw $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 sbbw %si, %di
+# CHECK-NEXT: 6 12 0.50 * * sbbw %si, (%rax)
+# CHECK-NEXT: 6 12 0.50 * * lock sbbw %si, (%rax)
+# CHECK-NEXT: 2 6 0.33 * sbbw (%rax), %di
+# CHECK-NEXT: 1 1 0.33 sbbl $0, %eax
+# CHECK-NEXT: 1 1 0.33 sbbl $0, %edi
+# CHECK-NEXT: 5 12 0.50 * * sbbl $0, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbl $0, (%rax)
+# CHECK-NEXT: 1 1 0.33 sbbl $665536, %eax
+# CHECK-NEXT: 1 1 0.33 sbbl $665536, %edi
+# CHECK-NEXT: 5 12 0.50 * * sbbl $665536, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.33 sbbl $7, %edi
+# CHECK-NEXT: 5 12 0.50 * * sbbl $7, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbl $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 sbbl %esi, %edi
+# CHECK-NEXT: 6 12 0.50 * * sbbl %esi, (%rax)
+# CHECK-NEXT: 6 12 0.50 * * lock sbbl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * sbbl (%rax), %edi
+# CHECK-NEXT: 1 1 0.33 sbbq $0, %rax
+# CHECK-NEXT: 1 1 0.33 sbbq $0, %rdi
+# CHECK-NEXT: 5 12 0.50 * * sbbq $0, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbq $0, (%rax)
+# CHECK-NEXT: 1 1 0.33 sbbq $665536, %rax
+# CHECK-NEXT: 1 1 0.33 sbbq $665536, %rdi
+# CHECK-NEXT: 5 12 0.50 * * sbbq $665536, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.33 sbbq $7, %rdi
+# CHECK-NEXT: 5 12 0.50 * * sbbq $7, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbq $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 sbbq %rsi, %rdi
+# CHECK-NEXT: 6 12 0.50 * * sbbq %rsi, (%rax)
+# CHECK-NEXT: 6 12 0.50 * * lock sbbq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * sbbq (%rax), %rdi
+# CHECK-NEXT: 1 100 0.17 U scasb %es:(%rdi), %al
+# CHECK-NEXT: 1 100 0.17 U scasw %es:(%rdi), %ax
+# CHECK-NEXT: 1 100 0.17 U scasl %es:(%rdi), %eax
+# CHECK-NEXT: 1 100 0.17 U scasq %es:(%rdi), %rax
+# CHECK-NEXT: 2 2 0.67 seto %al
+# CHECK-NEXT: 4 13 0.67 * seto (%rax)
+# CHECK-NEXT: 2 2 0.67 setno %al
+# CHECK-NEXT: 4 13 0.67 * setno (%rax)
+# CHECK-NEXT: 2 2 0.67 setb %al
+# CHECK-NEXT: 4 13 0.67 * setb (%rax)
+# CHECK-NEXT: 2 2 0.67 setae %al
+# CHECK-NEXT: 4 13 0.67 * setae (%rax)
+# CHECK-NEXT: 2 2 0.67 sete %al
+# CHECK-NEXT: 4 13 0.67 * sete (%rax)
+# CHECK-NEXT: 2 2 0.67 setne %al
+# CHECK-NEXT: 4 13 0.67 * setne (%rax)
+# CHECK-NEXT: 2 2 0.67 seta %al
+# CHECK-NEXT: 4 13 0.67 * seta (%rax)
+# CHECK-NEXT: 2 2 0.67 setbe %al
+# CHECK-NEXT: 4 13 0.67 * setbe (%rax)
+# CHECK-NEXT: 2 2 0.67 sets %al
+# CHECK-NEXT: 4 13 0.67 * sets (%rax)
+# CHECK-NEXT: 2 2 0.67 setns %al
+# CHECK-NEXT: 4 13 0.67 * setns (%rax)
+# CHECK-NEXT: 2 2 0.67 setp %al
+# CHECK-NEXT: 4 13 0.67 * setp (%rax)
+# CHECK-NEXT: 2 2 0.67 setnp %al
+# CHECK-NEXT: 4 13 0.67 * setnp (%rax)
+# CHECK-NEXT: 2 2 0.67 setl %al
+# CHECK-NEXT: 4 13 0.67 * setl (%rax)
+# CHECK-NEXT: 2 2 0.67 setge %al
+# CHECK-NEXT: 4 13 0.67 * setge (%rax)
+# CHECK-NEXT: 2 2 0.67 setg %al
+# CHECK-NEXT: 4 13 0.67 * setg (%rax)
+# CHECK-NEXT: 2 2 0.67 setle %al
+# CHECK-NEXT: 4 13 0.67 * setle (%rax)
+# CHECK-NEXT: 3 5 0.67 shldw %cl, %si, %di
+# CHECK-NEXT: 3 5 0.67 shrdw %cl, %si, %di
+# CHECK-NEXT: 6 12 0.67 * * shldw %cl, %si, (%rax)
+# CHECK-NEXT: 6 12 0.67 * * shrdw %cl, %si, (%rax)
+# CHECK-NEXT: 1 3 0.33 shldw $7, %si, %di
+# CHECK-NEXT: 1 3 0.33 shrdw $7, %si, %di
+# CHECK-NEXT: 5 12 0.50 * * shldw $7, %si, (%rax)
+# CHECK-NEXT: 5 13 0.50 * * shrdw $7, %si, (%rax)
+# CHECK-NEXT: 3 5 0.67 shldl %cl, %esi, %edi
+# CHECK-NEXT: 3 5 0.67 shrdl %cl, %esi, %edi
+# CHECK-NEXT: 6 12 0.67 * * shldl %cl, %esi, (%rax)
+# CHECK-NEXT: 6 12 0.67 * * shrdl %cl, %esi, (%rax)
+# CHECK-NEXT: 1 3 0.33 shldl $7, %esi, %edi
+# CHECK-NEXT: 1 3 0.33 shrdl $7, %esi, %edi
+# CHECK-NEXT: 5 12 0.50 * * shldl $7, %esi, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * shrdl $7, %esi, (%rax)
+# CHECK-NEXT: 3 5 0.67 shldq %cl, %rsi, %rdi
+# CHECK-NEXT: 3 5 0.67 shrdq %cl, %rsi, %rdi
+# CHECK-NEXT: 6 12 0.67 * * shldq %cl, %rsi, (%rax)
+# CHECK-NEXT: 6 12 0.67 * * shrdq %cl, %rsi, (%rax)
+# CHECK-NEXT: 1 3 0.33 shldq $7, %rsi, %rdi
+# CHECK-NEXT: 1 3 0.33 shrdq $7, %rsi, %rdi
+# CHECK-NEXT: 5 12 0.50 * * shldq $7, %rsi, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * shrdq $7, %rsi, (%rax)
+# CHECK-NEXT: 1 1 0.33 U stc
+# CHECK-NEXT: 2 6 0.33 U std
+# CHECK-NEXT: 4 8 0.50 U stosb %al, %es:(%rdi)
+# CHECK-NEXT: 4 7 0.50 U stosw %ax, %es:(%rdi)
+# CHECK-NEXT: 4 7 0.50 U stosl %eax, %es:(%rdi)
+# CHECK-NEXT: 4 7 0.50 U stosq %rax, %es:(%rdi)
+# CHECK-NEXT: 1 1 0.33 subb $7, %al
+# CHECK-NEXT: 1 1 0.33 subb $7, %dil
+# CHECK-NEXT: 4 13 0.50 * * subb $7, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock subb $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 subb %sil, %dil
+# CHECK-NEXT: 4 13 0.50 * * subb %sil, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock subb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.33 * subb (%rax), %dil
+# CHECK-NEXT: 1 1 0.33 subw $511, %ax
+# CHECK-NEXT: 1 1 0.33 subw $511, %di
+# CHECK-NEXT: 4 12 0.67 * * subw $511, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock subw $511, (%rax)
+# CHECK-NEXT: 1 1 0.33 subw $7, %di
+# CHECK-NEXT: 4 12 0.67 * * subw $7, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock subw $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 subw %si, %di
+# CHECK-NEXT: 4 12 0.67 * * subw %si, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock subw %si, (%rax)
+# CHECK-NEXT: 2 6 0.33 * subw (%rax), %di
+# CHECK-NEXT: 1 1 0.33 subl $665536, %eax
+# CHECK-NEXT: 1 1 0.33 subl $665536, %edi
+# CHECK-NEXT: 4 12 0.67 * * subl $665536, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock subl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.33 subl $7, %edi
+# CHECK-NEXT: 4 12 0.67 * * subl $7, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock subl $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 subl %esi, %edi
+# CHECK-NEXT: 4 12 0.67 * * subl %esi, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock subl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * subl (%rax), %edi
+# CHECK-NEXT: 1 1 0.33 subq $665536, %rax
+# CHECK-NEXT: 1 1 0.33 subq $665536, %rdi
+# CHECK-NEXT: 4 12 0.67 * * subq $665536, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock subq $665536, (%rax)
+# CHECK-NEXT: 0 1 0.00 subq $7, %rdi
+# CHECK-NEXT: 4 12 0.67 * * subq $7, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock subq $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 subq %rsi, %rdi
+# CHECK-NEXT: 4 12 0.67 * * subq %rsi, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock subq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * subq (%rax), %rdi
+# CHECK-NEXT: 1 2 0.17 testb $7, %al
+# CHECK-NEXT: 1 2 0.17 testb $7, %dil
+# CHECK-NEXT: 2 7 0.33 * testb $7, (%rax)
+# CHECK-NEXT: 1 2 0.17 testb %sil, %dil
+# CHECK-NEXT: 2 7 0.33 * testb %sil, (%rax)
+# CHECK-NEXT: 1 1 0.33 testw $511, %ax
+# CHECK-NEXT: 1 1 0.33 testw $511, %di
+# CHECK-NEXT: 2 7 0.33 * testw $511, (%rax)
+# CHECK-NEXT: 1 1 0.33 testw $7, %di
+# CHECK-NEXT: 2 7 0.33 * testw $7, (%rax)
+# CHECK-NEXT: 1 2 0.17 testw %si, %di
+# CHECK-NEXT: 2 7 0.33 * testw %si, (%rax)
+# CHECK-NEXT: 1 2 0.17 testl $665536, %eax
+# CHECK-NEXT: 1 2 0.17 testl $665536, %edi
+# CHECK-NEXT: 2 7 0.33 * testl $665536, (%rax)
+# CHECK-NEXT: 1 2 0.17 testl $7, %edi
+# CHECK-NEXT: 2 7 0.33 * testl $7, (%rax)
+# CHECK-NEXT: 1 2 0.17 testl %esi, %edi
+# CHECK-NEXT: 2 7 0.33 * testl %esi, (%rax)
+# CHECK-NEXT: 1 2 0.17 testq $665536, %rax
+# CHECK-NEXT: 1 2 0.17 testq $665536, %rdi
+# CHECK-NEXT: 2 7 0.33 * testq $665536, (%rax)
+# CHECK-NEXT: 1 2 0.17 testq $7, %rdi
+# CHECK-NEXT: 2 7 0.33 * testq $7, (%rax)
+# CHECK-NEXT: 1 2 0.17 testq %rsi, %rdi
+# CHECK-NEXT: 2 7 0.33 * testq %rsi, (%rax)
+# CHECK-NEXT: 1 100 0.17 * U ud2
+# CHECK-NEXT: 144 100 21.00 U wrmsr
+# CHECK-NEXT: 3 2 0.50 xaddb %bl, %cl
+# CHECK-NEXT: 5 13 0.50 * * xaddb %bl, (%rcx)
+# CHECK-NEXT: 5 13 0.50 * * lock xaddb %bl, (%rcx)
+# CHECK-NEXT: 3 2 0.50 xaddw %bx, %cx
+# CHECK-NEXT: 5 12 0.50 * * xaddw %ax, (%rbx)
+# CHECK-NEXT: 5 12 0.50 * * lock xaddw %ax, (%rbx)
+# CHECK-NEXT: 3 2 0.50 xaddl %ebx, %ecx
+# CHECK-NEXT: 5 12 0.50 * * xaddl %eax, (%rbx)
+# CHECK-NEXT: 5 12 0.50 * * lock xaddl %eax, (%rbx)
+# CHECK-NEXT: 3 2 0.50 xaddq %rbx, %rcx
+# CHECK-NEXT: 5 12 0.50 * * xaddq %rax, (%rbx)
+# CHECK-NEXT: 5 12 0.50 * * lock xaddq %rax, (%rbx)
+# CHECK-NEXT: 3 2 0.50 xchgb %bl, %cl
+# CHECK-NEXT: 8 40 0.83 * * xchgb %bl, (%rbx)
+# CHECK-NEXT: 8 40 0.83 * * lock xchgb %bl, (%rbx)
+# CHECK-NEXT: 3 2 0.50 xchgw %bx, %ax
+# CHECK-NEXT: 3 2 0.50 xchgw %bx, %cx
+# CHECK-NEXT: 8 39 0.83 * * xchgw %ax, (%rbx)
+# CHECK-NEXT: 8 39 0.83 * * lock xchgw %ax, (%rbx)
+# CHECK-NEXT: 3 2 0.50 xchgl %ebx, %eax
+# CHECK-NEXT: 3 2 0.50 xchgl %ebx, %ecx
+# CHECK-NEXT: 8 39 0.83 * * xchgl %eax, (%rbx)
+# CHECK-NEXT: 8 39 0.83 * * lock xchgl %eax, (%rbx)
+# CHECK-NEXT: 3 2 0.50 xchgq %rbx, %rax
+# CHECK-NEXT: 3 2 0.50 xchgq %rbx, %rcx
+# CHECK-NEXT: 9 39 1.00 * * xchgq %rax, (%rbx)
+# CHECK-NEXT: 9 39 1.00 * * lock xchgq %rax, (%rbx)
+# CHECK-NEXT: 3 7 0.33 * xlatb
+# CHECK-NEXT: 1 2 0.17 xorb $7, %al
+# CHECK-NEXT: 1 2 0.17 xorb $7, %dil
+# CHECK-NEXT: 4 13 0.50 * * xorb $7, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock xorb $7, (%rax)
+# CHECK-NEXT: 1 2 0.17 xorb %sil, %dil
+# CHECK-NEXT: 4 13 0.50 * * xorb %sil, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock xorb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.33 * xorb (%rax), %dil
+# CHECK-NEXT: 1 1 0.33 xorw $511, %ax
+# CHECK-NEXT: 1 1 0.33 xorw $511, %di
+# CHECK-NEXT: 4 12 0.67 * * xorw $511, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock xorw $511, (%rax)
+# CHECK-NEXT: 1 2 0.17 xorw $7, %di
+# CHECK-NEXT: 4 12 0.67 * * xorw $7, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock xorw $7, (%rax)
+# CHECK-NEXT: 1 2 0.17 xorw %si, %di
+# CHECK-NEXT: 4 12 0.67 * * xorw %si, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock xorw %si, (%rax)
+# CHECK-NEXT: 2 6 0.33 * xorw (%rax), %di
+# CHECK-NEXT: 1 2 0.17 xorl $665536, %eax
+# CHECK-NEXT: 1 2 0.17 xorl $665536, %edi
+# CHECK-NEXT: 4 12 0.67 * * xorl $665536, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock xorl $665536, (%rax)
+# CHECK-NEXT: 1 2 0.17 xorl $7, %edi
+# CHECK-NEXT: 4 12 0.67 * * xorl $7, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock xorl $7, (%rax)
+# CHECK-NEXT: 1 2 0.17 xorl %esi, %edi
+# CHECK-NEXT: 4 12 0.67 * * xorl %esi, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock xorl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * xorl (%rax), %edi
+# CHECK-NEXT: 1 2 0.17 xorq $665536, %rax
+# CHECK-NEXT: 1 2 0.17 xorq $665536, %rdi
+# CHECK-NEXT: 4 12 0.67 * * xorq $665536, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock xorq $665536, (%rax)
+# CHECK-NEXT: 1 2 0.17 xorq $7, %rdi
+# CHECK-NEXT: 4 12 0.67 * * xorq $7, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock xorq $7, (%rax)
+# CHECK-NEXT: 1 2 0.17 xorq %rsi, %rdi
+# CHECK-NEXT: 4 12 0.67 * * xorq %rsi, (%rax)
+# CHECK-NEXT: 4 12 0.67 * * lock xorq %rsi, (%rax)
+# CHECK-NEXT: 2 7 0.33 * xorq (%rax), %rdi
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - 270.17 357.17 266.17 314.17 266.17 314.17 194.00 194.00 225.67 225.67 225.67 127.67 127.67 127.67 - 12.25 12.25 13.75 13.75
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcb $0, %al
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcb $0, %dil
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - adcb $0, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock adcb $0, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcb $7, %al
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcb $7, %dil
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - adcb $7, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock adcb $7, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcb %sil, %dil
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - adcb %sil, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock adcb %sil, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - 0.33 0.33 0.33 - - - - - - - - adcb (%rax), %dil
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcw $0, %ax
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcw $0, %di
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - adcw $0, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock adcw $0, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcw $511, %ax
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcw $511, %di
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - adcw $511, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock adcw $511, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcw $7, %di
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - adcw $7, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock adcw $7, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcw %si, %di
+# CHECK-NEXT: - 0.67 0.33 0.67 0.33 0.67 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - adcw %si, (%rax)
+# CHECK-NEXT: - 0.67 0.33 0.67 0.33 0.67 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock adcw %si, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - 0.33 0.33 0.33 - - - - - - - - adcw (%rax), %di
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcl $0, %eax
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcl $0, %edi
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - adcl $0, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock adcl $0, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcl $665536, %eax
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcl $665536, %edi
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - adcl $665536, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock adcl $665536, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcl $7, %edi
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - adcl $7, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock adcl $7, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcl %esi, %edi
+# CHECK-NEXT: - 0.67 0.33 0.67 0.33 0.67 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - adcl %esi, (%rax)
+# CHECK-NEXT: - 0.67 0.33 0.67 0.33 0.67 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock adcl %esi, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - 0.33 0.33 0.33 - - - - - - - - adcl (%rax), %edi
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcq $0, %rax
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcq $0, %rdi
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - adcq $0, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock adcq $0, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcq $665536, %rax
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcq $665536, %rdi
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - adcq $665536, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock adcq $665536, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcq $7, %rdi
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - adcq $7, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock adcq $7, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - adcq %rsi, %rdi
+# CHECK-NEXT: - 0.67 0.33 0.67 0.33 0.67 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - adcq %rsi, (%rax)
+# CHECK-NEXT: - 0.67 0.33 0.67 0.33 0.67 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock adcq %rsi, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - 0.33 0.33 0.33 - - - - - - - - adcq (%rax), %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - addb $7, %al
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - addb $7, %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - addb $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock addb $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - addb %sil, %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - addb %sil, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock addb %sil, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - addb (%rax), %dil
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - addw $511, %ax
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - addw $511, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - addw $511, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock addw $511, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - addw $7, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - addw $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock addw $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - addw %si, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - addw %si, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock addw %si, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - addw (%rax), %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - addl $665536, %eax
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - addl $665536, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - addl $665536, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock addl $665536, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - addl $7, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - addl $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock addl $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - addl %esi, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - addl %esi, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock addl %esi, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - addl (%rax), %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - addq $665536, %rax
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - addq $665536, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - addq $665536, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock addq $665536, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - addq $7, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - addq $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock addq $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - addq %rsi, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - addq %rsi, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock addq %rsi, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - addq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - andb $7, %al
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - andb $7, %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - andb $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock andb $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - andb %sil, %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - andb %sil, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock andb %sil, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - andb (%rax), %dil
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - andw $511, %ax
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - andw $511, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - andw $511, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock andw $511, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - andw $7, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - andw $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock andw $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - andw %si, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - andw %si, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock andw %si, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - andw (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - andl $665536, %eax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - andl $665536, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - andl $665536, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock andl $665536, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - andl $7, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - andl $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock andl $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - andl %esi, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - andl %esi, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock andl %esi, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - andl (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - andq $665536, %rax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - andq $665536, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - andq $665536, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock andq $665536, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - andq $7, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - andq $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock andq $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - andq %rsi, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - andq %rsi, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock andq %rsi, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - andq (%rax), %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - bsfw %si, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - bsrw %si, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - bsfw (%rax), %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - bsrw (%rax), %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - bsfl %esi, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - bsrl %esi, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - bsfl (%rax), %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - bsrl (%rax), %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - bsfq %rsi, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - bsrq %rsi, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - bsfq (%rax), %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - bsrq (%rax), %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - bswapl %eax
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - bswapq %rax
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btw %si, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btcw %si, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btrw %si, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btsw %si, %di
+# CHECK-NEXT: - 1.67 1.33 1.67 1.33 1.67 1.33 - - 0.33 0.33 0.33 - - - - - - - - btw %si, (%rax)
+# CHECK-NEXT: - 1.50 1.17 1.50 1.17 1.50 1.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btcw %si, (%rax)
+# CHECK-NEXT: - 1.50 1.17 1.50 1.17 1.50 1.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btrw %si, (%rax)
+# CHECK-NEXT: - 1.50 1.17 1.50 1.17 1.50 1.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btsw %si, (%rax)
+# CHECK-NEXT: - 1.50 1.17 1.50 1.17 1.50 1.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btcw %si, (%rax)
+# CHECK-NEXT: - 1.50 1.17 1.50 1.17 1.50 1.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btrw %si, (%rax)
+# CHECK-NEXT: - 1.50 1.17 1.50 1.17 1.50 1.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btsw %si, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btw $7, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btcw $7, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btrw $7, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btsw $7, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - btw $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btcw $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btrw $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btsw $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btcw $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btrw $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btsw $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btl %esi, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btcl %esi, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btrl %esi, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btsl %esi, %edi
+# CHECK-NEXT: - 1.67 1.33 1.67 1.33 1.67 1.33 - - 0.33 0.33 0.33 - - - - - - - - btl %esi, (%rax)
+# CHECK-NEXT: - 1.50 1.17 1.50 1.17 1.50 1.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btcl %esi, (%rax)
+# CHECK-NEXT: - 1.50 1.17 1.50 1.17 1.50 1.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btrl %esi, (%rax)
+# CHECK-NEXT: - 1.50 1.17 1.50 1.17 1.50 1.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btsl %esi, (%rax)
+# CHECK-NEXT: - 1.50 1.17 1.50 1.17 1.50 1.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btcl %esi, (%rax)
+# CHECK-NEXT: - 1.50 1.17 1.50 1.17 1.50 1.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btrl %esi, (%rax)
+# CHECK-NEXT: - 1.50 1.17 1.50 1.17 1.50 1.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btsl %esi, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btl $7, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btcl $7, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btrl $7, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btsl $7, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - btl $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btcl $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btrl $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btsl $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btcl $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btrl $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btsl $7, (%rax)
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - btq %rsi, %rdi
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - btcq %rsi, %rdi
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - btrq %rsi, %rdi
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - btsq %rsi, %rdi
+# CHECK-NEXT: - 1.50 1.83 1.50 0.83 1.50 0.83 - - 0.33 0.33 0.33 - - - - - - - - btq %rsi, (%rax)
+# CHECK-NEXT: - 1.33 1.67 1.33 0.67 1.33 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btcq %rsi, (%rax)
+# CHECK-NEXT: - 1.33 1.67 1.33 0.67 1.33 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btrq %rsi, (%rax)
+# CHECK-NEXT: - 1.33 1.67 1.33 0.67 1.33 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btsq %rsi, (%rax)
+# CHECK-NEXT: - 1.33 1.67 1.33 0.67 1.33 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btcq %rsi, (%rax)
+# CHECK-NEXT: - 1.33 1.67 1.33 0.67 1.33 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btrq %rsi, (%rax)
+# CHECK-NEXT: - 1.33 1.67 1.33 0.67 1.33 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btsq %rsi, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btq $7, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btcq $7, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btrq $7, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - btsq $7, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - btq $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btcq $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btrq $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - btsq $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btcq $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btrq $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock btsq $7, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 cbtw
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 cwtl
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 cltq
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 - - - - - - - - - - - - - cwtd
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - cltd
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - cqto
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - clc
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 - - - - - - - - - - - - - cld
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - cmc
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - cmpb $7, %al
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - cmpb $7, %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - cmpb $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - cmpb %sil, %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - cmpb %sil, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - cmpb (%rax), %dil
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - cmpw $511, %ax
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - cmpw $511, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - cmpw $511, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - cmpw $7, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - cmpw $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - cmpw %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - cmpw %si, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - cmpw (%rax), %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - cmpl $665536, %eax
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - cmpl $665536, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - cmpl $665536, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - cmpl $7, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - cmpl $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - cmpl %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - cmpl %esi, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - cmpl (%rax), %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - cmpq $665536, %rax
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - cmpq $665536, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - cmpq $665536, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - cmpq $7, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - cmpq $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - cmpq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - cmpq %rsi, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - cmpq (%rax), %rdi
+# CHECK-NEXT: - 0.83 0.83 0.83 0.83 0.83 0.83 - - 0.67 0.67 0.67 - - - - - - - - cmpsb %es:(%rdi), (%rsi)
+# CHECK-NEXT: - 0.83 0.83 0.83 0.83 0.83 0.83 - - 0.67 0.67 0.67 - - - - - - - - cmpsw %es:(%rdi), (%rsi)
+# CHECK-NEXT: - 0.83 0.83 0.83 0.83 0.83 0.83 - - 0.67 0.67 0.67 - - - - - - - - cmpsl %es:(%rdi), (%rsi)
+# CHECK-NEXT: - 0.83 0.83 0.83 0.83 0.83 0.83 - - 0.67 0.67 0.67 - - - - - - - - cmpsq %es:(%rdi), (%rsi)
+# CHECK-NEXT: - 1.17 0.50 1.17 0.50 1.17 0.50 - - - - - - - - - - - - - cmpxchgb %cl, %bl
+# CHECK-NEXT: - 0.83 0.17 0.83 0.17 0.83 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: - 0.83 0.17 0.83 0.17 0.83 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: - 1.17 0.50 1.17 0.50 1.17 0.50 - - - - - - - - - - - - - cmpxchgw %cx, %bx
+# CHECK-NEXT: - 0.83 0.17 0.83 0.17 0.83 0.17 0.50 0.50 0.67 0.67 0.67 - - - - - - - - cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: - 0.83 0.17 0.83 0.17 0.83 0.17 0.50 0.50 0.67 0.67 0.67 - - - - - - - - lock cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: - 1.17 0.50 1.17 0.50 1.17 0.50 - - - - - - - - - - - - - cmpxchgl %ecx, %ebx
+# CHECK-NEXT: - 0.83 0.17 0.83 0.17 0.83 0.17 0.50 0.50 0.67 0.67 0.67 - - - - - - - - cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: - 0.83 0.17 0.83 0.17 0.83 0.17 0.50 0.50 0.67 0.67 0.67 - - - - - - - - lock cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: - 1.17 0.50 1.17 0.50 1.17 0.50 - - - - - - - - - - - - - cmpxchgq %rcx, %rbx
+# CHECK-NEXT: - 0.83 0.17 0.83 0.17 0.83 0.17 0.50 0.50 0.67 0.67 0.67 - - - - - - - - cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: - 0.83 0.17 0.83 0.17 0.83 0.17 0.50 0.50 0.67 0.67 0.67 - - - - - - - - lock cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: - 5.33 7.67 3.33 1.67 3.33 1.67 0.50 0.50 - - - 0.33 0.33 0.33 - 0.50 0.50 - - cpuid
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - decb %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - decb (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock decb (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - decw %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - decw (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock decw (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - decl %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - decl (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock decl (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - decq %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - decq (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock decq (%rax)
+# CHECK-NEXT: - - 3.00 - - - - - - - - - - - - - - - - - divb %dil
+# CHECK-NEXT: - - 3.00 - - - - - - - - - - - - - - - - - divb (%rax)
+# CHECK-NEXT: - 0.17 3.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - divw %si
+# CHECK-NEXT: - 0.17 3.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - divw (%rax)
+# CHECK-NEXT: - 0.17 3.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - divl %edx
+# CHECK-NEXT: - 0.17 3.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - divl (%rax)
+# CHECK-NEXT: - - 3.00 - - - - - - - - - - - - - - - - - divq %rcx
+# CHECK-NEXT: - - 3.00 - - - - - - 0.33 0.33 0.33 - - - - - - - - divq (%rax)
+# CHECK-NEXT: - 9.00 5.00 7.00 3.00 7.00 3.00 2.00 2.00 4.67 4.67 4.67 1.67 1.67 1.67 - - - - - enter $7, $4095
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - - - - - - - - - - - - idivb %dil
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - - - - - - - - - - - - idivb (%rax)
+# CHECK-NEXT: - 0.17 1.17 0.17 1.17 0.17 1.17 - - - - - - - - - - - - - idivw %si
+# CHECK-NEXT: - 0.17 1.17 0.17 1.17 0.17 1.17 - - 0.33 0.33 0.33 - - - - - - - - idivw (%rax)
+# CHECK-NEXT: - 0.17 1.17 0.17 1.17 0.17 1.17 - - - - - - - - - - - - - idivl %edx
+# CHECK-NEXT: - 0.17 1.17 0.17 1.17 0.17 1.17 - - 0.33 0.33 0.33 - - - - - - - - idivl (%rax)
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - - - - - - - - - - - - idivq %rcx
+# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 - - 0.33 0.33 0.33 - - - - - - - - idivq (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - imulb %dil
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - imulb (%rax)
+# CHECK-NEXT: - 0.33 0.67 0.33 0.67 0.33 0.67 - - - - - - - - - - - - - imulw %di
+# CHECK-NEXT: - 0.33 0.67 0.33 0.67 0.33 0.67 - - 0.33 0.33 0.33 - - - - - - - - imulw (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - imulw %si, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - imulw (%rax), %di
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - imulw $511, %si, %di
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - 0.33 0.33 0.33 - - - - - - - - imulw $511, (%rax), %di
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - imulw $7, %si, %di
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - 0.33 0.33 0.33 - - - - - - - - imulw $7, (%rax), %di
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - - - - - - - - - imull %edi
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 - - 0.33 0.33 0.33 - - - - - - - - imull (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - imull %esi, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - imull (%rax), %edi
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - imull $665536, %esi, %edi
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - 0.33 0.33 0.33 - - - - - - - - imull $665536, (%rax), %edi
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - imull $7, %esi, %edi
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - 0.33 0.33 0.33 - - - - - - - - imull $7, (%rax), %edi
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - - - - - - - - - imulq %rdi
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 - - 0.33 0.33 0.33 - - - - - - - - imulq (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - imulq %rsi, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - imulq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - imulq $665536, %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - 0.33 0.33 0.33 - - - - - - - - imulq $665536, (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - - - - - - - - - - - - imulq $7, %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 - - 0.33 0.33 0.33 - - - - - - - - imulq $7, (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - inb $7, %al
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - inb %dx, %al
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - inw $7, %ax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - inw %dx, %ax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - inl $7, %eax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - inl %dx, %eax
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - incb %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - incb (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock incb (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - incw %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - incw (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock incw (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - incl %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - incl (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock incl (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - incq %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - incq (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock incq (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - insb %dx, %es:(%rdi)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - insw %dx, %es:(%rdi)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - insl %dx, %es:(%rdi)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - int $7
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - invlpg (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - invlpga
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - leave
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - lodsb (%rsi), %al
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - lodsw (%rsi), %ax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - lodsl (%rsi), %eax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - lodsq (%rsi), %rax
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - loop 0
+# CHECK-NEXT: - 2.67 1.00 2.67 1.00 2.67 1.00 - - - - - - - - - - - - - loope 0
+# CHECK-NEXT: - 2.67 1.00 2.67 1.00 2.67 1.00 - - - - - - - - - - - - - loopne 0
+# CHECK-NEXT: - 0.67 0.67 0.67 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - movsb (%rsi), %es:(%rdi)
+# CHECK-NEXT: - 0.67 0.67 0.67 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - movsw (%rsi), %es:(%rdi)
+# CHECK-NEXT: - 0.67 0.67 0.67 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - movsl (%rsi), %es:(%rdi)
+# CHECK-NEXT: - 0.67 0.67 0.67 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - movsq (%rsi), %es:(%rdi)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - movsbw %al, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - movzbw %al, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - movsbw (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - movzbw (%rax), %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - movsbl %al, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - movzbl %al, %edi
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movsbl (%rax), %edi
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movzbl (%rax), %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - movsbq %al, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - movzbq %al, %rdi
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movsbq (%rax), %rdi
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movzbq (%rax), %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - movswl %ax, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - movzwl %ax, %edi
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movswl (%rax), %edi
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movzwl (%rax), %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - movswq %ax, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - movzwq %ax, %rdi
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movswq (%rax), %rdi
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movzwq (%rax), %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - movslq %eax, %rdi
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - movslq (%rax), %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - mulb %dil
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - mulb (%rax)
+# CHECK-NEXT: - 0.33 0.67 0.33 0.67 0.33 0.67 - - - - - - - - - - - - - mulw %si
+# CHECK-NEXT: - 0.33 0.67 0.33 0.67 0.33 0.67 - - 0.33 0.33 0.33 - - - - - - - - mulw (%rax)
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - - - - - - - - - mull %edx
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 - - 0.33 0.33 0.33 - - - - - - - - mull (%rax)
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - - - - - - - - - mulq %rcx
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 - - 0.33 0.33 0.33 - - - - - - - - mulq (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - negb %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - negb (%r8)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock negb (%r8)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - negw %si
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - negw (%r9)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock negw (%r9)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - negl %edx
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - negl (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock negl (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - negq %rcx
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - negq (%r10)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock negq (%r10)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - nop
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - nopw %di
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - nopw (%rcx)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - nopl %esi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - nopl (%r8)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - nopq %rdx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - nopq (%r9)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - notb %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - notb (%r8)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock notb (%r8)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - notw %si
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - notw (%r9)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock notw (%r9)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - notl %edx
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - notl (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock notl (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - notq %rcx
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - notq (%r10)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock notq (%r10)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - orb $7, %al
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - orb $7, %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - orb $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock orb $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - orb %sil, %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - orb %sil, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock orb %sil, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - orb (%rax), %dil
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - orw $511, %ax
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - orw $511, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - orw $511, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock orw $511, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - orw $7, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - orw $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock orw $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - orw %si, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - orw %si, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock orw %si, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - orw (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - orl $665536, %eax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - orl $665536, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - orl $665536, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock orl $665536, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - orl $7, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - orl $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock orl $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - orl %esi, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - orl %esi, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock orl %esi, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - orl (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - orq $665536, %rax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - orq $665536, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - orq $665536, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock orq $665536, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - orq $7, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - orq $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock orq $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - orq %rsi, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - orq %rsi, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock orq %rsi, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - orq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - outb %al, $7
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - outb %al, %dx
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - outw %ax, $7
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - outw %ax, %dx
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - outl %eax, $7
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - outl %eax, %dx
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - outsb (%rsi), %dx
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - outsw (%rsi), %dx
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - outsl (%rsi), %dx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - pause
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - rclb %dil
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - rcrb %dil
+# CHECK-NEXT: - 0.83 0.17 0.83 0.17 0.83 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rclb (%rax)
+# CHECK-NEXT: - 0.83 0.17 0.83 0.17 0.83 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rcrb (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - rclb $7, %dil
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - rcrb $7, %dil
+# CHECK-NEXT: - 0.83 0.17 0.83 0.17 0.83 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rclb $7, (%rax)
+# CHECK-NEXT: - 0.83 0.17 0.83 0.17 0.83 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rcrb $7, (%rax)
+# CHECK-NEXT: - 2.00 1.00 2.00 1.00 2.00 1.00 - - - - - - - - - - - - - rclb %cl, %dil
+# CHECK-NEXT: - 1.83 1.50 1.83 1.50 1.83 1.50 - - - - - - - - - - - - - rcrb %cl, %dil
+# CHECK-NEXT: - 1.83 0.83 1.83 0.83 1.83 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rclb %cl, (%rax)
+# CHECK-NEXT: - 1.67 1.33 1.67 1.33 1.67 1.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rcrb %cl, (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - rclw %di
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - rcrw %di
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rclw (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rcrw (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - rclw $7, %di
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - rcrw $7, %di
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rclw $7, (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rcrw $7, (%rax)
+# CHECK-NEXT: - 1.33 1.00 1.33 1.00 1.33 1.00 - - - - - - - - - - - - - rclw %cl, %di
+# CHECK-NEXT: - 1.33 1.00 1.33 1.00 1.33 1.00 - - - - - - - - - - - - - rcrw %cl, %di
+# CHECK-NEXT: - 0.33 2.00 0.33 2.00 0.33 2.00 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rclw %cl, (%rax)
+# CHECK-NEXT: - 0.33 2.00 0.33 2.00 0.33 2.00 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rcrw %cl, (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - rcll %edi
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - rcrl %edi
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rcll (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rcrl (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - rcll $7, %edi
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - rcrl $7, %edi
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rcll $7, (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rcrl $7, (%rax)
+# CHECK-NEXT: - 1.33 1.00 1.33 1.00 1.33 1.00 - - - - - - - - - - - - - rcll %cl, %edi
+# CHECK-NEXT: - 1.33 1.00 1.33 1.00 1.33 1.00 - - - - - - - - - - - - - rcrl %cl, %edi
+# CHECK-NEXT: - 0.33 2.00 0.33 2.00 0.33 2.00 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rcll %cl, (%rax)
+# CHECK-NEXT: - 0.33 2.00 0.33 2.00 0.33 2.00 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rcrl %cl, (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - rclq %rdi
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - rcrq %rdi
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rclq (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rcrq (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - rclq $7, %rdi
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - rcrq $7, %rdi
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rclq $7, (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rcrq $7, (%rax)
+# CHECK-NEXT: - 1.33 1.00 1.33 1.00 1.33 1.00 - - - - - - - - - - - - - rclq %cl, %rdi
+# CHECK-NEXT: - 1.33 1.00 1.33 1.00 1.33 1.00 - - - - - - - - - - - - - rcrq %cl, %rdi
+# CHECK-NEXT: - 0.33 2.00 0.33 2.00 0.33 2.00 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rclq %cl, (%rax)
+# CHECK-NEXT: - 0.33 2.00 0.33 2.00 0.33 2.00 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rcrq %cl, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - rdmsr
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - rdpmc
+# CHECK-NEXT: - 2.83 2.17 2.83 2.17 2.83 2.17 - - - - - - - - - - - - - rdtsc
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - rdtscp
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - rolb %dil
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - rorb %dil
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rolb (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rorb (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - rolb $7, %dil
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - rorb $7, %dil
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rolb $7, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rorb $7, (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - rolb %cl, %dil
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - rorb %cl, %dil
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rolb %cl, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rorb %cl, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - rolw %di
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - rorw %di
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rolw (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rorw (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - rolw $7, %di
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - rorw $7, %di
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rolw $7, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rorw $7, (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - rolw %cl, %di
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - rorw %cl, %di
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rolw %cl, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rorw %cl, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - roll %edi
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - rorl %edi
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - roll (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rorl (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - roll $7, %edi
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - rorl $7, %edi
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - roll $7, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rorl $7, (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - roll %cl, %edi
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - rorl %cl, %edi
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - roll %cl, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rorl %cl, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - rolq %rdi
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - rorq %rdi
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rolq (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rorq (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - rolq $7, %rdi
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - rorq $7, %rdi
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rolq $7, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rorq $7, (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - rolq %cl, %rdi
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - rorq %cl, %rdi
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rolq %cl, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - rorq %cl, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - sahf
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - sarb %dil
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shlb %dil
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shrb %dil
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sarb (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shlb (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shrb (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - sarb $7, %dil
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shlb $7, %dil
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shrb $7, %dil
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sarb $7, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shlb $7, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shrb $7, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - sarb %cl, %dil
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - shlb %cl, %dil
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - shrb %cl, %dil
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sarb %cl, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shlb %cl, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shrb %cl, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - sarw %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shlw %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shrw %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - sarw (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - shlw (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - shrw (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - sarw $7, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shlw $7, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shrw $7, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - sarw $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - shlw $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - shrw $7, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - sarw %cl, %di
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - shlw %cl, %di
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - shrw %cl, %di
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sarw %cl, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shlw %cl, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shrw %cl, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - sarl %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shll %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shrl %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - sarl (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - shll (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - shrl (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - sarl $7, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shll $7, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shrl $7, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - sarl $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - shll $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - shrl $7, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - sarl %cl, %edi
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - shll %cl, %edi
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - shrl %cl, %edi
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sarl %cl, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shll %cl, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shrl %cl, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - sarq %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shlq %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shrq %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - sarq (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - shlq (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - shrq (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - sarq $7, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shlq $7, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shrq $7, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - sarq $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - shlq $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 1.67 1.67 1.67 0.33 0.33 0.33 - - - - - shrq $7, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - sarq %cl, %rdi
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - shlq %cl, %rdi
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - - shrq %cl, %rdi
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sarq %cl, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shlq %cl, (%rax)
+# CHECK-NEXT: - 0.67 - 0.67 - 0.67 - 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shrq %cl, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbb $0, %al
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbb $0, %dil
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sbbb $0, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock sbbb $0, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbb $7, %al
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbb $7, %dil
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sbbb $7, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock sbbb $7, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbb %sil, %dil
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sbbb %sil, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock sbbb %sil, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - 0.33 0.33 0.33 - - - - - - - - sbbb (%rax), %dil
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbw $0, %ax
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbw $0, %di
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sbbw $0, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock sbbw $0, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbw $511, %ax
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbw $511, %di
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sbbw $511, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock sbbw $511, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbw $7, %di
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sbbw $7, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock sbbw $7, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbw %si, %di
+# CHECK-NEXT: - 0.67 0.33 0.67 0.33 0.67 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sbbw %si, (%rax)
+# CHECK-NEXT: - 0.67 0.33 0.67 0.33 0.67 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock sbbw %si, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - 0.33 0.33 0.33 - - - - - - - - sbbw (%rax), %di
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbl $0, %eax
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbl $0, %edi
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sbbl $0, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock sbbl $0, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbl $665536, %eax
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbl $665536, %edi
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sbbl $665536, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock sbbl $665536, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbl $7, %edi
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sbbl $7, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock sbbl $7, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbl %esi, %edi
+# CHECK-NEXT: - 0.67 0.33 0.67 0.33 0.67 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sbbl %esi, (%rax)
+# CHECK-NEXT: - 0.67 0.33 0.67 0.33 0.67 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock sbbl %esi, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - 0.33 0.33 0.33 - - - - - - - - sbbl (%rax), %edi
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbq $0, %rax
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbq $0, %rdi
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sbbq $0, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock sbbq $0, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbq $665536, %rax
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbq $665536, %rdi
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sbbq $665536, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock sbbq $665536, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbq $7, %rdi
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sbbq $7, (%rax)
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock sbbq $7, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - - sbbq %rsi, %rdi
+# CHECK-NEXT: - 0.67 0.33 0.67 0.33 0.67 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - sbbq %rsi, (%rax)
+# CHECK-NEXT: - 0.67 0.33 0.67 0.33 0.67 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock sbbq %rsi, (%rax)
+# CHECK-NEXT: - 0.33 - 0.33 - 0.33 - - - 0.33 0.33 0.33 - - - - - - - - sbbq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - scasb %es:(%rdi), %al
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - scasw %es:(%rdi), %ax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - scasl %es:(%rdi), %eax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - scasq %es:(%rdi), %rax
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - seto %al
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - seto (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - setno %al
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - setno (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - setb %al
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - setb (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - setae %al
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - setae (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - sete %al
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - sete (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - setne %al
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - setne (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - seta %al
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - seta (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - setbe %al
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - setbe (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - sets %al
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - sets (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - setns %al
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - setns (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - setp %al
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - setp (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - setnp %al
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - setnp (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - setl %al
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - setl (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - setge %al
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - setge (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - setg %al
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - setg (%rax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - setle %al
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - setle (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - shldw %cl, %si, %di
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - shrdw %cl, %si, %di
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shldw %cl, %si, (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shrdw %cl, %si, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shldw $7, %si, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shrdw $7, %si, %di
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shldw $7, %si, (%rax)
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shrdw $7, %si, (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - shldl %cl, %esi, %edi
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - shrdl %cl, %esi, %edi
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shldl %cl, %esi, (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shrdl %cl, %esi, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shldl $7, %esi, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shrdl $7, %esi, %edi
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shldl $7, %esi, (%rax)
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shrdl $7, %esi, (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - shldq %cl, %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 - - - - - - - - - - - - - shrdq %cl, %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shldq %cl, %rsi, (%rax)
+# CHECK-NEXT: - 0.17 0.83 0.17 0.83 0.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shrdq %cl, %rsi, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shldq $7, %rsi, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - shrdq $7, %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shldq $7, %rsi, (%rax)
+# CHECK-NEXT: - 0.17 0.50 0.17 0.50 0.17 0.50 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - shrdq $7, %rsi, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - stc
+# CHECK-NEXT: - 0.50 0.17 0.50 0.17 0.50 0.17 - - - - - - - - - - - - - std
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - stosb %al, %es:(%rdi)
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - stosw %ax, %es:(%rdi)
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - stosl %eax, %es:(%rdi)
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - stosq %rax, %es:(%rdi)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - subb $7, %al
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - subb $7, %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - subb $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock subb $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - subb %sil, %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - subb %sil, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock subb %sil, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - subb (%rax), %dil
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - subw $511, %ax
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - subw $511, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - subw $511, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock subw $511, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - subw $7, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - subw $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock subw $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - subw %si, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - subw %si, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock subw %si, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - subw (%rax), %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - subl $665536, %eax
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - subl $665536, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - subl $665536, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock subl $665536, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - subl $7, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - subl $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock subl $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - subl %esi, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - subl %esi, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock subl %esi, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - subl (%rax), %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - subq $665536, %rax
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - subq $665536, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - subq $665536, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock subq $665536, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - subq $7, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - subq $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock subq $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - subq %rsi, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - subq %rsi, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock subq %rsi, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - subq (%rax), %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - testb $7, %al
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - testb $7, %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - testb $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - testb %sil, %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - testb %sil, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - testw $511, %ax
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - testw $511, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - testw $511, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - testw $7, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - testw $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - testw %si, %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - testw %si, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - testl $665536, %eax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - testl $665536, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - testl $665536, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - testl $7, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - testl $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - testl %esi, %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - testl %esi, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - testq $665536, %rax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - testq $665536, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - testq $665536, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - testq $7, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - testq $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - testq %rsi, %rdi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - testq %rsi, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - ud2
+# CHECK-NEXT: - 21.00 10.33 21.00 10.33 21.00 10.33 0.50 0.50 - - - 0.33 0.33 0.33 - 11.75 11.75 12.25 12.25 wrmsr
+# CHECK-NEXT: - 0.50 0.50 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - xaddb %bl, %cl
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - xaddb %bl, (%rcx)
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock xaddb %bl, (%rcx)
+# CHECK-NEXT: - 0.50 0.50 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - xaddw %bx, %cx
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - xaddw %ax, (%rbx)
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock xaddw %ax, (%rbx)
+# CHECK-NEXT: - 0.50 0.50 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - xaddl %ebx, %ecx
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - xaddl %eax, (%rbx)
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock xaddl %eax, (%rbx)
+# CHECK-NEXT: - 0.50 0.50 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - xaddq %rbx, %rcx
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - xaddq %rax, (%rbx)
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock xaddq %rax, (%rbx)
+# CHECK-NEXT: - 0.50 0.50 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - xchgb %bl, %cl
+# CHECK-NEXT: - 1.00 0.67 1.00 0.67 1.00 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - xchgb %bl, (%rbx)
+# CHECK-NEXT: - 1.00 0.67 1.00 0.67 1.00 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock xchgb %bl, (%rbx)
+# CHECK-NEXT: - 0.50 0.50 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - xchgw %bx, %ax
+# CHECK-NEXT: - 0.50 0.50 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - xchgw %bx, %cx
+# CHECK-NEXT: - 1.00 0.67 1.00 0.67 1.00 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - xchgw %ax, (%rbx)
+# CHECK-NEXT: - 1.00 0.67 1.00 0.67 1.00 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock xchgw %ax, (%rbx)
+# CHECK-NEXT: - 0.50 0.50 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - xchgl %ebx, %eax
+# CHECK-NEXT: - 0.50 0.50 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - xchgl %ebx, %ecx
+# CHECK-NEXT: - 1.00 0.67 1.00 0.67 1.00 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - xchgl %eax, (%rbx)
+# CHECK-NEXT: - 1.00 0.67 1.00 0.67 1.00 0.67 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock xchgl %eax, (%rbx)
+# CHECK-NEXT: - 0.50 0.50 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - xchgq %rbx, %rax
+# CHECK-NEXT: - 0.50 0.50 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - xchgq %rbx, %rcx
+# CHECK-NEXT: - 1.17 0.83 1.17 0.83 1.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - xchgq %rax, (%rbx)
+# CHECK-NEXT: - 1.17 0.83 1.17 0.83 1.17 0.83 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock xchgq %rax, (%rbx)
+# CHECK-NEXT: - 0.33 0.33 0.33 0.33 0.33 0.33 - - 0.33 0.33 0.33 - - - - - - - - xlatb
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - xorb $7, %al
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - xorb $7, %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - xorb $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock xorb $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - xorb %sil, %dil
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - xorb %sil, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 0.50 0.50 0.33 0.33 0.33 0.33 0.33 0.33 - - - - - lock xorb %sil, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - xorb (%rax), %dil
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - xorw $511, %ax
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - xorw $511, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - xorw $511, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock xorw $511, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - xorw $7, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - xorw $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock xorw $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - xorw %si, %di
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - xorw %si, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock xorw %si, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - xorw (%rax), %di
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - xorl $665536, %eax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - xorl $665536, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - xorl $665536, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock xorl $665536, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - xorl $7, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - xorl $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock xorl $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - xorl %esi, %edi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - xorl %esi, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock xorl %esi, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - xorl (%rax), %edi
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - xorq $665536, %rax
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - xorq $665536, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - xorq $665536, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock xorq $665536, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - xorq $7, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - xorq $7, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock xorq $7, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - xorq %rsi, %rdi
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - xorq %rsi, (%rax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 0.50 0.50 0.67 0.67 0.67 0.33 0.33 0.33 - - - - - lock xorq %rsi, (%rax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - 0.33 0.33 0.33 - - - - - - - - xorq (%rax), %rdi
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-x87.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-x87.s
new file mode 100644
index 0000000000000..08ec7adfe958d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-x87.s
@@ -0,0 +1,533 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+f2xm1
+
+fabs
+
+fadd %st, %st(1)
+fadd %st(2)
+fadds (%ecx)
+faddl (%ecx)
+faddp %st(1)
+faddp %st(2)
+fiadds (%ecx)
+fiaddl (%ecx)
+
+fbld (%ecx)
+fbstp (%eax)
+
+fchs
+
+fnclex
+
+fcmovb %st(1), %st
+fcmovbe %st(1), %st
+fcmove %st(1), %st
+fcmovnb %st(1), %st
+fcmovnbe %st(1), %st
+fcmovne %st(1), %st
+fcmovnu %st(1), %st
+fcmovu %st(1), %st
+
+fcom %st(1)
+fcom %st(3)
+fcoms (%ecx)
+fcoml (%eax)
+fcomp %st(1)
+fcomp %st(3)
+fcomps (%ecx)
+fcompl (%eax)
+fcompp
+
+fcomi %st(3)
+fcompi %st(3)
+
+fcos
+
+fdecstp
+
+fdiv %st, %st(1)
+fdiv %st(2)
+fdivs (%ecx)
+fdivl (%eax)
+fdivp %st(1)
+fdivp %st(2)
+fidivs (%ecx)
+fidivl (%eax)
+
+fdivr %st, %st(1)
+fdivr %st(2)
+fdivrs (%ecx)
+fdivrl (%eax)
+fdivrp %st(1)
+fdivrp %st(2)
+fidivrs (%ecx)
+fidivrl (%eax)
+
+ffree %st(0)
+
+ficoms (%ecx)
+ficoml (%eax)
+ficomps (%ecx)
+ficompl (%eax)
+
+filds (%edx)
+fildl (%ecx)
+fildll (%eax)
+
+fincstp
+
+fninit
+
+fists (%edx)
+fistl (%ecx)
+fistps (%edx)
+fistpl (%ecx)
+fistpll (%eax)
+
+fisttps (%edx)
+fisttpl (%ecx)
+fisttpll (%eax)
+
+fld %st(0)
+flds (%edx)
+fldl (%ecx)
+fldt (%eax)
+
+fldcw (%eax)
+fldenv (%eax)
+
+fld1
+fldl2e
+fldl2t
+fldlg2
+fldln2
+fldpi
+fldz
+
+fmul %st, %st(1)
+fmul %st(2)
+fmuls (%ecx)
+fmull (%eax)
+fmulp %st(1)
+fmulp %st(2)
+fimuls (%ecx)
+fimull (%eax)
+
+fnop
+
+fpatan
+
+fprem
+fprem1
+
+fptan
+
+frndint
+
+frstor (%eax)
+
+fnsave (%eax)
+
+fscale
+
+fsin
+
+fsincos
+
+fsqrt
+
+fst %st(0)
+fsts (%edx)
+fstl (%ecx)
+fstp %st(0)
+fstpl (%edx)
+fstpl (%ecx)
+fstpt (%eax)
+
+fnstcw (%eax)
+fnstenv (%eax)
+fnstsw (%eax)
+
+frstor (%eax)
+fsave (%eax)
+
+fsub %st, %st(1)
+fsub %st(2)
+fsubs (%ecx)
+fsubl (%eax)
+fsubp %st(1)
+fsubp %st(2)
+fisubs (%ecx)
+fisubl (%eax)
+
+fsubr %st, %st(1)
+fsubr %st(2)
+fsubrs (%ecx)
+fsubrl (%eax)
+fsubrp %st(1)
+fsubrp %st(2)
+fisubrs (%ecx)
+fisubrl (%eax)
+
+ftst
+
+fucom %st(1)
+fucom %st(3)
+fucomp %st(1)
+fucomp %st(3)
+fucompp
+
+fucomi %st(3)
+fucompi %st(3)
+
+fwait
+
+fxam
+
+fxch %st(1)
+fxch %st(3)
+
+fxrstor (%eax)
+fxsave (%eax)
+
+fxtract
+
+fyl2x
+fyl2xp1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.17 U f2xm1
+# CHECK-NEXT: 1 1 0.50 U fabs
+# CHECK-NEXT: 1 2 0.50 U fadd %st, %st(1)
+# CHECK-NEXT: 1 2 0.50 U fadd %st(2), %st
+# CHECK-NEXT: 2 10 0.33 * U fadds (%ecx)
+# CHECK-NEXT: 2 10 0.33 * U faddl (%ecx)
+# CHECK-NEXT: 1 2 0.50 U faddp %st, %st(1)
+# CHECK-NEXT: 1 2 0.50 U faddp %st, %st(2)
+# CHECK-NEXT: 3 13 0.67 * U fiadds (%ecx)
+# CHECK-NEXT: 3 13 0.67 * U fiaddl (%ecx)
+# CHECK-NEXT: 1 100 0.17 * U fbld (%ecx)
+# CHECK-NEXT: 2 1 0.50 * U fbstp (%eax)
+# CHECK-NEXT: 1 1 0.50 U fchs
+# CHECK-NEXT: 4 4 1.00 U fnclex
+# CHECK-NEXT: 1 3 0.50 U fcmovb %st(1), %st
+# CHECK-NEXT: 1 3 0.50 U fcmovbe %st(1), %st
+# CHECK-NEXT: 1 3 0.50 U fcmove %st(1), %st
+# CHECK-NEXT: 1 3 0.50 U fcmovnb %st(1), %st
+# CHECK-NEXT: 1 3 0.50 U fcmovnbe %st(1), %st
+# CHECK-NEXT: 1 3 0.50 U fcmovne %st(1), %st
+# CHECK-NEXT: 1 3 0.50 U fcmovnu %st(1), %st
+# CHECK-NEXT: 1 3 0.50 U fcmovu %st(1), %st
+# CHECK-NEXT: 1 1 0.50 U fcom %st(1)
+# CHECK-NEXT: 1 1 0.50 U fcom %st(3)
+# CHECK-NEXT: 2 8 0.50 * U fcoms (%ecx)
+# CHECK-NEXT: 2 8 0.50 * U fcoml (%eax)
+# CHECK-NEXT: 1 1 0.50 U fcomp %st(1)
+# CHECK-NEXT: 1 1 0.50 U fcomp %st(3)
+# CHECK-NEXT: 2 8 0.50 * U fcomps (%ecx)
+# CHECK-NEXT: 2 8 0.50 * U fcompl (%eax)
+# CHECK-NEXT: 1 100 0.17 U fcompp
+# CHECK-NEXT: 1 1 0.50 U fcomi %st(3), %st
+# CHECK-NEXT: 1 1 0.50 U fcompi %st(3), %st
+# CHECK-NEXT: 1 100 0.17 U fcos
+# CHECK-NEXT: 2 2 0.67 U fdecstp
+# CHECK-NEXT: 1 15 1.00 U fdiv %st, %st(1)
+# CHECK-NEXT: 1 20 1.00 U fdiv %st(2), %st
+# CHECK-NEXT: 2 22 1.00 * U fdivs (%ecx)
+# CHECK-NEXT: 2 22 1.00 * U fdivl (%eax)
+# CHECK-NEXT: 1 15 1.00 U fdivp %st, %st(1)
+# CHECK-NEXT: 1 15 1.00 U fdivp %st, %st(2)
+# CHECK-NEXT: 3 25 1.00 * U fidivs (%ecx)
+# CHECK-NEXT: 3 25 1.00 * U fidivl (%eax)
+# CHECK-NEXT: 1 20 1.00 U fdivr %st, %st(1)
+# CHECK-NEXT: 1 15 1.00 U fdivr %st(2), %st
+# CHECK-NEXT: 2 27 1.00 * U fdivrs (%ecx)
+# CHECK-NEXT: 2 27 1.00 * U fdivrl (%eax)
+# CHECK-NEXT: 1 20 1.00 U fdivrp %st, %st(1)
+# CHECK-NEXT: 1 20 1.00 U fdivrp %st, %st(2)
+# CHECK-NEXT: 3 30 1.00 * U fidivrs (%ecx)
+# CHECK-NEXT: 3 30 1.00 * U fidivrl (%eax)
+# CHECK-NEXT: 1 100 0.17 U ffree %st(0)
+# CHECK-NEXT: 3 11 0.67 * U ficoms (%ecx)
+# CHECK-NEXT: 3 11 0.67 * U ficoml (%eax)
+# CHECK-NEXT: 3 11 0.67 * U ficomps (%ecx)
+# CHECK-NEXT: 3 11 0.67 * U ficompl (%eax)
+# CHECK-NEXT: 2 10 0.33 * U filds (%edx)
+# CHECK-NEXT: 2 10 0.33 * U fildl (%ecx)
+# CHECK-NEXT: 2 10 0.33 * U fildll (%eax)
+# CHECK-NEXT: 1 1 0.33 U fincstp
+# CHECK-NEXT: 15 75 3.00 U fninit
+# CHECK-NEXT: 2 12 0.50 * U fists (%edx)
+# CHECK-NEXT: 2 12 0.50 * U fistl (%ecx)
+# CHECK-NEXT: 2 12 0.50 * U fistps (%edx)
+# CHECK-NEXT: 2 12 0.50 * U fistpl (%ecx)
+# CHECK-NEXT: 2 12 0.50 * U fistpll (%eax)
+# CHECK-NEXT: 2 12 0.50 * U fisttps (%edx)
+# CHECK-NEXT: 2 12 0.50 * U fisttpl (%ecx)
+# CHECK-NEXT: 2 12 0.50 * U fisttpll (%eax)
+# CHECK-NEXT: 1 1 0.17 U fld %st(0)
+# CHECK-NEXT: 1 4 0.33 * U flds (%edx)
+# CHECK-NEXT: 1 4 0.33 * U fldl (%ecx)
+# CHECK-NEXT: 1 4 0.33 * U fldt (%eax)
+# CHECK-NEXT: 3 7 0.50 * U fldcw (%eax)
+# CHECK-NEXT: 64 62 10.25 * U fldenv (%eax)
+# CHECK-NEXT: 2 1 1.00 U fld1
+# CHECK-NEXT: 2 1 1.00 U fldl2e
+# CHECK-NEXT: 2 1 1.00 U fldl2t
+# CHECK-NEXT: 2 1 1.00 U fldlg2
+# CHECK-NEXT: 2 1 1.00 U fldln2
+# CHECK-NEXT: 2 1 1.00 U fldpi
+# CHECK-NEXT: 1 1 0.50 U fldz
+# CHECK-NEXT: 1 4 0.25 U fmul %st, %st(1)
+# CHECK-NEXT: 1 4 0.25 U fmul %st(2), %st
+# CHECK-NEXT: 2 11 0.50 * U fmuls (%ecx)
+# CHECK-NEXT: 2 11 0.50 * U fmull (%eax)
+# CHECK-NEXT: 1 4 0.25 U fmulp %st, %st(1)
+# CHECK-NEXT: 1 4 0.25 U fmulp %st, %st(2)
+# CHECK-NEXT: 3 14 0.50 * U fimuls (%ecx)
+# CHECK-NEXT: 3 14 0.50 * U fimull (%eax)
+# CHECK-NEXT: 1 1 0.33 U fnop
+# CHECK-NEXT: 1 100 0.17 U fpatan
+# CHECK-NEXT: 1 100 0.17 U fprem
+# CHECK-NEXT: 1 100 0.17 U fprem1
+# CHECK-NEXT: 1 100 0.17 U fptan
+# CHECK-NEXT: 1 100 0.17 U frndint
+# CHECK-NEXT: 1 100 0.17 * U frstor (%eax)
+# CHECK-NEXT: 1 100 0.17 * U fnsave (%eax)
+# CHECK-NEXT: 1 100 0.17 U fscale
+# CHECK-NEXT: 1 100 0.17 U fsin
+# CHECK-NEXT: 1 100 0.17 U fsincos
+# CHECK-NEXT: 1 21 7.00 U fsqrt
+# CHECK-NEXT: 1 1 0.17 U fst %st(0)
+# CHECK-NEXT: 1 1 0.50 * U fsts (%edx)
+# CHECK-NEXT: 1 1 0.50 * U fstl (%ecx)
+# CHECK-NEXT: 1 1 0.17 U fstp %st(0)
+# CHECK-NEXT: 2 1 0.50 * U fstpl (%edx)
+# CHECK-NEXT: 2 1 0.50 * U fstpl (%ecx)
+# CHECK-NEXT: 2 1 0.50 * U fstpt (%eax)
+# CHECK-NEXT: 3 2 0.50 * U fnstcw (%eax)
+# CHECK-NEXT: 100 106 10.00 * U fnstenv (%eax)
+# CHECK-NEXT: 3 3 0.50 * U fnstsw (%eax)
+# CHECK-NEXT: 1 100 0.17 * U frstor (%eax)
+# CHECK-NEXT: 2 2 0.50 U wait
+# CHECK-NEXT: 1 100 0.17 * U fnsave (%eax)
+# CHECK-NEXT: 1 2 0.50 U fsub %st, %st(1)
+# CHECK-NEXT: 1 2 0.50 U fsub %st(2), %st
+# CHECK-NEXT: 2 10 0.33 * U fsubs (%ecx)
+# CHECK-NEXT: 2 10 0.33 * U fsubl (%eax)
+# CHECK-NEXT: 1 2 0.50 U fsubp %st, %st(1)
+# CHECK-NEXT: 1 2 0.50 U fsubp %st, %st(2)
+# CHECK-NEXT: 3 13 0.67 * U fisubs (%ecx)
+# CHECK-NEXT: 3 13 0.67 * U fisubl (%eax)
+# CHECK-NEXT: 1 2 0.50 U fsubr %st, %st(1)
+# CHECK-NEXT: 1 2 0.50 U fsubr %st(2), %st
+# CHECK-NEXT: 2 10 0.33 * U fsubrs (%ecx)
+# CHECK-NEXT: 2 10 0.33 * U fsubrl (%eax)
+# CHECK-NEXT: 1 2 0.50 U fsubrp %st, %st(1)
+# CHECK-NEXT: 1 2 0.50 U fsubrp %st, %st(2)
+# CHECK-NEXT: 3 13 0.67 * U fisubrs (%ecx)
+# CHECK-NEXT: 3 13 0.67 * U fisubrl (%eax)
+# CHECK-NEXT: 1 2 0.33 U ftst
+# CHECK-NEXT: 1 1 0.50 U fucom %st(1)
+# CHECK-NEXT: 1 1 0.50 U fucom %st(3)
+# CHECK-NEXT: 1 1 0.50 U fucomp %st(1)
+# CHECK-NEXT: 1 1 0.50 U fucomp %st(3)
+# CHECK-NEXT: 1 2 0.33 U fucompp
+# CHECK-NEXT: 1 1 0.50 U fucomi %st(3), %st
+# CHECK-NEXT: 1 1 0.50 U fucompi %st(3), %st
+# CHECK-NEXT: 2 2 0.50 U wait
+# CHECK-NEXT: 1 2 0.33 U fxam
+# CHECK-NEXT: 15 17 2.00 U fxch %st(1)
+# CHECK-NEXT: 15 17 2.00 U fxch %st(3)
+# CHECK-NEXT: 90 63 13.50 * * U fxrstor (%eax)
+# CHECK-NEXT: 110 100 19.00 * * U fxsave (%eax)
+# CHECK-NEXT: 1 100 0.17 U fxtract
+# CHECK-NEXT: 1 100 0.17 U fyl2x
+# CHECK-NEXT: 1 100 0.17 U fyl2xp1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - 37.67 44.00 21.67 33.00 21.67 33.00 32.50 32.50 32.33 32.33 32.33 15.33 15.33 15.33 7.00 53.00 53.00 64.00 64.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - f2xm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fabs
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 fadd %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 fadd %st(2), %st
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - fadds (%ecx)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - faddl (%ecx)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 faddp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 faddp %st, %st(2)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 0.33 0.33 0.33 - - - - - - - - fiadds (%ecx)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 0.33 0.33 0.33 - - - - - - - - fiaddl (%ecx)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fbld (%ecx)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 0.33 0.33 0.33 - - - - - - - - fbstp (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fchs
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 1.00 1.00 1.00 fnclex
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fcmovb %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fcmovbe %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fcmove %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fcmovnb %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fcmovnbe %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fcmovne %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fcmovnu %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fcmovu %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fcom %st(1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fcom %st(3)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - fcoms (%ecx)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - fcoml (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fcomp %st(1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fcomp %st(3)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - fcomps (%ecx)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - 0.50 0.50 - - fcompl (%eax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fcompp
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fcomi %st(3), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fcompi %st(3), %st
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fcos
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - - - - - - - - - - - - fdecstp
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - fdiv %st, %st(1)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - fdiv %st(2), %st
+# CHECK-NEXT: - 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - - - fdivs (%ecx)
+# CHECK-NEXT: - 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - - - fdivl (%eax)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - fdivp %st, %st(1)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - fdivp %st, %st(2)
+# CHECK-NEXT: - 1.00 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - fidivs (%ecx)
+# CHECK-NEXT: - 1.00 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - fidivl (%eax)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - fdivr %st, %st(1)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - fdivr %st(2), %st
+# CHECK-NEXT: - 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - - - fdivrs (%ecx)
+# CHECK-NEXT: - 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - - - fdivrl (%eax)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - fdivrp %st, %st(1)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - fdivrp %st, %st(2)
+# CHECK-NEXT: - 1.00 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - fidivrs (%ecx)
+# CHECK-NEXT: - 1.00 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - fidivrl (%eax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - ffree %st(0)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 0.33 0.33 0.33 - - - - - - - - ficoms (%ecx)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 0.33 0.33 0.33 - - - - - - - - ficoml (%eax)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 0.33 0.33 0.33 - - - - - - - - ficomps (%ecx)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 0.33 0.33 0.33 - - - - - - - - ficompl (%eax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - filds (%edx)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - fildl (%ecx)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - fildll (%eax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - fincstp
+# CHECK-NEXT: - - 3.00 - 3.00 - 3.00 - - - - - - - - - 1.50 1.50 1.50 1.50 fninit
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - fists (%edx)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - fistl (%ecx)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - fistps (%edx)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - fistpl (%ecx)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - fistpll (%eax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - fisttps (%edx)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - fisttpl (%ecx)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - 0.33 0.33 0.33 - - - - - fisttpll (%eax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fld %st(0)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - flds (%edx)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - fldl (%ecx)
+# CHECK-NEXT: - - - - - - - - - 0.33 0.33 0.33 - - - - - - - - fldt (%eax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - 0.50 0.50 fldcw (%eax)
+# CHECK-NEXT: - 3.33 1.67 3.33 1.67 3.33 1.67 - - 2.67 2.67 2.67 - - - - 9.75 9.75 10.75 10.75 fldenv (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 1.00 fld1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 1.00 fldl2e
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 1.00 fldl2t
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 1.00 fldlg2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 1.00 fldln2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 1.00 fldpi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 fldz
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmul %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmul %st(2), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.75 0.75 fmuls (%ecx)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.75 0.75 fmull (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmulp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 fmulp %st, %st(2)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - 0.25 0.25 0.75 0.75 fimuls (%ecx)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - 0.25 0.25 0.75 0.75 fimull (%eax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - fnop
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fpatan
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fprem
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fprem1
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fptan
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - frndint
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - frstor (%eax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fnsave (%eax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fscale
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fsin
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fsincos
+# CHECK-NEXT: - - - - - - - - - - - - - - - 7.00 0.50 0.50 - - fsqrt
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fst %st(0)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 0.33 0.33 0.33 - - - - - - - - fsts (%edx)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 0.33 0.33 0.33 - - - - - - - - fstl (%ecx)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fstp %st(0)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 0.33 0.33 0.33 - - - - - - - - fstpl (%edx)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 0.33 0.33 0.33 - - - - - - - - fstpl (%ecx)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 0.33 0.33 0.33 - - - - - - - - fstpt (%eax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 0.33 0.33 0.33 - - - - - - 0.50 0.50 fnstcw (%eax)
+# CHECK-NEXT: - 7.00 6.33 7.00 5.33 7.00 5.33 5.50 5.50 3.67 3.67 3.67 - - - - 7.50 7.50 12.50 12.50 fnstenv (%eax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 0.33 0.33 0.33 - - - - - - 0.50 0.50 fnstsw (%eax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - frstor (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 wait
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fnsave (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 fsub %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 fsub %st(2), %st
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - fsubs (%ecx)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - fsubl (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 fsubp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 fsubp %st, %st(2)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 0.33 0.33 0.33 - - - - - - - - fisubs (%ecx)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 0.33 0.33 0.33 - - - - - - - - fisubl (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 fsubr %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 fsubr %st(2), %st
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - fsubrs (%ecx)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - 0.33 0.33 0.33 - - - - - - - - fsubrl (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 fsubrp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 0.50 0.50 fsubrp %st, %st(2)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 0.33 0.33 0.33 - - - - - - - - fisubrs (%ecx)
+# CHECK-NEXT: - - 0.67 - 0.67 - 0.67 - - 0.33 0.33 0.33 - - - - - - - - fisubrl (%eax)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - ftst
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fucom %st(1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fucom %st(3)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fucomp %st(1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fucomp %st(3)
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - fucompp
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fucomi %st(3), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 - - fucompi %st(3), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 wait
+# CHECK-NEXT: - - 0.33 - 0.33 - 0.33 - - - - - - - - - - - - - fxam
+# CHECK-NEXT: - 1.33 1.00 1.33 1.00 1.33 1.00 - - - - - - - - - 2.50 2.50 1.50 1.50 fxch %st(1)
+# CHECK-NEXT: - 1.33 1.00 1.33 1.00 1.33 1.00 - - - - - - - - - 2.50 2.50 1.50 1.50 fxch %st(3)
+# CHECK-NEXT: - 0.67 0.33 0.67 0.33 0.67 0.33 - - 11.00 11.00 11.00 - - - - 11.75 11.75 15.25 15.25 fxrstor (%eax)
+# CHECK-NEXT: - 4.17 12.50 4.17 2.50 4.17 2.50 19.00 19.00 0.67 0.67 0.67 12.67 12.67 12.67 - - - 1.00 1.00 fxsave (%eax)
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fxtract
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fyl2x
+# CHECK-NEXT: - 0.17 0.17 0.17 0.17 0.17 0.17 - - - - - - - - - - - - - fyl2xp1
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-xsave.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-xsave.s
new file mode 100644
index 0000000000000..987847de8aaac
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-xsave.s
@@ -0,0 +1,61 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s
+
+xgetbv
+
+xrstor (%rax)
+
+xrstors (%rax)
+
+xsave (%rax)
+
+xsetbv
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 23 4 3.33 U xgetbv
+# CHECK-NEXT: 31 37 5.25 * * U xrstor (%rax)
+# CHECK-NEXT: 31 37 5.25 * * U xrstors (%rax)
+# CHECK-NEXT: 140 42 15.00 * * U xsave (%rax)
+# CHECK-NEXT: 54 5 8.67 * * U xsetbv
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - 32.33 22.33 32.33 22.33 32.33 22.33 0.50 0.50 2.00 2.00 2.00 0.33 0.33 0.33 - 25.00 25.00 28.50 28.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - 3.83 2.83 3.83 2.83 3.83 2.83 - - - - - - - - - 0.75 0.75 0.75 0.75 xgetbv
+# CHECK-NEXT: - 2.67 0.33 2.67 0.33 2.67 0.33 - - 0.33 0.33 0.33 - - - - 5.25 5.25 5.25 5.25 xrstor (%rax)
+# CHECK-NEXT: - 2.67 0.33 2.67 0.33 2.67 0.33 - - 0.33 0.33 0.33 - - - - 5.25 5.25 5.25 5.25 xrstors (%rax)
+# CHECK-NEXT: - 14.67 10.00 14.67 10.00 14.67 10.00 0.50 0.50 1.33 1.33 1.33 0.33 0.33 0.33 - 13.25 13.25 16.75 16.75 xsave (%rax)
+# CHECK-NEXT: - 8.50 8.83 8.50 8.83 8.50 8.83 - - - - - - - - - 0.50 0.50 0.50 0.50 xsetbv
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/zero-idioms.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/zero-idioms.s
new file mode 100644
index 0000000000000..b6e5cfcbe0660
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/zero-idioms.s
@@ -0,0 +1,503 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -timeline -register-file-stats -iterations=1 < %s | FileCheck %s
+
+# On SKL, renamer-based zeroing does not work for:
+# - 16 and 8-bit GPRs
+# - MMX
+# - ANDN variants
+
+subl %eax, %eax
+subq %rax, %rax
+xorl %eax, %eax
+xorq %rax, %rax
+
+pcmpgtb %mm2, %mm2
+pcmpgtd %mm2, %mm2
+# pcmpgtq %mm2, %mm2 # invalid operand for instruction
+pcmpgtw %mm2, %mm2
+
+pcmpgtb %xmm2, %xmm2
+pcmpgtd %xmm2, %xmm2
+pcmpgtq %xmm2, %xmm2
+pcmpgtw %xmm2, %xmm2
+
+vpcmpgtb %xmm3, %xmm3, %xmm3
+vpcmpgtd %xmm3, %xmm3, %xmm3
+vpcmpgtq %xmm3, %xmm3, %xmm3
+vpcmpgtw %xmm3, %xmm3, %xmm3
+
+vpcmpgtb %xmm3, %xmm3, %xmm5
+vpcmpgtd %xmm3, %xmm3, %xmm5
+vpcmpgtq %xmm3, %xmm3, %xmm5
+vpcmpgtw %xmm3, %xmm3, %xmm5
+
+vpcmpgtb %ymm3, %ymm3, %ymm3
+vpcmpgtd %ymm3, %ymm3, %ymm3
+vpcmpgtq %ymm3, %ymm3, %ymm3
+vpcmpgtw %ymm3, %ymm3, %ymm3
+
+vpcmpgtb %ymm3, %ymm3, %ymm5
+vpcmpgtd %ymm3, %ymm3, %ymm5
+vpcmpgtq %ymm3, %ymm3, %ymm5
+vpcmpgtw %ymm3, %ymm3, %ymm5
+
+psubb %mm2, %mm2
+psubd %mm2, %mm2
+psubq %mm2, %mm2
+psubw %mm2, %mm2
+psubb %xmm2, %xmm2
+psubd %xmm2, %xmm2
+psubq %xmm2, %xmm2
+psubw %xmm2, %xmm2
+vpsubb %xmm3, %xmm3, %xmm3
+vpsubd %xmm3, %xmm3, %xmm3
+vpsubq %xmm3, %xmm3, %xmm3
+vpsubw %xmm3, %xmm3, %xmm3
+vpsubb %ymm3, %ymm3, %ymm3
+vpsubd %ymm3, %ymm3, %ymm3
+vpsubq %ymm3, %ymm3, %ymm3
+vpsubw %ymm3, %ymm3, %ymm3
+
+vpsubb %xmm3, %xmm3, %xmm5
+vpsubd %xmm3, %xmm3, %xmm5
+vpsubq %xmm3, %xmm3, %xmm5
+vpsubw %xmm3, %xmm3, %xmm5
+vpsubb %ymm3, %ymm3, %ymm5
+vpsubd %ymm3, %ymm3, %ymm5
+vpsubq %ymm3, %ymm3, %ymm5
+vpsubw %ymm3, %ymm3, %ymm5
+
+andnps %xmm0, %xmm0
+andnpd %xmm1, %xmm1
+vandnps %xmm2, %xmm2, %xmm2
+vandnpd %xmm1, %xmm1, %xmm1
+vandnps %ymm2, %ymm2, %ymm2
+vandnpd %ymm1, %ymm1, %ymm1
+pandn %mm2, %mm2
+pandn %xmm2, %xmm2
+vpandn %xmm3, %xmm3, %xmm3
+vpandn %ymm3, %ymm3, %ymm3
+
+vandnps %xmm2, %xmm2, %xmm5
+vandnpd %xmm1, %xmm1, %xmm5
+vpandn %xmm3, %xmm3, %xmm5
+vandnps %ymm2, %ymm2, %ymm5
+vandnpd %ymm1, %ymm1, %ymm5
+vpandn %ymm3, %ymm3, %ymm5
+
+xorps %xmm0, %xmm0
+xorpd %xmm1, %xmm1
+vxorps %xmm2, %xmm2, %xmm2
+vxorpd %xmm1, %xmm1, %xmm1
+vxorps %ymm2, %ymm2, %ymm2
+vxorpd %ymm1, %ymm1, %ymm1
+pxor %mm2, %mm2
+pxor %xmm2, %xmm2
+vpxor %xmm3, %xmm3, %xmm3
+vpxor %ymm3, %ymm3, %ymm3
+
+vxorps %xmm4, %xmm4, %xmm5
+vxorpd %xmm1, %xmm1, %xmm3
+vxorps %ymm4, %ymm4, %ymm5
+vxorpd %ymm1, %ymm1, %ymm3
+vpxor %xmm3, %xmm3, %xmm5
+vpxor %ymm3, %ymm3, %ymm5
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 83
+# CHECK-NEXT: Total Cycles: 32
+# CHECK-NEXT: Total uOps: 83
+
+# CHECK: Dispatch Width: 8
+# CHECK-NEXT: uOps Per Cycle: 2.59
+# CHECK-NEXT: IPC: 2.59
+# CHECK-NEXT: Block RThroughput: 13.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.33 subl %eax, %eax
+# CHECK-NEXT: 1 1 0.33 subq %rax, %rax
+# CHECK-NEXT: 1 2 0.17 xorl %eax, %eax
+# CHECK-NEXT: 1 2 0.17 xorq %rax, %rax
+# CHECK-NEXT: 1 1 1.00 pcmpgtb %mm2, %mm2
+# CHECK-NEXT: 1 1 1.00 pcmpgtd %mm2, %mm2
+# CHECK-NEXT: 1 1 1.00 pcmpgtw %mm2, %mm2
+# CHECK-NEXT: 1 1 0.50 pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: 1 3 1.50 pcmpgtq %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpgtw %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpcmpgtb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.50 vpcmpgtd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 3 1.50 vpcmpgtq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.50 vpcmpgtw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.50 vpcmpgtb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.50 vpcmpgtd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 3 1.50 vpcmpgtq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.50 vpcmpgtw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.50 vpcmpgtb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.50 vpcmpgtd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 3 1.50 vpcmpgtq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.50 vpcmpgtw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.50 vpcmpgtb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.50 vpcmpgtd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 3 1.50 vpcmpgtq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.50 vpcmpgtw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.33 psubb %mm2, %mm2
+# CHECK-NEXT: 1 1 0.33 psubd %mm2, %mm2
+# CHECK-NEXT: 1 1 0.33 psubq %mm2, %mm2
+# CHECK-NEXT: 1 1 0.33 psubw %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 psubb %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 psubd %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 psubq %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 psubw %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.25 vpsubd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.25 vpsubq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.25 vpsubw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.25 vpsubb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.25 vpsubd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.25 vpsubq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.25 vpsubw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.25 vpsubb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.25 vpsubd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.25 vpsubq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.25 vpsubw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.25 vpsubb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.25 vpsubd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.25 vpsubq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.25 vpsubw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.25 andnps %xmm0, %xmm0
+# CHECK-NEXT: 1 1 0.25 andnpd %xmm1, %xmm1
+# CHECK-NEXT: 1 1 0.25 vandnps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandnpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: 1 1 0.25 vandnps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: 1 1 0.25 vandnpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 1 1 0.25 pandn %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 pandn %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpandn %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.25 vpandn %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.25 vandnps %xmm2, %xmm2, %xmm5
+# CHECK-NEXT: 1 1 0.25 vandnpd %xmm1, %xmm1, %xmm5
+# CHECK-NEXT: 1 1 0.25 vpandn %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.25 vandnps %ymm2, %ymm2, %ymm5
+# CHECK-NEXT: 1 1 0.25 vandnpd %ymm1, %ymm1, %ymm5
+# CHECK-NEXT: 1 1 0.25 vpandn %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.25 xorps %xmm0, %xmm0
+# CHECK-NEXT: 1 1 0.25 xorpd %xmm1, %xmm1
+# CHECK-NEXT: 1 1 0.25 vxorps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 vxorpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: 1 1 0.25 vxorps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: 1 1 0.25 vxorpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 1 1 0.25 pxor %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 pxor %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpxor %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.25 vpxor %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.25 vxorps %xmm4, %xmm4, %xmm5
+# CHECK-NEXT: 1 1 0.25 vxorpd %xmm1, %xmm1, %xmm3
+# CHECK-NEXT: 1 1 0.25 vxorps %ymm4, %ymm4, %ymm5
+# CHECK-NEXT: 1 1 0.25 vxorpd %ymm1, %ymm1, %ymm3
+# CHECK-NEXT: 1 1 0.25 vpxor %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.25 vpxor %ymm3, %ymm3, %ymm5
+
+# CHECK: Register File statistics:
+# CHECK-NEXT: Total number of mappings created: 87
+# CHECK-NEXT: Max number of mappings used: 68
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - LNLPPort00
+# CHECK-NEXT: [2] - LNLPPort01
+# CHECK-NEXT: [3] - LNLPPort02
+# CHECK-NEXT: [4] - LNLPPort03
+# CHECK-NEXT: [5] - LNLPPort04
+# CHECK-NEXT: [6] - LNLPPort05
+# CHECK-NEXT: [7] - LNLPPort10
+# CHECK-NEXT: [8] - LNLPPort11
+# CHECK-NEXT: [9] - LNLPPort20
+# CHECK-NEXT: [10] - LNLPPort21
+# CHECK-NEXT: [11] - LNLPPort22
+# CHECK-NEXT: [12] - LNLPPort25
+# CHECK-NEXT: [13] - LNLPPort26
+# CHECK-NEXT: [14] - LNLPPort27
+# CHECK-NEXT: [15] - LNLPPortInvalid
+# CHECK-NEXT: [16] - LNLPVPort00
+# CHECK-NEXT: [17] - LNLPVPort01
+# CHECK-NEXT: [18] - LNLPVPort02
+# CHECK-NEXT: [19] - LNLPVPort03
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
+# CHECK-NEXT: - - 2.00 1.00 2.00 1.00 2.00 - - - - - - - - - 22.00 22.00 20.00 21.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] Instructions:
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - subl %eax, %eax
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - subq %rax, %rax
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - - xorl %eax, %eax
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - xorq %rax, %rax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pcmpgtb %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pcmpgtd %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pcmpgtw %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 3.00 pcmpgtq %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pcmpgtw %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - vpcmpgtb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - vpcmpgtd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 3.00 - vpcmpgtq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - vpcmpgtw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - vpcmpgtb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - vpcmpgtd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 3.00 - vpcmpgtq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - vpcmpgtw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - vpcmpgtb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - vpcmpgtd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 3.00 - vpcmpgtq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - vpcmpgtw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - vpcmpgtb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - vpcmpgtd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 3.00 - vpcmpgtq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - vpcmpgtw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - psubb %mm2, %mm2
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - psubd %mm2, %mm2
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - psubq %mm2, %mm2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - psubw %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 psubb %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 psubd %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 psubq %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 psubw %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 vpsubb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 vpsubd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 vpsubq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 vpsubw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 vpsubb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - vpsubd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 vpsubq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - vpsubw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - vpsubb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - vpsubd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 vpsubq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - vpsubw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - vpsubb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - vpsubd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 vpsubq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - vpsubw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - andnps %xmm0, %xmm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - andnpd %xmm1, %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - vandnps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - vandnpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 vandnps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 vandnpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pandn %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 pandn %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - vpandn %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - vpandn %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 vandnps %xmm2, %xmm2, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - vandnpd %xmm1, %xmm1, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 vpandn %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - vandnps %ymm2, %ymm2, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - vandnpd %ymm1, %ymm1, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - vpandn %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - xorps %xmm0, %xmm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - xorpd %xmm1, %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - vxorps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 vxorpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - vxorps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - vxorpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - pxor %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - pxor %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - vpxor %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - vpxor %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - vxorps %xmm4, %xmm4, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - vxorpd %xmm1, %xmm1, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - vxorps %ymm4, %ymm4, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - vxorpd %ymm1, %ymm1, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - vpxor %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - vpxor %ymm3, %ymm3, %ymm5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 01
+# CHECK-NEXT: Index 0123456789 0123456789
+
+# CHECK: [0,0] DeER . . . . . .. subl %eax, %eax
+# CHECK-NEXT: [0,1] D=eER. . . . . .. subq %rax, %rax
+# CHECK-NEXT: [0,2] D==eeER . . . . .. xorl %eax, %eax
+# CHECK-NEXT: [0,3] D====eeER . . . . .. xorq %rax, %rax
+# CHECK-NEXT: [0,4] DeE-----R . . . . .. pcmpgtb %mm2, %mm2
+# CHECK-NEXT: [0,5] D=eE----R . . . . .. pcmpgtd %mm2, %mm2
+# CHECK-NEXT: [0,6] D==eE---R . . . . .. pcmpgtw %mm2, %mm2
+# CHECK-NEXT: [0,7] DeE-----R . . . . .. pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: [0,8] .DeE----R . . . . .. pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: [0,9] .D=eeeE-R . . . . .. pcmpgtq %xmm2, %xmm2
+# CHECK-NEXT: [0,10] .D====eER . . . . .. pcmpgtw %xmm2, %xmm2
+# CHECK-NEXT: [0,11] .D=eE---R . . . . .. vpcmpgtb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,12] .D==eE--R . . . . .. vpcmpgtd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,13] .D===eeeER. . . . .. vpcmpgtq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,14] .D======eER . . . .. vpcmpgtw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,15] .D=======eER . . . .. vpcmpgtb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,16] . D======eER . . . .. vpcmpgtd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,17] . D======eeeER . . . .. vpcmpgtq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,18] . D=======eE-R . . . .. vpcmpgtw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,19] . D=======eE-R . . . .. vpcmpgtb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,20] . D========eER . . . .. vpcmpgtd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,21] . D=========eeeER . . .. vpcmpgtq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,22] . D============eER . . .. vpcmpgtw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,23] . D=============eER . . .. vpcmpgtb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,24] . D============eER . . .. vpcmpgtd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,25] . D============eeeER . .. vpcmpgtq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,26] . D=============eE-R . .. vpcmpgtw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,27] . DeE--------------R . .. psubb %mm2, %mm2
+# CHECK-NEXT: [0,28] . D=eE-------------R . .. psubd %mm2, %mm2
+# CHECK-NEXT: [0,29] . D==eE------------R . .. psubq %mm2, %mm2
+# CHECK-NEXT: [0,30] . D===eE-----------R . .. psubw %mm2, %mm2
+# CHECK-NEXT: [0,31] . D===eE-----------R . .. psubb %xmm2, %xmm2
+# CHECK-NEXT: [0,32] . D===eE----------R . .. psubd %xmm2, %xmm2
+# CHECK-NEXT: [0,33] . D====eE---------R . .. psubq %xmm2, %xmm2
+# CHECK-NEXT: [0,34] . D=====eE--------R . .. psubw %xmm2, %xmm2
+# CHECK-NEXT: [0,35] . D===========eE--R . .. vpsubb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,36] . D============eE-R . .. vpsubd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,37] . D=============eER . .. vpsubq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,38] . D==============eER . .. vpsubw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,39] . D===============eER . .. vpsubb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,40] . D===============eER . .. vpsubd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,41] . D================eER. .. vpsubq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,42] . D=================eER .. vpsubw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,43] . D==================eER .. vpsubb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,44] . D==================eER .. vpsubd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,45] . D==================eER .. vpsubq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,46] . D==================eER .. vpsubw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,47] . D===================eER .. vpsubb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,48] . .D==================eER .. vpsubd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,49] . .D==================eER .. vpsubq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,50] . .D==================eER .. vpsubw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,51] . .DeE------------------R .. andnps %xmm0, %xmm0
+# CHECK-NEXT: [0,52] . .DeE------------------R .. andnpd %xmm1, %xmm1
+# CHECK-NEXT: [0,53] . .D====eE--------------R .. vandnps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: [0,54] . .D=eE-----------------R .. vandnpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: [0,55] . .D=====eE-------------R .. vandnps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: [0,56] . . D===eE--------------R .. vandnpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: [0,57] . . DeE-----------------R .. pandn %mm2, %mm2
+# CHECK-NEXT: [0,58] . . D=====eE------------R .. pandn %xmm2, %xmm2
+# CHECK-NEXT: [0,59] . . D==================eER .. vpandn %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,60] . . D===================eER.. vpandn %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,61] . . D======eE-------------R.. vandnps %xmm2, %xmm2, %xmm5
+# CHECK-NEXT: [0,62] . . D====eE---------------R.. vandnpd %xmm1, %xmm1, %xmm5
+# CHECK-NEXT: [0,63] . . D====================eER. vpandn %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,64] . . D=====eE--------------R. vandnps %ymm2, %ymm2, %ymm5
+# CHECK-NEXT: [0,65] . . D===eE----------------R. vandnpd %ymm1, %ymm1, %ymm5
+# CHECK-NEXT: [0,66] . . D===================eER. vpandn %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,67] . . D====eE---------------R. xorps %xmm0, %xmm0
+# CHECK-NEXT: [0,68] . . D====eE---------------R. xorpd %xmm1, %xmm1
+# CHECK-NEXT: [0,69] . . D=====eE--------------R. vxorps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: [0,70] . . D======eE-------------R. vxorpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: [0,71] . . D======eE-------------R. vxorps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: [0,72] . . D=======eE-----------R. vxorpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: [0,73] . . D=====eE-------------R. pxor %mm2, %mm2
+# CHECK-NEXT: [0,74] . . D========eE----------R. pxor %xmm2, %xmm2
+# CHECK-NEXT: [0,75] . . D==================eER. vpxor %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,76] . . D===================eER vpxor %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,77] . . D=========eE----------R vxorps %xmm4, %xmm4, %xmm5
+# CHECK-NEXT: [0,78] . . D=========eE----------R vxorpd %xmm1, %xmm1, %xmm3
+# CHECK-NEXT: [0,79] . . D=========eE----------R vxorps %ymm4, %ymm4, %ymm5
+# CHECK-NEXT: [0,80] . . D=======eE-----------R vxorpd %ymm1, %ymm1, %ymm3
+# CHECK-NEXT: [0,81] . . D=========eE---------R vpxor %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,82] . . D=========eE---------R vpxor %ymm3, %ymm3, %ymm5
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 subl %eax, %eax
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 subq %rax, %rax
+# CHECK-NEXT: 2. 1 3.0 0.0 0.0 xorl %eax, %eax
+# CHECK-NEXT: 3. 1 5.0 0.0 0.0 xorq %rax, %rax
+# CHECK-NEXT: 4. 1 1.0 1.0 5.0 pcmpgtb %mm2, %mm2
+# CHECK-NEXT: 5. 1 2.0 0.0 4.0 pcmpgtd %mm2, %mm2
+# CHECK-NEXT: 6. 1 3.0 0.0 3.0 pcmpgtw %mm2, %mm2
+# CHECK-NEXT: 7. 1 1.0 1.0 5.0 pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: 8. 1 1.0 0.0 4.0 pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: 9. 1 2.0 0.0 1.0 pcmpgtq %xmm2, %xmm2
+# CHECK-NEXT: 10. 1 5.0 0.0 0.0 pcmpgtw %xmm2, %xmm2
+# CHECK-NEXT: 11. 1 2.0 2.0 3.0 vpcmpgtb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 12. 1 3.0 0.0 2.0 vpcmpgtd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 13. 1 4.0 0.0 0.0 vpcmpgtq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 14. 1 7.0 0.0 0.0 vpcmpgtw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 15. 1 8.0 0.0 0.0 vpcmpgtb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 16. 1 7.0 0.0 0.0 vpcmpgtd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 17. 1 7.0 0.0 0.0 vpcmpgtq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 18. 1 8.0 1.0 1.0 vpcmpgtw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 19. 1 8.0 1.0 1.0 vpcmpgtb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 20. 1 9.0 0.0 0.0 vpcmpgtd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 21. 1 10.0 0.0 0.0 vpcmpgtq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 22. 1 13.0 0.0 0.0 vpcmpgtw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 23. 1 14.0 0.0 0.0 vpcmpgtb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 24. 1 13.0 0.0 0.0 vpcmpgtd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 25. 1 13.0 0.0 0.0 vpcmpgtq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 26. 1 14.0 1.0 1.0 vpcmpgtw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 27. 1 1.0 0.0 14.0 psubb %mm2, %mm2
+# CHECK-NEXT: 28. 1 2.0 0.0 13.0 psubd %mm2, %mm2
+# CHECK-NEXT: 29. 1 3.0 0.0 12.0 psubq %mm2, %mm2
+# CHECK-NEXT: 30. 1 4.0 0.0 11.0 psubw %mm2, %mm2
+# CHECK-NEXT: 31. 1 4.0 0.0 11.0 psubb %xmm2, %xmm2
+# CHECK-NEXT: 32. 1 4.0 0.0 10.0 psubd %xmm2, %xmm2
+# CHECK-NEXT: 33. 1 5.0 0.0 9.0 psubq %xmm2, %xmm2
+# CHECK-NEXT: 34. 1 6.0 0.0 8.0 psubw %xmm2, %xmm2
+# CHECK-NEXT: 35. 1 12.0 0.0 2.0 vpsubb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 36. 1 13.0 0.0 1.0 vpsubd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 37. 1 14.0 0.0 0.0 vpsubq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 38. 1 15.0 0.0 0.0 vpsubw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 39. 1 16.0 0.0 0.0 vpsubb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 40. 1 16.0 0.0 0.0 vpsubd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 41. 1 17.0 0.0 0.0 vpsubq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 42. 1 18.0 0.0 0.0 vpsubw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 43. 1 19.0 0.0 0.0 vpsubb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 44. 1 19.0 0.0 0.0 vpsubd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 45. 1 19.0 0.0 0.0 vpsubq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 46. 1 19.0 0.0 0.0 vpsubw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 47. 1 20.0 1.0 0.0 vpsubb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 48. 1 19.0 1.0 0.0 vpsubd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 49. 1 19.0 1.0 0.0 vpsubq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 50. 1 19.0 1.0 0.0 vpsubw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 51. 1 1.0 1.0 18.0 andnps %xmm0, %xmm0
+# CHECK-NEXT: 52. 1 1.0 1.0 18.0 andnpd %xmm1, %xmm1
+# CHECK-NEXT: 53. 1 5.0 0.0 14.0 vandnps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: 54. 1 2.0 0.0 17.0 vandnpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: 55. 1 6.0 0.0 13.0 vandnps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: 56. 1 4.0 2.0 14.0 vandnpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 57. 1 1.0 0.0 17.0 pandn %mm2, %mm2
+# CHECK-NEXT: 58. 1 6.0 0.0 12.0 pandn %xmm2, %xmm2
+# CHECK-NEXT: 59. 1 19.0 2.0 0.0 vpandn %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 60. 1 20.0 0.0 0.0 vpandn %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 61. 1 7.0 0.0 13.0 vandnps %xmm2, %xmm2, %xmm5
+# CHECK-NEXT: 62. 1 5.0 0.0 15.0 vandnpd %xmm1, %xmm1, %xmm5
+# CHECK-NEXT: 63. 1 21.0 0.0 0.0 vpandn %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 64. 1 6.0 0.0 14.0 vandnps %ymm2, %ymm2, %ymm5
+# CHECK-NEXT: 65. 1 4.0 0.0 16.0 vandnpd %ymm1, %ymm1, %ymm5
+# CHECK-NEXT: 66. 1 20.0 0.0 0.0 vpandn %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 67. 1 5.0 5.0 15.0 xorps %xmm0, %xmm0
+# CHECK-NEXT: 68. 1 5.0 1.0 15.0 xorpd %xmm1, %xmm1
+# CHECK-NEXT: 69. 1 6.0 0.0 14.0 vxorps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: 70. 1 7.0 1.0 13.0 vxorpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: 71. 1 7.0 0.0 13.0 vxorps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: 72. 1 8.0 1.0 11.0 vxorpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 73. 1 6.0 6.0 13.0 pxor %mm2, %mm2
+# CHECK-NEXT: 74. 1 9.0 2.0 10.0 pxor %xmm2, %xmm2
+# CHECK-NEXT: 75. 1 19.0 0.0 0.0 vpxor %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 76. 1 20.0 0.0 0.0 vpxor %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 77. 1 10.0 10.0 10.0 vxorps %xmm4, %xmm4, %xmm5
+# CHECK-NEXT: 78. 1 10.0 1.0 10.0 vxorpd %xmm1, %xmm1, %xmm3
+# CHECK-NEXT: 79. 1 10.0 10.0 10.0 vxorps %ymm4, %ymm4, %ymm5
+# CHECK-NEXT: 80. 1 8.0 0.0 11.0 vxorpd %ymm1, %ymm1, %ymm3
+# CHECK-NEXT: 81. 1 10.0 1.0 9.0 vpxor %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 82. 1 10.0 1.0 9.0 vpxor %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 9.0 0.7 5.6 <total>
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