[llvm] [NFC][TableGen] Add {} for `else` when `if` body has {} (PR #139420)
Rahul Joshi via llvm-commits
llvm-commits at lists.llvm.org
Sat May 10 17:13:48 PDT 2025
https://github.com/jurahul created https://github.com/llvm/llvm-project/pull/139420
None
>From ae7e8ca23a9b5d6fa9cf8d1e548726f3a72a0b34 Mon Sep 17 00:00:00 2001
From: Rahul Joshi <rjoshi at nvidia.com>
Date: Sat, 10 May 2025 17:09:43 -0700
Subject: [PATCH] [NFC][TableGen] Add {} for `else` when `if` body has {}
---
llvm/lib/TableGen/Record.cpp | 3 ++-
llvm/lib/TableGen/TGParser.cpp | 5 +++--
llvm/utils/TableGen/AsmMatcherEmitter.cpp | 15 ++++++++++-----
llvm/utils/TableGen/AsmWriterEmitter.cpp | 6 ++++--
llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp | 10 +++++-----
llvm/utils/TableGen/Basic/VTEmitter.cpp | 3 ++-
llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp | 3 ++-
llvm/utils/TableGen/Common/CodeGenInstruction.cpp | 6 ++++--
llvm/utils/TableGen/Common/CodeGenSchedule.cpp | 3 ++-
.../Common/GlobalISel/GlobalISelMatchTable.cpp | 12 ++++++++----
.../TableGen/Common/GlobalISel/PatternParser.cpp | 3 ++-
.../utils/TableGen/Common/GlobalISel/Patterns.cpp | 3 ++-
llvm/utils/TableGen/CompressInstEmitter.cpp | 3 ++-
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 12 ++++++++----
llvm/utils/TableGen/FastISelEmitter.cpp | 7 ++++---
llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp | 6 ++++--
llvm/utils/TableGen/GlobalISelEmitter.cpp | 6 ++++--
.../TableGen/MacroFusionPredicatorEmitter.cpp | 3 ++-
llvm/utils/TableGen/OptionParserEmitter.cpp | 12 ++++++++----
llvm/utils/TableGen/PseudoLoweringEmitter.cpp | 6 ++++--
llvm/utils/TableGen/RegisterBankEmitter.cpp | 3 ++-
llvm/utils/TableGen/SubtargetEmitter.cpp | 6 ++++--
22 files changed, 88 insertions(+), 48 deletions(-)
diff --git a/llvm/lib/TableGen/Record.cpp b/llvm/lib/TableGen/Record.cpp
index f3d54e6083e48..fe2f000e2e49c 100644
--- a/llvm/lib/TableGen/Record.cpp
+++ b/llvm/lib/TableGen/Record.cpp
@@ -751,8 +751,9 @@ const Init *ListInit::convertInitializerTo(const RecTy *Ty) const {
Elements.push_back(CI);
if (CI != I)
Changed = true;
- } else
+ } else {
return nullptr;
+ }
if (!Changed)
return this;
diff --git a/llvm/lib/TableGen/TGParser.cpp b/llvm/lib/TableGen/TGParser.cpp
index 423daf6bd5d07..5cad9e74c10bd 100644
--- a/llvm/lib/TableGen/TGParser.cpp
+++ b/llvm/lib/TableGen/TGParser.cpp
@@ -1928,9 +1928,10 @@ const Init *TGParser::ParseOperation(Record *CurRec, const RecTy *ItemType) {
const auto *Arg2 = cast<TypedInit>(Args[2]);
assert(isa<IntRecTy>(Arg2->getType()));
RHS = Arg2;
- } else
+ } else {
// (start, end, 1)
RHS = IntInit::get(Records, 1);
+ }
}
return TernOpInit::get(TernOpInit::RANGE, LHS, MHS, RHS,
IntRecTy::get(Records)->getListTy())
@@ -1946,7 +1947,7 @@ const Init *TGParser::ParseOperation(Record *CurRec, const RecTy *ItemType) {
const RecTy *Type = nullptr;
tgtok::TokKind LexCode = Lex.getCode();
- Lex.Lex(); // eat the operation
+ Lex.Lex(); // Eat the operation.
switch (LexCode) {
default: llvm_unreachable("Unhandled code!");
case tgtok::XDag:
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index a3a739e6636a5..cd2223ca74111 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -1347,8 +1347,9 @@ void AsmMatcherInfo::buildRegisterClasses(
CI->ClassName = RC.getName();
CI->Name = "MCK_" + RC.getName();
CI->ValueName = RC.getName();
- } else
+ } else {
CI->ValueName = CI->ValueName + "," + RC.getName();
+ }
const Init *DiagnosticType = Def->getValueInit("DiagnosticType");
if (const StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
@@ -1379,8 +1380,9 @@ void AsmMatcherInfo::buildRegisterClasses(
CI->ClassName = std::string(Rec->getName());
CI->Name = "MCK_" + Rec->getName().str();
CI->ValueName = std::string(Rec->getName());
- } else
+ } else {
CI->ValueName = CI->ValueName + "," + Rec->getName().str();
+ }
}
}
@@ -1663,13 +1665,14 @@ void AsmMatcherInfo::buildInfo() {
// Add the alias to the matchables list.
NewMatchables.push_back(std::move(AliasII));
}
- } else
+ } else {
// FIXME: The tied operands checking is not yet integrated with the
// framework for reporting multiple near misses. To prevent invalid
// formats from being matched with an alias if a tied-operands check
// would otherwise have disallowed it, we just disallow such constructs
// in TableGen completely.
II->buildAliasResultOperands(!ReportMultipleNearMisses);
+ }
}
if (!NewMatchables.empty())
Matchables.insert(Matchables.end(),
@@ -2303,9 +2306,10 @@ emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
<< utostr(std::get<2>(KV.first)) << " },\n";
}
OS << "};\n\n";
- } else
+ } else {
OS << "static const uint8_t TiedAsmOperandTable[][3] = "
"{ /* empty */ {0, 0, 0} };\n\n";
+ }
OS << "namespace {\n";
@@ -2503,8 +2507,9 @@ static void emitValidateOperandClass(const CodeGenTarget &Target,
OS << " return " << Info.Target.getName() << "AsmParser::Match_"
<< CI.DiagnosticType << ";\n";
OS << " break;\n";
- } else
+ } else {
OS << " break;\n";
+ }
OS << " }\n";
}
OS << " } // end switch (Kind)\n\n";
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index d0ec4fc8e23a6..6c0d67f6d6076 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -660,8 +660,9 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
if (hasAltNames) {
for (const Record *R : AltNameIndices)
emitRegisterNameString(O, R->getName(), Registers);
- } else
+ } else {
emitRegisterNameString(O, "", Registers);
+ }
if (hasAltNames) {
O << " switch(AltIdx) {\n"
@@ -969,8 +970,9 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
if (!Rec->isValueUnset("MCOperandPredicate")) {
MCOpPredicates.push_back(Rec);
Entry = MCOpPredicates.size();
- } else
+ } else {
break; // No conditions on this operand at all
+ }
}
IAP.addCond(
std::string(formatv("AliasPatternCond::K_Custom, {}", Entry)));
diff --git a/llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp b/llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
index 24dc3272d8071..bc42efa3b2e9c 100644
--- a/llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
+++ b/llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
@@ -444,15 +444,16 @@ void CodeGenIntrinsic::setProperty(const Record *R) {
int64_t Lower = R->getValueAsInt("Lower");
int64_t Upper = R->getValueAsInt("Upper");
addArgAttribute(ArgNo, Range, Lower, Upper);
- } else
+ } else {
llvm_unreachable("Unknown property!");
+ }
}
bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const {
if (ParamIdx >= IS.ParamTys.size())
return false;
- return (IS.ParamTys[ParamIdx]->isSubClassOf("LLVMQualPointerType") ||
- IS.ParamTys[ParamIdx]->isSubClassOf("LLVMAnyPointerType"));
+ return IS.ParamTys[ParamIdx]->isSubClassOf("LLVMQualPointerType") ||
+ IS.ParamTys[ParamIdx]->isSubClassOf("LLVMAnyPointerType");
}
bool CodeGenIntrinsic::isParamImmArg(unsigned ParamIdx) const {
@@ -461,8 +462,7 @@ bool CodeGenIntrinsic::isParamImmArg(unsigned ParamIdx) const {
if (ParamIdx >= ArgumentAttributes.size())
return false;
ArgAttribute Val{ImmArg, 0, 0};
- return std::binary_search(ArgumentAttributes[ParamIdx].begin(),
- ArgumentAttributes[ParamIdx].end(), Val);
+ return llvm::binary_search(ArgumentAttributes[ParamIdx], Val);
}
void CodeGenIntrinsic::addArgAttribute(unsigned Idx, ArgAttrKind AK, uint64_t V,
diff --git a/llvm/utils/TableGen/Basic/VTEmitter.cpp b/llvm/utils/TableGen/Basic/VTEmitter.cpp
index 07840d397bb15..040f37c3a5e1e 100644
--- a/llvm/utils/TableGen/Basic/VTEmitter.cpp
+++ b/llvm/utils/TableGen/Basic/VTEmitter.cpp
@@ -79,8 +79,9 @@ static void vTtoGetLlvmTyString(raw_ostream &OS, const Record *VT) {
OS << "Type::getInt" << OutputVTSize << "Ty(Context)";
else
OS << "Type::getIntNTy(Context, " << OutputVTSize << ")";
- } else
+ } else {
llvm_unreachable("Unhandled case");
+ }
if (IsVector)
OS << ", " << VT->getValueAsInt("nElem") << ")";
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index febcb1fd662f5..5d60de79b72ca 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -2405,8 +2405,9 @@ TreePatternNode::getComplexPatternInfo(const CodeGenDAGPatterns &CGP) const {
if (!DI)
return nullptr;
Rec = DI->getDef();
- } else
+ } else {
Rec = getOperator();
+ }
if (!Rec->isSubClassOf("ComplexPattern"))
return nullptr;
diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
index ecef9caa9c3d8..a7d9516a26682 100644
--- a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
@@ -34,9 +34,10 @@ CGIOperandList::CGIOperandList(const Record *R) : TheDef(R) {
PrintFatalError(R->getLoc(),
R->getName() +
": invalid def name for output list: use 'outs'");
- } else
+ } else {
PrintFatalError(R->getLoc(),
R->getName() + ": invalid output list: use 'outs'");
+ }
NumDefs = OutDI->getNumArgs();
@@ -46,9 +47,10 @@ CGIOperandList::CGIOperandList(const Record *R) : TheDef(R) {
PrintFatalError(R->getLoc(),
R->getName() +
": invalid def name for input list: use 'ins'");
- } else
+ } else {
PrintFatalError(R->getLoc(),
R->getName() + ": invalid input list: use 'ins'");
+ }
unsigned MIOperandNo = 0;
std::set<std::string> OperandNames;
diff --git a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
index 8e8b3196c91b0..acf38d1d661d8 100644
--- a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
@@ -2016,8 +2016,9 @@ void CodeGenSchedModels::collectRWResources(unsigned RWIdx, bool IsRead,
if (Alias->getValueInit("SchedModel")->isComplete()) {
AliasProcIndices.push_back(
getProcModel(Alias->getValueAsDef("SchedModel")).Index);
- } else
+ } else {
AliasProcIndices = ProcIndices;
+ }
const CodeGenSchedRW &AliasRW = getSchedRW(Alias->getValueAsDef("AliasRW"));
assert(AliasRW.IsRead == IsRead && "cannot alias reads to writes");
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
index 4c809b4016cbd..2cb357927250f 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
@@ -2015,9 +2015,10 @@ void TempRegRenderer::emitRenderOpcodes(MatchTable &Table,
if (SubRegIdx) {
assert(!IsDef);
Table << MatchTable::Opcode("GIR_AddTempSubRegister");
- } else
+ } else {
Table << MatchTable::Opcode(NeedsFlags ? "GIR_AddTempRegister"
: "GIR_AddSimpleTempRegister");
+ }
Table << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID)
<< MatchTable::Comment("TempRegID")
@@ -2035,8 +2036,9 @@ void TempRegRenderer::emitRenderOpcodes(MatchTable &Table,
if (IsDead)
RegFlags += "|RegState::Dead";
Table << MatchTable::NamedValue(2, RegFlags);
- } else
+ } else {
Table << MatchTable::IntValue(2, 0);
+ }
if (SubRegIdx)
Table << MatchTable::NamedValue(2, SubRegIdx->getQualifiedName());
@@ -2064,8 +2066,9 @@ void ImmRenderer::emitRenderOpcodes(MatchTable &Table,
<< MatchTable::ULEB128Value(InsnID) << MatchTable::Comment("Type")
<< *CImmLLT << MatchTable::Comment("Imm")
<< MatchTable::IntValue(8, Imm) << MatchTable::LineBreak;
- } else
+ } else {
emitAddImm(Table, Rule, InsnID, Imm);
+ }
}
//===- SubRegIndexRenderer ------------------------------------------------===//
@@ -2156,8 +2159,9 @@ bool BuildMIAction::canMutate(RuleMatcher &Rule,
if (Insn != &OM.getInstructionMatcher() ||
OM.getOpIdx() != Renderer.index())
return false;
- } else
+ } else {
return false;
+ }
}
return true;
diff --git a/llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp b/llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp
index cb423ce142fb7..e62f63ae53ba4 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp
@@ -134,8 +134,9 @@ PatternParser::parseInstructionPattern(const Init &Arg, StringRef Name) {
getDagWithOperatorOfSubClass(Arg, BuiltinPattern::ClassName)) {
Pat = std::make_unique<BuiltinPattern>(*BP->getOperatorAsDef(DiagLoc),
insertStrRef(Name));
- } else
+ } else {
return nullptr;
+ }
for (unsigned K = 0; K < DagPat->getNumArgs(); ++K) {
const Init *Arg = DagPat->getArg(K);
diff --git a/llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp b/llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp
index 0b84a9bbe6343..981761821300e 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp
@@ -840,8 +840,9 @@ bool PatFragPattern::mapInputCodeExpansions(const CodeExpansions &ParentCEs,
if (It == ParentCEs.end()) {
if (!PF.handleUnboundInParam(ParamName, ArgName, DiagLoc))
return false;
- } else
+ } else {
PatFragCEs.declare(ParamName, It->second);
+ }
continue;
}
diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp
index ea617b2067831..b981d38e283f3 100644
--- a/llvm/utils/TableGen/CompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -278,8 +278,9 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec,
<< (IsSourceInst ? "input " : "output ")
<< "Dag. No validation time check possible for values of "
"fixed immediate.\n");
- } else
+ } else {
llvm_unreachable("Unhandled CompressPat argument type!");
+ }
}
}
}
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index 8b0f48aca259c..82e47fd8932b3 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -439,8 +439,9 @@ unsigned MatcherTableEmitter::EmitMatcher(const Matcher *N,
if (!OmitComments) {
OS << "/*" << format_decimal(CurrentIdx, IndexWidth) << "*/";
OS.indent(Indent) << "/*Scope*/ ";
- } else
+ } else {
OS.indent(Indent);
+ }
}
unsigned ChildSize = SM->getChild(i)->getSize();
@@ -558,8 +559,9 @@ unsigned MatcherTableEmitter::EmitMatcher(const Matcher *N,
if (PredNo < 8) {
OperandBytes = -1;
OS << "OPC_CheckPredicate" << PredNo << ", ";
- } else
+ } else {
OS << "OPC_CheckPredicate, ";
+ }
}
if (PredNo >= 8 || Pred.usesOperands())
@@ -916,9 +918,10 @@ unsigned MatcherTableEmitter::EmitMatcher(const Matcher *N,
OS << "OPC_EmitCopyToReg" << Slot << ", "
<< getQualifiedName(Reg->TheDef) << ",\n";
--Bytes;
- } else
+ } else {
OS << "OPC_EmitCopyToReg, " << Slot << ", "
<< getQualifiedName(Reg->TheDef) << ",\n";
+ }
}
return Bytes;
@@ -1042,8 +1045,9 @@ unsigned MatcherTableEmitter::EmitMatcher(const Matcher *N,
OS.indent(FullIndexWidth + Indent)
<< "// Dst: " << SNT->getPattern().getDstPattern() << '\n';
}
- } else
+ } else {
OS << '\n';
+ }
return 4 + !CompressVTs + !CompressNodeInfo + NumTypeBytes +
NumOperandBytes + NumCoveredBytes;
diff --git a/llvm/utils/TableGen/FastISelEmitter.cpp b/llvm/utils/TableGen/FastISelEmitter.cpp
index 26625da393851..3818660cce5fb 100644
--- a/llvm/utils/TableGen/FastISelEmitter.cpp
+++ b/llvm/utils/TableGen/FastISelEmitter.cpp
@@ -280,9 +280,9 @@ struct OperandsSignature {
RC = &Target.getRegisterClass(OpLeafRec);
else if (OpLeafRec->isSubClassOf("Register"))
RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
- else if (OpLeafRec->isSubClassOf("ValueType")) {
+ else if (OpLeafRec->isSubClassOf("ValueType"))
RC = OrigDstRC;
- } else
+ else
return false;
// For now, this needs to be a register class of some sort.
@@ -294,8 +294,9 @@ struct OperandsSignature {
if (DstRC) {
if (DstRC != RC && !DstRC->hasSubClass(RC))
return false;
- } else
+ } else {
DstRC = RC;
+ }
Operands.push_back(OpKind::getReg());
}
return true;
diff --git a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
index 4e491f8983ec0..36c0cf529e32f 100644
--- a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
@@ -1277,8 +1277,9 @@ bool CombineRuleBuilder::checkSemantics() {
"patterns");
return false;
}
- } else
+ } else {
IsUsingCXXPatterns = isa<CXXPattern>(Pat);
+ }
assert(Pat);
const auto *IP = dyn_cast<InstructionPattern>(Pat);
@@ -1610,8 +1611,9 @@ bool CombineRuleBuilder::emitMatchPattern(CodeExpansions &CE,
return false;
} else if (isa<BuiltinPattern>(&IP)) {
llvm_unreachable("No match builtins known!");
- } else
+ } else {
llvm_unreachable("Unknown kind of InstructionPattern!");
+ }
// Emit remaining patterns
const bool IsUsingCustomCXXAction = hasOnlyCXXApplyPatterns();
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 8d0403ae43068..ecd7997871273 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -756,9 +756,10 @@ Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
if (isa<IntInit>(SrcInit)) {
InsnMatcher.addPredicate<InstructionOpcodeMatcher>(
&Target.getInstruction(RK.getDef("G_CONSTANT")));
- } else
+ } else {
return failedImport(
"Unable to deduce gMIR opcode to handle Src (which is a leaf)");
+ }
} else {
SrcGIEquivOrNull = findNodeEquiv(Src.getOperator());
if (!SrcGIEquivOrNull)
@@ -850,9 +851,10 @@ Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
OperandMatcher &OM =
InsnMatcher.addOperand(OpIdx++, Src.getName(), TempOpIdx);
OM.addPredicate<LiteralIntOperandMatcher>(SrcIntInit->getValue());
- } else
+ } else {
return failedImport(
"Unable to deduce gMIR opcode to handle Src (which is a leaf)");
+ }
} else {
assert(SrcGIOrNull &&
"Expected to have already found an equivalent Instruction");
diff --git a/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp b/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
index ce509c7ef1aba..0b77586b39d2c 100644
--- a/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
+++ b/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
@@ -263,10 +263,11 @@ void MacroFusionPredicatorEmitter::emitBothPredicate(const Record *Predicate,
OS.indent(2) << " return false;";
}
OS << "\n";
- } else
+ } else {
PrintFatalError(Predicate->getLoc(),
"Unsupported predicate for both instruction: " +
Predicate->getType()->getAsString());
+ }
}
void MacroFusionPredicatorEmitter::run(raw_ostream &OS) {
diff --git a/llvm/utils/TableGen/OptionParserEmitter.cpp b/llvm/utils/TableGen/OptionParserEmitter.cpp
index be0ed1eca35bb..3aede8df0dc55 100644
--- a/llvm/utils/TableGen/OptionParserEmitter.cpp
+++ b/llvm/utils/TableGen/OptionParserEmitter.cpp
@@ -389,8 +389,9 @@ static void emitOptionParser(const RecordKeeper &Records, raw_ostream &OS) {
OS << ",\n";
OS << " ";
writeCstring(OS, R.getValueAsString("HelpText"));
- } else
+ } else {
OS << ", nullptr";
+ }
// Not using Visibility specific text for group help.
emitHelpTextsForVariants(OS, {});
@@ -428,8 +429,9 @@ static void emitOptionParser(const RecordKeeper &Records, raw_ostream &OS) {
GroupFlags = DI->getDef()->getValueAsListInit("Flags");
GroupVis = DI->getDef()->getValueAsListInit("Visibility");
OS << getOptionName(*DI->getDef());
- } else
+ } else {
OS << "INVALID";
+ }
// The option alias (if any).
OS << ", ";
@@ -490,8 +492,9 @@ static void emitOptionParser(const RecordKeeper &Records, raw_ostream &OS) {
OS << ",\n";
OS << " ";
writeCstring(OS, R.getValueAsString("HelpText"));
- } else
+ } else {
OS << ", nullptr";
+ }
std::vector<std::pair<std::vector<std::string>, StringRef>>
HelpTextsForVariants;
@@ -522,8 +525,9 @@ static void emitOptionParser(const RecordKeeper &Records, raw_ostream &OS) {
writeCstring(OS, R.getValueAsString("Values"));
else if (!isa<UnsetInit>(R.getValueInit("ValuesCode"))) {
OS << getOptionName(R) << "_Values";
- } else
+ } else {
OS << "nullptr";
+ }
};
auto IsMarshallingOption = [](const Record &R) {
diff --git a/llvm/utils/TableGen/PseudoLoweringEmitter.cpp b/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
index 44a17a3906fe6..e65265e152efb 100644
--- a/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
+++ b/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
@@ -126,8 +126,9 @@ void PseudoLoweringEmitter::addOperandMapping(
auto &Entry = OperandMap[MIOpNo];
Entry.Kind = OpData::Imm;
Entry.Data.Imm = *BI->convertInitializerToInt();
- } else
+ } else {
llvm_unreachable("Unhandled pseudo-expansion argument type!");
+ }
}
void PseudoLoweringEmitter::evaluateExpansion(const Record *Rec) {
@@ -281,8 +282,9 @@ void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
<< " }\n";
}
o << " }\n return true;";
- } else
+ } else {
o << " return false;";
+ }
o << "\n}\n\n";
}
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index e931000bb9c71..e00b06ca3f537 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -370,8 +370,9 @@ void RegisterBankEmitter::emitBaseClassImplementation(
if (HasAmbigousOrMissingEntry) {
OS << " if (RegBankID != InvalidRegBankID)\n"
" return getRegBank(RegBankID);\n";
- } else
+ } else {
OS << " return getRegBank(RegBankID);\n";
+ }
OS << " }\n"
" llvm_unreachable(llvm::Twine(\"Target needs to handle register "
"class ID "
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 96cbfba9bd27f..18cb78196cfae 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -2085,8 +2085,9 @@ void SubtargetEmitter::run(raw_ostream &OS) {
if (SchedModels.hasItineraries()) {
OS << Target << "Stages, " << Target << "OperandCycles, " << Target
<< "ForwardingPaths";
- } else
+ } else {
OS << "nullptr, nullptr, nullptr";
+ }
OS << ");\n}\n\n";
OS << "} // end namespace llvm\n\n";
@@ -2216,8 +2217,9 @@ void SubtargetEmitter::run(raw_ostream &OS) {
if (SchedModels.hasItineraries()) {
OS << Target << "Stages, " << Target << "OperandCycles, " << Target
<< "ForwardingPaths";
- } else
+ } else {
OS << "nullptr, nullptr, nullptr";
+ }
OS << ") {}\n\n";
emitSchedModelHelpers(ClassName, OS);
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