[llvm] 9bd38bf - [AVR][NFC] Improve format of TD files (#139249)
via llvm-commits
llvm-commits at lists.llvm.org
Fri May 9 22:37:23 PDT 2025
Author: Ben Shi
Date: 2025-05-10T13:37:20+08:00
New Revision: 9bd38bfca3debd9554c71b5325fd52ba516f2bdd
URL: https://github.com/llvm/llvm-project/commit/9bd38bfca3debd9554c71b5325fd52ba516f2bdd
DIFF: https://github.com/llvm/llvm-project/commit/9bd38bfca3debd9554c71b5325fd52ba516f2bdd.diff
LOG: [AVR][NFC] Improve format of TD files (#139249)
Added:
Modified:
llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
llvm/lib/Target/AVR/AVRInstrInfo.td
llvm/lib/Target/AVR/AVRRegisterInfo.cpp
llvm/lib/Target/AVR/AVRRegisterInfo.td
llvm/lib/Target/AVR/AVRShiftExpand.cpp
llvm/lib/Target/AVR/AVRTargetMachine.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
index da861227d1acd..20d35340bd15a 100644
--- a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
@@ -413,8 +413,7 @@ template <> bool AVRDAGToDAGISel::select<ISD::LOAD>(SDNode *N) {
case MVT::i8:
if (ProgMemBank == 0) {
unsigned Opc = Subtarget->hasLPMX() ? AVR::LPMRdZ : AVR::LPMBRdZ;
- ResNode =
- CurDAG->getMachineNode(Opc, DL, MVT::i8, MVT::Other, Ptr);
+ ResNode = CurDAG->getMachineNode(Opc, DL, MVT::i8, MVT::Other, Ptr);
} else {
// Do not combine the LDI instruction into the ELPM pseudo instruction,
// since it may be reused by other ELPM pseudo instructions.
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td b/llvm/lib/Target/AVR/AVRInstrInfo.td
index 606ce50f5f19e..b00938ca64221 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -1467,208 +1467,106 @@ def WDR : F16<0b1001010110101000, (outs), (ins), "wdr", []>;
//: TODO: Optimize this for wider types AND optimize the following code
// compile int foo(char a, char b, char c, char d) {return d+b;}
// looks like a missed sext_inreg opportunity.
-def SEXT
- : ExtensionPseudo<(outs DREGS
- : $dst),
- (ins GPR8
- : $src),
- "sext\t$dst, $src",
- [(set i16
- : $dst, (sext i8
- : $src))]>;
-
-def ZEXT
- : ExtensionPseudo<(outs DREGS
- : $dst),
- (ins GPR8
- : $src),
- "zext\t$dst, $src",
- [(set i16
- : $dst, (zext i8
- : $src))]>;
+def SEXT : ExtensionPseudo<(outs DREGS:$dt), (ins GPR8:$src), "sext\t$dt, $src",
+ [(set i16:$dt, (sext i8:$src))]>;
+
+def ZEXT : ExtensionPseudo<(outs DREGS:$dt), (ins GPR8:$src), "zext\t$dt, $src",
+ [(set i16:$dt, (zext i8:$src))]>;
// This pseudo gets expanded into a movw+adiw thus it clobbers SREG.
-let Defs = [SREG],
- hasSideEffects = 0 in def FRMIDX : Pseudo<(outs DLDREGS
- : $dst),
- (ins DLDREGS
- : $src, i16imm
- : $src2),
- "frmidx\t$dst, $src, $src2", []>;
+let Defs = [SREG], hasSideEffects = 0 in
+def FRMIDX : Pseudo<(outs DLDREGS:$dst), (ins DLDREGS:$src, i16imm:$src2),
+ "frmidx\t$dst, $src, $src2", []>;
// This pseudo is either converted to a regular store or a push which clobbers
// SP.
-def STDSPQRr : StorePseudo<(outs),
- (ins memspi
- : $dst, GPR8
- : $src),
- "stdstk\t$dst, $src", [(store i8
- : $src, addr
- : $dst)]>;
+def STDSPQRr : StorePseudo<(outs), (ins memspi:$dst, GPR8:$src),
+ "stdstk\t$dst, $src", [(store i8:$src, addr:$dst)]>;
// This pseudo is either converted to a regular store or a push which clobbers
// SP.
-def STDWSPQRr : StorePseudo<(outs),
- (ins memspi
- : $dst, DREGS
- : $src),
- "stdwstk\t$dst, $src", [(store i16
- : $src, addr
- : $dst)]>;
+def STDWSPQRr : StorePseudo<(outs), (ins memspi:$dt, DREGS:$src),
+ "stdwstk\t$dt, $src", [(store i16:$src, addr:$dt)]>;
// SP read/write pseudos.
-let hasSideEffects = 0 in {
- let Uses = [SP] in def SPREAD : Pseudo<(outs DREGS
- : $dst),
- (ins GPRSP
- : $src),
- "spread\t$dst, $src", []>;
-
- let Defs = [SP] in def SPWRITE : Pseudo<(outs GPRSP
- : $dst),
- (ins DREGS
- : $src),
- "spwrite\t$dst, $src", []>;
+let hasSideEffects = 0 in {
+ let Uses = [SP] in
+ def SPREAD : Pseudo<(outs DREGS:$dst), (ins GPRSP:$src), "spread\t$dst, $src",
+ []>;
+ let Defs = [SP] in
+ def SPWRITE : Pseudo<(outs GPRSP:$dst), (ins DREGS:$src),
+ "spwrite\t$dst, $src", []>;
}
-def Select8 : SelectPseudo<(outs GPR8
- : $dst),
- (ins GPR8
- : $src, GPR8
- : $src2, i8imm
- : $cc),
- "# Select8 PSEUDO", [(set i8
- : $dst, (AVRselectcc i8
- : $src, i8
- : $src2, imm
- : $cc))]>;
-
-def Select16 : SelectPseudo<(outs DREGS
- : $dst),
- (ins DREGS
- : $src, DREGS
- : $src2, i8imm
- : $cc),
- "# Select16 PSEUDO", [(set i16
- : $dst, (AVRselectcc i16
- : $src, i16
- : $src2, imm
- : $cc))]>;
-
-def Lsl8 : ShiftPseudo<(outs GPR8
- : $dst),
- (ins GPR8
- : $src, GPR8
- : $cnt),
- "# Lsl8 PSEUDO", [(set i8
- : $dst, (AVRlslLoop i8
- : $src, i8
- : $cnt))]>;
-
-def Lsl16 : ShiftPseudo<(outs DREGS
- : $dst),
- (ins DREGS
- : $src, GPR8
- : $cnt),
- "# Lsl16 PSEUDO", [(set i16
- : $dst, (AVRlslLoop i16
- : $src, i8
- : $cnt))]>;
+def Select8 : SelectPseudo<(outs GPR8:$dst),
+ (ins GPR8:$src, GPR8:$src2, i8imm:$cc),
+ "# Select8 PSEUDO",
+ [(set i8:$dst,
+ (AVRselectcc i8:$src, i8:$src2, imm:$cc))]>;
+
+def Select16 : SelectPseudo<(outs DREGS:$dst),
+ (ins DREGS:$src, DREGS:$src2, i8imm:$cc),
+ "# Select16 PSEUDO",
+ [(set i16:$dst,
+ (AVRselectcc i16:$src, i16:$src2, imm:$cc))]>;
+
+def Lsl8 : ShiftPseudo<(outs GPR8:$dst), (ins GPR8:$src, GPR8:$cnt),
+ "# Lsl8 PSEUDO",
+ [(set i8:$dst, (AVRlslLoop i8:$src, i8:$cnt))]>;
+
+def Lsl16 : ShiftPseudo<(outs DREGS:$dst), (ins DREGS:$src, GPR8:$cnt),
+ "# Lsl16 PSEUDO",
+ [(set i16:$dst, (AVRlslLoop i16:$src, i8:$cnt))]>;
def Lsl32 : ShiftPseudo<(outs DREGS:$dstlo, DREGS:$dsthi),
(ins DREGS:$srclo, DREGS:$srchi, i8imm:$cnt),
"# Lsl32 PSEUDO",
- [(set i16:$dstlo, i16:$dsthi, (AVRlslw i16:$srclo, i16:$srchi, i8:$cnt))]>;
-
-def Lsr8 : ShiftPseudo<(outs GPR8
- : $dst),
- (ins GPR8
- : $src, GPR8
- : $cnt),
- "# Lsr8 PSEUDO", [(set i8
- : $dst, (AVRlsrLoop i8
- : $src, i8
- : $cnt))]>;
-
-def Lsr16 : ShiftPseudo<(outs DREGS
- : $dst),
- (ins DREGS
- : $src, GPR8
- : $cnt),
- "# Lsr16 PSEUDO", [(set i16
- : $dst, (AVRlsrLoop i16
- : $src, i8
- : $cnt))]>;
+ [(set i16:$dstlo, i16:$dsthi,
+ (AVRlslw i16:$srclo, i16:$srchi, i8:$cnt))]>;
+
+def Lsr8 : ShiftPseudo<(outs GPR8:$dst), (ins GPR8:$src, GPR8:$cnt),
+ "# Lsr8 PSEUDO",
+ [(set i8:$dst, (AVRlsrLoop i8:$src, i8:$cnt))]>;
+
+def Lsr16 : ShiftPseudo<(outs DREGS:$dst), (ins DREGS:$src, GPR8:$cnt),
+ "# Lsr16 PSEUDO",
+ [(set i16:$dst, (AVRlsrLoop i16:$src, i8:$cnt))]>;
def Lsr32 : ShiftPseudo<(outs DREGS:$dstlo, DREGS:$dsthi),
(ins DREGS:$srclo, DREGS:$srchi, i8imm:$cnt),
"# Lsr32 PSEUDO",
- [(set i16:$dstlo, i16:$dsthi, (AVRlsrw i16:$srclo, i16:$srchi, i8:$cnt))]>;
-
-def Rol8 : ShiftPseudo<(outs GPR8
- : $dst),
- (ins GPR8
- : $src, GPR8
- : $cnt),
- "# Rol8 PSEUDO", [(set i8
- : $dst, (AVRrolLoop i8
- : $src, i8
- : $cnt))]>;
-
-def Rol16 : ShiftPseudo<(outs DREGS
- : $dst),
- (ins DREGS
- : $src, GPR8
- : $cnt),
- "# Rol16 PSEUDO", [(set i16
- : $dst, (AVRrolLoop i16
- : $src, i8
- : $cnt))]>;
-
-def Ror8 : ShiftPseudo<(outs GPR8
- : $dst),
- (ins GPR8
- : $src, GPR8
- : $cnt),
- "# Ror8 PSEUDO", [(set i8
- : $dst, (AVRrorLoop i8
- : $src, i8
- : $cnt))]>;
-
-def Ror16 : ShiftPseudo<(outs DREGS
- : $dst),
- (ins DREGS
- : $src, GPR8
- : $cnt),
- "# Ror16 PSEUDO", [(set i16
- : $dst, (AVRrorLoop i16
- : $src, i8
- : $cnt))]>;
-
-def Asr8 : ShiftPseudo<(outs GPR8
- : $dst),
- (ins GPR8
- : $src, GPR8
- : $cnt),
- "# Asr8 PSEUDO", [(set i8
- : $dst, (AVRasrLoop i8
- : $src, i8
- : $cnt))]>;
-
-def Asr16 : ShiftPseudo<(outs DREGS
- : $dst),
- (ins DREGS
- : $src, GPR8
- : $cnt),
- "# Asr16 PSEUDO", [(set i16
- : $dst, (AVRasrLoop i16
- : $src, i8
- : $cnt))]>;
+ [(set i16:$dstlo, i16:$dsthi,
+ (AVRlsrw i16:$srclo, i16:$srchi, i8:$cnt))]>;
+
+def Rol8 : ShiftPseudo<(outs GPR8:$dst), (ins GPR8:$src, GPR8:$cnt),
+ "# Rol8 PSEUDO",
+ [(set i8:$dst, (AVRrolLoop i8:$src, i8:$cnt))]>;
+
+def Rol16 : ShiftPseudo<(outs DREGS:$dst), (ins DREGS:$src, GPR8:$cnt),
+ "# Rol16 PSEUDO",
+ [(set i16:$dst, (AVRrolLoop i16:$src, i8:$cnt))]>;
+
+def Ror8 : ShiftPseudo<(outs GPR8:$dst), (ins GPR8:$src, GPR8:$cnt),
+ "# Ror8 PSEUDO",
+ [(set i8:$dst, (AVRrorLoop i8:$src, i8:$cnt))]>;
+
+def Ror16 : ShiftPseudo<(outs DREGS:$dst), (ins DREGS:$src, GPR8:$cnt),
+ "# Ror16 PSEUDO",
+ [(set i16:$dst, (AVRrorLoop i16:$src, i8:$cnt))]>;
+
+def Asr8 : ShiftPseudo<(outs GPR8:$dst), (ins GPR8:$src, GPR8:$cnt),
+ "# Asr8 PSEUDO",
+ [(set i8:$dst, (AVRasrLoop i8:$src, i8:$cnt))]>;
+
+def Asr16 : ShiftPseudo<(outs DREGS:$dst), (ins DREGS:$src, GPR8:$cnt),
+ "# Asr16 PSEUDO",
+ [(set i16:$dst, (AVRasrLoop i16:$src, i8:$cnt))]>;
def Asr32 : ShiftPseudo<(outs DREGS:$dstlo, DREGS:$dsthi),
(ins DREGS:$srclo, DREGS:$srchi, i8imm:$cnt),
"# Asr32 PSEUDO",
- [(set i16:$dstlo, i16:$dsthi, (AVRasrw i16:$srclo, i16:$srchi, i8:$cnt))]>;
+ [(set i16:$dstlo, i16:$dsthi,
+ (AVRasrw i16:$srclo, i16:$srchi, i8:$cnt))]>;
// lowered to a copy from the zero register.
let usesCustomInserter=1 in
@@ -1683,12 +1581,7 @@ def CopyZero : Pseudo<(outs GPR8:$rd), (ins), "clrz\t$rd", [(set i8:$rd, 0)]>;
// the add instruction always writes the carry flag
def : Pat<(addc i8 : $src, i8 : $src2), (ADDRdRr i8 : $src, i8 : $src2)>;
-def : Pat<(addc DREGS
- : $src, DREGS
- : $src2),
- (ADDWRdRr DREGS
- : $src, DREGS
- : $src2)>;
+def : Pat<(addc DREGS:$src, DREGS:$src2), (ADDWRdRr DREGS:$src, DREGS:$src2)>;
// all sub instruction variants always writes the carry flag
def : Pat<(subc i8 : $src, i8 : $src2), (SUBRdRr i8 : $src, i8 : $src2)>;
@@ -1698,48 +1591,26 @@ def : Pat<(subc i16 : $src, imm : $src2), (SUBIWRdK i16 : $src, imm : $src2)>;
// These patterns convert add (x, -imm) to sub (x, imm) since we dont have
// any add with imm instructions. Also take care of the adiw/sbiw instructions.
-def : Pat<(add i16
- : $src1, imm0_63_neg
- : $src2),
- (SBIWRdK i16
- : $src1, (imm0_63_neg
- : $src2))>,
- Requires<[HasADDSUBIW]>;
-def : Pat<(add i16
- : $src1, imm
- : $src2),
- (SUBIWRdK i16
- : $src1, (imm16_neg_XFORM imm
- : $src2))>;
-def : Pat<(addc i16
- : $src1, imm
- : $src2),
- (SUBIWRdK i16
- : $src1, (imm16_neg_XFORM imm
- : $src2))>;
-
-def : Pat<(add i8
- : $src1, imm
- : $src2),
- (SUBIRdK i8
- : $src1, (imm8_neg_XFORM imm
- : $src2))>;
-def : Pat<(addc i8
- : $src1, imm
- : $src2),
- (SUBIRdK i8
- : $src1, (imm8_neg_XFORM imm
- : $src2))>;
-def : Pat<(adde i8
- : $src1, imm
- : $src2),
- (SBCIRdK i8
- : $src1, (imm8_neg_XFORM imm
- : $src2))>;
+def : Pat<(add i16:$s1, imm0_63_neg:$s2), (SBIWRdK i16:$s1, (imm0_63_neg:$s2))>,
+ Requires<[HasADDSUBIW]>;
+
+def : Pat<(add i16:$src1, imm:$src2),
+ (SUBIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>;
+
+def : Pat<(addc i16:$src1, imm:$src2),
+ (SUBIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>;
+
+def : Pat<(add i8:$src1, imm:$src2),
+ (SUBIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>;
+
+def : Pat<(addc i8:$src1, imm:$src2),
+ (SUBIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>;
+
+def : Pat<(adde i8:$src1, imm:$src2),
+ (SBCIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>;
// Emit NEGWRd with an extra zero register operand.
-def : Pat<(ineg i16:$src),
- (NEGWRd i16:$src, (CopyZero))>;
+def : Pat<(ineg i16:$src), (NEGWRd i16:$src, (CopyZero))>;
// Calls.
let Predicates = [HasJMPCALL] in {
@@ -1759,48 +1630,36 @@ def : Pat<(i16(anyext i8:$src)),
def : Pat<(i8(trunc i16 : $src)), (EXTRACT_SUBREG i16 : $src, sub_lo)>;
// sext_inreg
-def : Pat<(sext_inreg i16
- : $src, i8),
- (SEXT(i8(EXTRACT_SUBREG i16
- : $src, sub_lo)))>;
+def : Pat<(sext_inreg i16:$s, i8), (SEXT(i8(EXTRACT_SUBREG i16:$s, sub_lo)))>;
// GlobalAddress
def : Pat<(i16(AVRWrapper tglobaladdr : $dst)), (LDIWRdK tglobaladdr : $dst)>;
-def : Pat<(add i16
- : $src, (AVRWrapper tglobaladdr
- : $src2)),
- (SUBIWRdK i16
- : $src, tglobaladdr
- : $src2)>;
+def : Pat<(add i16:$src, (AVRWrapper tglobaladdr:$src2)),
+ (SUBIWRdK i16:$src, tglobaladdr:$src2)>;
def : Pat<(i8(load(AVRWrapper tglobaladdr:$dst))),
(LDSRdK tglobaladdr:$dst)>,
- Requires<[HasSRAM, HasNonTinyEncoding]>;
+ Requires<[HasSRAM, HasNonTinyEncoding]>;
def : Pat<(i8(load(AVRWrapper tglobaladdr:$dst))),
(LDSRdKTiny tglobaladdr:$dst)>,
- Requires<[HasSRAM, HasTinyEncoding]>;
+ Requires<[HasSRAM, HasTinyEncoding]>;
def : Pat<(i16(load(AVRWrapper tglobaladdr:$dst))),
(LDSWRdK tglobaladdr:$dst)>,
- Requires<[HasSRAM, HasNonTinyEncoding]>;
+ Requires<[HasSRAM, HasNonTinyEncoding]>;
def : Pat<(store i8:$src, (i16(AVRWrapper tglobaladdr:$dst))),
(STSKRr tglobaladdr:$dst, i8:$src)>,
- Requires<[HasSRAM, HasNonTinyEncoding]>;
+ Requires<[HasSRAM, HasNonTinyEncoding]>;
def : Pat<(store i8:$src, (i16(AVRWrapper tglobaladdr:$dst))),
(STSKRrTiny tglobaladdr:$dst, i8:$src)>,
- Requires<[HasSRAM, HasTinyEncoding]>;
+ Requires<[HasSRAM, HasTinyEncoding]>;
def : Pat<(store i16:$src, (i16(AVRWrapper tglobaladdr:$dst))),
(STSWKRr tglobaladdr:$dst, i16:$src)>,
- Requires<[HasSRAM, HasNonTinyEncoding]>;
+ Requires<[HasSRAM, HasNonTinyEncoding]>;
// BlockAddress
-def : Pat<(i16(AVRWrapper tblockaddress
- : $dst)),
- (LDIWRdK tblockaddress
- : $dst)>;
-
-def : Pat<(i8(trunc(AVRlsrwn DLDREGS
- : $src, (i16 8)))),
- (EXTRACT_SUBREG DREGS
- : $src, sub_hi)>;
+def : Pat<(i16(AVRWrapper tblockaddress :$dst)), (LDIWRdK tblockaddress:$dst)>;
+
+def : Pat<(i8(trunc(AVRlsrwn DLDREGS:$src, (i16 8)))),
+ (EXTRACT_SUBREG DREGS:$src, sub_hi)>;
// :FIXME: DAGCombiner produces an shl node after legalization from these seq:
// BR_JT -> (mul x, 2) -> (shl x, 1)
diff --git a/llvm/lib/Target/AVR/AVRRegisterInfo.cpp b/llvm/lib/Target/AVR/AVRRegisterInfo.cpp
index 6e66b4c111be9..051affe7110dd 100644
--- a/llvm/lib/Target/AVR/AVRRegisterInfo.cpp
+++ b/llvm/lib/Target/AVR/AVRRegisterInfo.cpp
@@ -169,15 +169,12 @@ bool AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// Copy the frame pointer.
if (STI.hasMOVW()) {
- BuildMI(MBB, MI, dl, TII.get(AVR::MOVWRdRr), DstReg)
- .addReg(AVR::R29R28);
+ BuildMI(MBB, MI, dl, TII.get(AVR::MOVWRdRr), DstReg).addReg(AVR::R29R28);
} else {
Register DstLoReg, DstHiReg;
splitReg(DstReg, DstLoReg, DstHiReg);
- BuildMI(MBB, MI, dl, TII.get(AVR::MOVRdRr), DstLoReg)
- .addReg(AVR::R28);
- BuildMI(MBB, MI, dl, TII.get(AVR::MOVRdRr), DstHiReg)
- .addReg(AVR::R29);
+ BuildMI(MBB, MI, dl, TII.get(AVR::MOVRdRr), DstLoReg).addReg(AVR::R28);
+ BuildMI(MBB, MI, dl, TII.get(AVR::MOVRdRr), DstHiReg).addReg(AVR::R29);
}
assert(Offset > 0 && "Invalid offset");
diff --git a/llvm/lib/Target/AVR/AVRRegisterInfo.td b/llvm/lib/Target/AVR/AVRRegisterInfo.td
index 4e8e8234f6213..21b4aedea44cd 100644
--- a/llvm/lib/Target/AVR/AVRRegisterInfo.td
+++ b/llvm/lib/Target/AVR/AVRRegisterInfo.td
@@ -112,14 +112,13 @@ let SubRegIndices = [sub_lo, sub_hi], CoveredBySubRegs = 1 in {
// Main 8-bit register class.
def GPR8 : RegisterClass<"AVR", [i8], 8,
- (
- // Return value and argument registers.
- add R24, R25, R18, R19, R20, R21, R22, R23,
- // Scratch registers.
- R30, R31, R26, R27,
- // Callee saved registers.
- R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
- R9, R8, R7, R6, R5, R4, R3, R2, R0, R1)>;
+ (// Return value and argument registers.
+ add R24, R25, R18, R19, R20, R21, R22, R23,
+ // Scratch registers.
+ R30, R31, R26, R27,
+ // Callee saved registers.
+ R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
+ R9, R8, R7, R6, R5, R4, R3, R2, R0, R1)>;
// Simple lower registers r0..r15
def GPR8lo : RegisterClass<"AVR", [i8], 8,
@@ -128,13 +127,12 @@ def GPR8lo : RegisterClass<"AVR", [i8], 8,
// 8-bit register class for instructions which take immediates.
def LD8 : RegisterClass<"AVR", [i8], 8,
- (
- // Return value and arguments.
- add R24, R25, R18, R19, R20, R21, R22, R23,
- // Scratch registers.
- R30, R31, R26, R27,
- // Callee saved registers.
- R28, R29, R17, R16)>;
+ (// Return value and arguments.
+ add R24, R25, R18, R19, R20, R21, R22, R23,
+ // Scratch registers.
+ R30, R31, R26, R27,
+ // Callee saved registers.
+ R28, R29, R17, R16)>;
// Simple lower registers r16..r23
def LD8lo : RegisterClass<"AVR", [i8], 8,
@@ -142,17 +140,16 @@ def LD8lo : RegisterClass<"AVR", [i8], 8,
// Main 16-bit pair register class.
def DREGS : RegisterClass<"AVR", [i16], 8,
- (
- // Return value and arguments.
- add R25R24, R19R18, R21R20, R23R22,
- // Scratch registers.
- R31R30, R27R26,
- // Callee saved registers.
- R29R28, R17R16, R15R14, R13R12, R11R10, R9R8,
- R7R6, R5R4, R3R2, R1R0,
- // Pseudo regs for unaligned 16-bits
- R26R25, R24R23, R22R21, R20R19, R18R17, R16R15,
- R14R13, R12R11, R10R9)>;
+ (// Return value and arguments.
+ add R25R24, R19R18, R21R20, R23R22,
+ // Scratch registers.
+ R31R30, R27R26,
+ // Callee saved registers.
+ R29R28, R17R16, R15R14, R13R12, R11R10, R9R8,
+ R7R6, R5R4, R3R2, R1R0,
+ // Pseudo regs for unaligned 16-bits
+ R26R25, R24R23, R22R21, R20R19, R18R17, R16R15,
+ R14R13, R12R11, R10R9)>;
// Lower 16-bit pair registers in R0..R15, only used in inline assembly.
def DREGSlo
@@ -161,42 +158,38 @@ def DREGSlo
// Lower 16-bit pair registers in r16..r23, only used in inline assembly.
def DREGSLD8lo : RegisterClass<"AVR", [i16], 8,
- (
- // Return value and arguments.
- add R19R18, R21R20, R23R22,
- // Callee saved registers.
- R17R16)>;
+ (// Return value and arguments.
+ add R19R18, R21R20, R23R22,
+ // Callee saved registers.
+ R17R16)>;
// 16-bit pair register class for movw
def DREGSMOVW : RegisterClass<"AVR", [i16], 8,
- (
- // Return value and arguments.
- add R25R24, R19R18, R21R20, R23R22,
- // Scratch registers.
- R31R30, R27R26,
- // Callee saved registers.
- R29R28, R17R16, R15R14, R13R12, R11R10, R9R8,
- R7R6, R5R4, R3R2, R1R0)>;
+ (// Return value and arguments.
+ add R25R24, R19R18, R21R20, R23R22,
+ // Scratch registers.
+ R31R30, R27R26,
+ // Callee saved registers.
+ R29R28, R17R16, R15R14, R13R12, R11R10, R9R8,
+ R7R6, R5R4, R3R2, R1R0)>;
// 16-bit register class for immediate instructions.
def DLDREGS : RegisterClass<"AVR", [i16], 8,
- (
- // Return value and arguments.
- add R25R24, R19R18, R21R20, R23R22,
- // Scratch registers.
- R31R30, R27R26,
- // Callee saved registers.
- R29R28, R17R16)>;
+ (// Return value and arguments.
+ add R25R24, R19R18, R21R20, R23R22,
+ // Scratch registers.
+ R31R30, R27R26,
+ // Callee saved registers.
+ R29R28, R17R16)>;
// 16-bit register class for the adiw/sbiw instructions.
def IWREGS : RegisterClass<"AVR", [i16], 8,
- (
- // Return value and arguments.
- add R25R24,
- // Scratch registers.
- R31R30, R27R26,
- // Callee saved registers.
- R29R28)>;
+ (// Return value and arguments.
+ add R25R24,
+ // Scratch registers.
+ R31R30, R27R26,
+ // Callee saved registers.
+ R29R28)>;
// 16-bit register class for the ld and st instructions.
// AKA X,Y, and Z
@@ -204,7 +197,7 @@ def PTRREGS : RegisterClass<"AVR", [i16], 8,
(add R27R26, // X
R29R28, // Y
R31R30), // Z
- ptr>;
+ ptr>;
// 16-bit register class for the ldd and std instructions.
// AKA Y and Z.
diff --git a/llvm/lib/Target/AVR/AVRShiftExpand.cpp b/llvm/lib/Target/AVR/AVRShiftExpand.cpp
index f549ae62c8b2e..46103bd2b5ddc 100644
--- a/llvm/lib/Target/AVR/AVRShiftExpand.cpp
+++ b/llvm/lib/Target/AVR/AVRShiftExpand.cpp
@@ -52,7 +52,8 @@ bool AVRShiftExpand::runOnFunction(Function &F) {
if (!I.isShift())
// Only expand shift instructions (shl, lshr, ashr).
continue;
- if (I.getType() == Type::getInt8Ty(Ctx) || I.getType() == Type::getInt16Ty(Ctx))
+ if (I.getType() == Type::getInt8Ty(Ctx) ||
+ I.getType() == Type::getInt16Ty(Ctx))
// Only expand non-8-bit and non-16-bit shifts, since those are expanded
// directly during isel.
continue;
diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.cpp b/llvm/lib/Target/AVR/AVRTargetMachine.cpp
index 5eaa642d19903..72544b0afd8d2 100644
--- a/llvm/lib/Target/AVR/AVRTargetMachine.cpp
+++ b/llvm/lib/Target/AVR/AVRTargetMachine.cpp
@@ -126,9 +126,7 @@ bool AVRPassConfig::addInstSelector() {
return false;
}
-void AVRPassConfig::addPreSched2() {
- addPass(createAVRExpandPseudoPass());
-}
+void AVRPassConfig::addPreSched2() { addPass(createAVRExpandPseudoPass()); }
void AVRPassConfig::addPreEmitPass() {
// Must run branch selection immediately preceding the asm printer.
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