[llvm] 34ecc4b - [gn] port c60db55568e82fd

[Nico Weber via llvm-commits]

Author: Nico Weber
Date: 2025-05-09T19:15:58-04:00
New Revision: 34ecc4b9b8329a833234a84e4cf81c2b7741b4de

URL: https://github.com/llvm/llvm-project/commit/34ecc4b9b8329a833234a84e4cf81c2b7741b4de
DIFF: https://github.com/llvm/llvm-project/commit/34ecc4b9b8329a833234a84e4cf81c2b7741b4de.diff

LOG: [gn] port c60db55568e82fd

Added: 
    

Modified: 
    llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn

Removed: 
    


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diff  --git a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
index c59ed2267a98e..ad73f51e57eaf 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
@@ -79,6 +79,12 @@ tablegen("RISCVGenRegisterBank") {
   td_file = "RISCV.td"
 }
 
+tablegen("RISCVGenSDNodeInfo") {
+  visibility = [ ":LLVMRISCVCodeGen" ]
+  args = [ "-gen-sd-node-info" ]
+  td_file = "RISCV.td"
+}
+
 static_library("LLVMRISCVCodeGen") {
   deps = [
     ":RISCVGenCompressInstEmitter",
@@ -90,6 +96,7 @@ static_library("LLVMRISCVCodeGen") {
     ":RISCVGenPostLegalizeGICombiner",
     ":RISCVGenPreLegalizeGICombiner",
     ":RISCVGenRegisterBank",
+    ":RISCVGenSDNodeInfo",
 
     # See https://reviews.llvm.org/D69130
     "AsmParser:RISCVGenAsmMatcher",