[llvm] [RISCV] Add 2^N + 2^M expanding pattern for mul (PR #137954)

[Min-Yih Hsu via llvm-commits]

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@@ -502,24 +502,23 @@ define i32 @muli32_p18(i32 %a) nounwind {
 ;
 ; RV32IM-LABEL: muli32_p18:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    li a1, 18
-; RV32IM-NEXT:    mul a0, a0, a1
+; RV32IM-NEXT:    slli a1, a0, 1
+; RV32IM-NEXT:    slli a0, a0, 4
+; RV32IM-NEXT:    add a0, a0, a1
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli32_p18:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    li a1, 18
-; RV64I-NEXT:    call __muldi3
-; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    slli a1, a0, 1
+; RV64I-NEXT:    slli a0, a0, 4
+; RV64I-NEXT:    add a0, a0, a1
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mshockwave wrote:

In the absent of M (more precisely, Zmmul), RISCV simply asks it to expand the node. Otherwise, we set a custom legalization action for i32 under RV64 which prepends a sign extension node preemptively, in the hope that we would select mulw rather than creating an extra sext instruction later.
The result will be correct (https://alive2.llvm.org/ce/z/tDgeiL), as long as we don't care the high 32-bit part, that is.

https://github.com/llvm/llvm-project/pull/137954