[llvm] [RISCV] Implement codegen for XAndesPerf lea instructions (PR #137925)

[Craig Topper via llvm-commits]

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@@ -125,19 +125,25 @@ class NDSRVInstBFO<bits<3> funct3, string opcodestr>
   let mayStore = 0;
 }
 
-class NDSRVInstRR<bits<7> funct7, string opcodestr,
-                  string argstr = "$rd, $rs1, $rs2">
+class NDSRVInstRR<bits<7> funct7, string opcodestr>
     : RVInstR<funct7, 0b000, OPC_CUSTOM_2,
               (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
-              opcodestr, argstr>,
+              opcodestr, "$rd, $rs1, $rs2">,
       Sched<[WriteIALU, ReadIALU, ReadIALU]> {
   let hasSideEffects = 0;
   let mayLoad = 0;
   let mayStore = 0;
 }
 
 class NDSRVInstLEA<bits<7> funct7, string opcodestr>
-    : NDSRVInstRR<funct7, opcodestr, "$rd, $rs2, $rs1">;
+    : RVInstR<funct7, 0b000, OPC_CUSTOM_2,
+              (outs GPR:$rd), (ins GPR:$rs2, GPR:$rs1),
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topperc wrote:

Please add a comment about why the operands are reversed.

https://github.com/llvm/llvm-project/pull/137925