[llvm] 269f5fe - [AARCH64] Add support for Cortex-A320 (#139055)
via llvm-commits
llvm-commits at lists.llvm.org
Fri May 9 08:24:52 PDT 2025
Author: Ties Stuij
Date: 2025-05-09T16:24:48+01:00
New Revision: 269f5fe91ef9abec5dcdc574b5fb7e7f35269f29
URL: https://github.com/llvm/llvm-project/commit/269f5fe91ef9abec5dcdc574b5fb7e7f35269f29
DIFF: https://github.com/llvm/llvm-project/commit/269f5fe91ef9abec5dcdc574b5fb7e7f35269f29.diff
LOG: [AARCH64] Add support for Cortex-A320 (#139055)
This patch adds initial support for the recently announced Armv9
Cortex-A320 processor.
For more information, including the Technical Reference Manual, see:
https://developer.arm.com/Processors/Cortex-A320
---------
Co-authored-by: Oliver Stannard <oliver.stannard at arm.com>
Added:
clang/test/Driver/aarch64-cortex-a320.c
clang/test/Driver/print-enabled-extensions/aarch64-cortex-a320.c
Modified:
clang/docs/ReleaseNotes.rst
clang/test/Misc/target-invalid-cpu-note/aarch64.c
llvm/lib/Target/AArch64/AArch64Processors.td
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
llvm/lib/TargetParser/Host.cpp
llvm/unittests/TargetParser/Host.cpp
llvm/unittests/TargetParser/TargetParserTest.cpp
Removed:
################################################################################
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index f7d56cfd19ce5..3f38d510f7ad1 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -728,6 +728,9 @@ X86 Support
Arm and AArch64 Support
^^^^^^^^^^^^^^^^^^^^^^^
+
+- Support has been added for the following processors (command-line identifiers in parentheses):
+ - Arm Cortex-A320 (``cortex-a320``)
- For ARM targets, cc1as now considers the FPU's features for the selected CPU or Architecture.
- The ``+nosimd`` attribute is now fully supported for ARM. Previously, this had no effect when being used with
ARM targets, however this will now disable NEON instructions being generated. The ``simd`` option is
diff --git a/clang/test/Driver/aarch64-cortex-a320.c b/clang/test/Driver/aarch64-cortex-a320.c
new file mode 100644
index 0000000000000..d0b180bff85d7
--- /dev/null
+++ b/clang/test/Driver/aarch64-cortex-a320.c
@@ -0,0 +1,6 @@
+// RUN: not %clang --target=arm-arm-none-eabi -mcpu=cortex-a320 %s 2>&1 | FileCheck %s
+// CHECK: error: unsupported argument {{.*}} to option '-mcpu='
+
+// RUN: %clang -target aarch64 -mcpu=cortex-a320 -### -c %s 2>&1 | FileCheck -check-prefix=A320 %s
+// A320: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a320"
+
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a320.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a320.c
new file mode 100644
index 0000000000000..eed89039f3a19
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a320.c
@@ -0,0 +1,60 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=cortex-a320 | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+// CHECK: Extensions enabled for the given AArch64 target
+// CHECK-EMPTY:
+// CHECK-NEXT: Architecture Feature(s) Description
+// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
+// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
+// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
+// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
+// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
+// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
+// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
+// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
+// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
+// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
+// CHECK-NEXT: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence
+// CHECK-NEXT: FEAT_DotProd Enable dot product support
+// CHECK-NEXT: FEAT_ECV Enable enhanced counter virtualization extension
+// CHECK-NEXT: FEAT_ETE Enable Embedded Trace Extension
+// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
+// CHECK-NEXT: FEAT_FGT Enable fine grained virtualization traps extension
+// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
+// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
+// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
+// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons
+// CHECK-NEXT: FEAT_HCX Enable Armv8.7-A HCRX_EL2 system register
+// CHECK-NEXT: FEAT_I8MM Enable Matrix Multiply Int8 Extension
+// CHECK-NEXT: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions
+// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension
+// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension
+// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets
+// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
+// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
+// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
+// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
+// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
+// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
+// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
+// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
+// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
+// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
+// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
+// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
+// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
+// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
+// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
+// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
+// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
+// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
+// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
+// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
+// CHECK-NEXT: FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction
+// CHECK-NEXT: FEAT_XS Enable Armv8.7-A limited-TLB-maintenance instruction
+
diff --git a/clang/test/Misc/target-invalid-cpu-note/aarch64.c b/clang/test/Misc/target-invalid-cpu-note/aarch64.c
index e8e728a27e410..0a5c485e896be 100644
--- a/clang/test/Misc/target-invalid-cpu-note/aarch64.c
+++ b/clang/test/Misc/target-invalid-cpu-note/aarch64.c
@@ -36,6 +36,7 @@
// CHECK-SAME: {{^}}, apple-s9
// CHECK-SAME: {{^}}, carmel
// CHECK-SAME: {{^}}, cobalt-100
+// CHECK-SAME: {{^}}, cortex-a320
// CHECK-SAME: {{^}}, cortex-a34
// CHECK-SAME: {{^}}, cortex-a35
// CHECK-SAME: {{^}}, cortex-a510
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index e0df19baa54b8..a5f0f6a2eb150 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -17,6 +17,12 @@
def TuneA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
"Cortex-A35 ARM processors">;
+def TuneA320 : SubtargetFeature<"a320", "ARMProcFamily", "CortexA320",
+ "Cortex-A320 ARM processors", [
+ FeatureFuseAES,
+ FeatureFuseAdrpAdd,
+ FeaturePostRAScheduler]>;
+
def TuneA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
"Cortex-A53 ARM processors", [
FeatureFuseAES,
@@ -709,6 +715,16 @@ def TuneOryon : SubtargetFeature<"oryon-1", "ARMProcFamily",
HasV8_6aOps]>;
def ProcessorFeatures {
+ list<SubtargetFeature> A320 = [HasV9_2aOps, FeatureNEON, FeatureMTE,
+ FeatureSVEBitPerm, FeatureFP16FML, FeatureFullFP16,
+ FeatureETE, FeaturePerfMon, FeatureCCIDX,
+ FeatureCCPP, FeatureComplxNum, FeatureCRC,
+ FeatureDotProd, FeatureJS, FeatureLOR,
+ FeatureLSE, FeaturePAN, FeaturePAN_RWV,
+ FeaturePAuth, FeaturePsUAO, FeatureRAS,
+ FeatureRDM, FeatureTRBE, FeatureVH,
+ FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS,
+ FeatureSVE, FeatureSVE2];
list<SubtargetFeature> A53 = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES,
FeatureFPARMv8, FeatureNEON, FeaturePerfMon];
list<SubtargetFeature> A55 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
@@ -1110,10 +1126,12 @@ class ProcessorAlias<string n, string alias> {
def : ProcessorModel<"generic", CortexA510Model, ProcessorFeatures.Generic,
[FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler,
FeatureEnableSelectOptimize]>;
-def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53,
- [TuneA35]>;
def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53,
[TuneA35]>;
+def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53,
+ [TuneA35]>;
+def : ProcessorModel<"cortex-a320", CortexA510Model, ProcessorFeatures.A320,
+ [TuneA320]>;
def : ProcessorModel<"cortex-a53", CortexA53Model, ProcessorFeatures.A53,
[TuneA53]>;
def : ProcessorModel<"cortex-a55", CortexA55Model, ProcessorFeatures.A55,
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index 7b4ded6322098..a28e6bad0dca0 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -175,6 +175,7 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
PrefLoopAlignment = Align(32);
MaxBytesForLoopAlignment = 16;
break;
+ case CortexA320:
case CortexA510:
case CortexA520:
PrefFunctionAlignment = Align(16);
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index 922c2163b8ea9..14acef116708a 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -228,6 +228,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
.Case("0xd14", "cortex-r82ae")
.Case("0xd02", "cortex-a34")
.Case("0xd04", "cortex-a35")
+ .Case("0xd8f", "cortex-a320")
.Case("0xd03", "cortex-a53")
.Case("0xd05", "cortex-a55")
.Case("0xd46", "cortex-a510")
diff --git a/llvm/unittests/TargetParser/Host.cpp b/llvm/unittests/TargetParser/Host.cpp
index 1beed7bd87d18..c13d33e32c6d9 100644
--- a/llvm/unittests/TargetParser/Host.cpp
+++ b/llvm/unittests/TargetParser/Host.cpp
@@ -72,6 +72,9 @@ Serial : 0000000000000000
}
TEST(getLinuxHostCPUName, AArch64) {
+ EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
+ "CPU part : 0xd8f"),
+ "cortex-a320");
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
"CPU part : 0xd03"),
"cortex-a53");
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index b3c470b774de7..0b1c84e6311ba 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1085,6 +1085,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64CPUTests, AArch64CPUTestFixture,
::testing::Values(AArch64CPUTestParams("cortex-a34", "armv8-a"),
AArch64CPUTestParams("cortex-a35", "armv8-a"),
+ AArch64CPUTestParams("cortex-a320", "armv9.2-a"),
AArch64CPUTestParams("cortex-a53", "armv8-a"),
AArch64CPUTestParams("cortex-a55", "armv8.2-a"),
AArch64CPUTestParams("cortex-a510", "armv9-a"),
@@ -1262,7 +1263,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64CPUAliasTestParams::PrintToStringParamName);
// Note: number of CPUs includes aliases.
-static constexpr unsigned NumAArch64CPUArchs = 89;
+static constexpr unsigned NumAArch64CPUArchs = 90;
TEST(TargetParserTest, testAArch64CPUArchList) {
SmallVector<StringRef, NumAArch64CPUArchs> List;
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