[llvm] [Hexagon] Use TargetInstrInfo::RegSubRegPair (PR #138637)
Sudharsan Veeravalli via llvm-commits
llvm-commits at lists.llvm.org
Fri May 9 05:06:29 PDT 2025
https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/138637
>From 8ddc09bada8921f276d32bf757a656c6752944a7 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: Tue, 6 May 2025 12:01:20 +0530
Subject: [PATCH 1/2] [Hexagon] Use TargetInstrInfo::RegSubRegPair
Use the RegSubRegPair struct defined in TargetInstrInfo instead of the custom definitions
in HexagonGenPredicates and HexagonConstantPropogation.
This patch addresses the FIXME's that were there in these passes.
---
.../Hexagon/HexagonConstPropagation.cpp | 292 +++++++++---------
.../Target/Hexagon/HexagonGenPredicate.cpp | 127 ++++----
llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 7 +
3 files changed, 216 insertions(+), 210 deletions(-)
diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
index a0a67bed45e74..740479174c814 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
@@ -77,27 +77,7 @@ namespace {
static uint32_t deduce(const Constant *C);
};
- // A representation of a register as it can appear in a MachineOperand,
- // i.e. a pair register:subregister.
-
- // FIXME: Use TargetInstrInfo::RegSubRegPair. Also duplicated in
- // HexagonGenPredicate
- struct RegisterSubReg {
- Register Reg;
- unsigned SubReg;
-
- explicit RegisterSubReg(unsigned R, unsigned SR = 0) : Reg(R), SubReg(SR) {}
- explicit RegisterSubReg(const MachineOperand &MO)
- : Reg(MO.getReg()), SubReg(MO.getSubReg()) {}
-
- void print(const TargetRegisterInfo *TRI = nullptr) const {
- dbgs() << printReg(Reg, TRI, SubReg);
- }
-
- bool operator== (const RegisterSubReg &R) const {
- return (Reg == R.Reg) && (SubReg == R.SubReg);
- }
- };
+ using RegSubRegPair = TargetInstrInfo::RegSubRegPair;
// Lattice cell, based on that was described in the W-Z paper on constant
// propagation.
@@ -312,7 +292,7 @@ namespace {
using CellMap = MachineConstPropagator::CellMap;
virtual bool evaluate(const MachineInstr &MI, const CellMap &Inputs,
CellMap &Outputs) = 0;
- virtual bool evaluate(const RegisterSubReg &R, const LatticeCell &SrcC,
+ virtual bool evaluate(const RegSubRegPair &R, const LatticeCell &SrcC,
LatticeCell &Result) = 0;
virtual bool evaluate(const MachineInstr &BrI, const CellMap &Inputs,
SetVector<const MachineBasicBlock*> &Targets,
@@ -355,17 +335,19 @@ namespace {
// Helper functions.
- bool getCell(const RegisterSubReg &R, const CellMap &Inputs, LatticeCell &RC);
+ bool getCell(const RegSubRegPair &R, const CellMap &Inputs,
+ LatticeCell &RC);
bool constToInt(const Constant *C, APInt &Val) const;
const ConstantInt *intToConst(const APInt &Val) const;
// Compares.
- bool evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2,
- const CellMap &Inputs, bool &Result);
- bool evaluateCMPri(uint32_t Cmp, const RegisterSubReg &R1, const APInt &A2,
- const CellMap &Inputs, bool &Result);
- bool evaluateCMPrp(uint32_t Cmp, const RegisterSubReg &R1, uint64_t Props2,
- const CellMap &Inputs, bool &Result);
+ bool evaluateCMPrr(uint32_t Cmp, const RegSubRegPair &R1,
+ const RegSubRegPair &R2, const CellMap &Inputs,
+ bool &Result);
+ bool evaluateCMPri(uint32_t Cmp, const RegSubRegPair &R1, const APInt &A2,
+ const CellMap &Inputs, bool &Result);
+ bool evaluateCMPrp(uint32_t Cmp, const RegSubRegPair &R1, uint64_t Props2,
+ const CellMap &Inputs, bool &Result);
bool evaluateCMPii(uint32_t Cmp, const APInt &A1, const APInt &A2,
bool &Result);
bool evaluateCMPpi(uint32_t Cmp, uint32_t Props, const APInt &A2,
@@ -373,53 +355,53 @@ namespace {
bool evaluateCMPpp(uint32_t Cmp, uint32_t Props1, uint32_t Props2,
bool &Result);
- bool evaluateCOPY(const RegisterSubReg &R1, const CellMap &Inputs,
- LatticeCell &Result);
+ bool evaluateCOPY(const RegSubRegPair &R1, const CellMap &Inputs,
+ LatticeCell &Result);
// Logical operations.
- bool evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
- const CellMap &Inputs, LatticeCell &Result);
- bool evaluateANDri(const RegisterSubReg &R1, const APInt &A2,
- const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateANDrr(const RegSubRegPair &R1, const RegSubRegPair &R2,
+ const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateANDri(const RegSubRegPair &R1, const APInt &A2,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateANDii(const APInt &A1, const APInt &A2, APInt &Result);
- bool evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
- const CellMap &Inputs, LatticeCell &Result);
- bool evaluateORri(const RegisterSubReg &R1, const APInt &A2,
- const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateORrr(const RegSubRegPair &R1, const RegSubRegPair &R2,
+ const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateORri(const RegSubRegPair &R1, const APInt &A2,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateORii(const APInt &A1, const APInt &A2, APInt &Result);
- bool evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
- const CellMap &Inputs, LatticeCell &Result);
- bool evaluateXORri(const RegisterSubReg &R1, const APInt &A2,
- const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateXORrr(const RegSubRegPair &R1, const RegSubRegPair &R2,
+ const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateXORri(const RegSubRegPair &R1, const APInt &A2,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateXORii(const APInt &A1, const APInt &A2, APInt &Result);
// Extensions.
- bool evaluateZEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
- const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateZEXTr(const RegSubRegPair &R1, unsigned Width, unsigned Bits,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateZEXTi(const APInt &A1, unsigned Width, unsigned Bits,
APInt &Result);
- bool evaluateSEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
- const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateSEXTr(const RegSubRegPair &R1, unsigned Width, unsigned Bits,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateSEXTi(const APInt &A1, unsigned Width, unsigned Bits,
APInt &Result);
// Leading/trailing bits.
- bool evaluateCLBr(const RegisterSubReg &R1, bool Zeros, bool Ones,
- const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateCLBr(const RegSubRegPair &R1, bool Zeros, bool Ones,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateCLBi(const APInt &A1, bool Zeros, bool Ones, APInt &Result);
- bool evaluateCTBr(const RegisterSubReg &R1, bool Zeros, bool Ones,
- const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateCTBr(const RegSubRegPair &R1, bool Zeros, bool Ones,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateCTBi(const APInt &A1, bool Zeros, bool Ones, APInt &Result);
// Bitfield extract.
- bool evaluateEXTRACTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
- unsigned Offset, bool Signed, const CellMap &Inputs,
- LatticeCell &Result);
+ bool evaluateEXTRACTr(const RegSubRegPair &R1, unsigned Width,
+ unsigned Bits, unsigned Offset, bool Signed,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateEXTRACTi(const APInt &A1, unsigned Bits, unsigned Offset,
bool Signed, APInt &Result);
// Vector operations.
- bool evaluateSplatr(const RegisterSubReg &R1, unsigned Bits, unsigned Count,
- const CellMap &Inputs, LatticeCell &Result);
+ bool evaluateSplatr(const RegSubRegPair &R1, unsigned Bits, unsigned Count,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateSplati(const APInt &A1, unsigned Bits, unsigned Count,
APInt &Result);
};
@@ -630,7 +612,7 @@ void MachineConstPropagator::visitPHI(const MachineInstr &PN) {
LLVM_DEBUG(dbgs() << "Visiting FI(" << printMBBReference(*MB) << "): " << PN);
const MachineOperand &MD = PN.getOperand(0);
- RegisterSubReg DefR(MD);
+ RegSubRegPair DefR(getRegSubRegPair(MD));
assert(DefR.Reg.isVirtual());
bool Changed = false;
@@ -657,7 +639,7 @@ void MachineConstPropagator::visitPHI(const MachineInstr &PN) {
continue;
}
const MachineOperand &SO = PN.getOperand(i);
- RegisterSubReg UseR(SO);
+ RegSubRegPair UseR(getRegSubRegPair(SO));
// If the input is not a virtual register, we don't really know what
// value it holds.
if (!UseR.Reg.isVirtual())
@@ -700,7 +682,7 @@ void MachineConstPropagator::visitNonBranch(const MachineInstr &MI) {
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
- RegisterSubReg DefR(MO);
+ RegSubRegPair DefR(getRegSubRegPair(MO));
// Only track virtual registers.
if (!DefR.Reg.isVirtual())
continue;
@@ -1075,8 +1057,8 @@ bool MachineConstPropagator::run(MachineFunction &MF) {
// --------------------------------------------------------------------
// Machine const evaluator.
-bool MachineConstEvaluator::getCell(const RegisterSubReg &R, const CellMap &Inputs,
- LatticeCell &RC) {
+bool MachineConstEvaluator::getCell(const RegSubRegPair &R,
+ const CellMap &Inputs, LatticeCell &RC) {
if (!R.Reg.isVirtual())
return false;
const LatticeCell &L = Inputs.get(R.Reg);
@@ -1101,8 +1083,9 @@ const ConstantInt *MachineConstEvaluator::intToConst(const APInt &Val) const {
return ConstantInt::get(CX, Val);
}
-bool MachineConstEvaluator::evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1,
- const RegisterSubReg &R2, const CellMap &Inputs, bool &Result) {
+bool MachineConstEvaluator::evaluateCMPrr(uint32_t Cmp, const RegSubRegPair &R1,
+ const RegSubRegPair &R2,
+ const CellMap &Inputs, bool &Result) {
assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
LatticeCell LS1, LS2;
if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2))
@@ -1140,8 +1123,9 @@ bool MachineConstEvaluator::evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1
return IsTrue || IsFalse;
}
-bool MachineConstEvaluator::evaluateCMPri(uint32_t Cmp, const RegisterSubReg &R1,
- const APInt &A2, const CellMap &Inputs, bool &Result) {
+bool MachineConstEvaluator::evaluateCMPri(uint32_t Cmp, const RegSubRegPair &R1,
+ const APInt &A2,
+ const CellMap &Inputs, bool &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS;
if (!getCell(R1, Inputs, LS))
@@ -1167,8 +1151,9 @@ bool MachineConstEvaluator::evaluateCMPri(uint32_t Cmp, const RegisterSubReg &R1
return IsTrue || IsFalse;
}
-bool MachineConstEvaluator::evaluateCMPrp(uint32_t Cmp, const RegisterSubReg &R1,
- uint64_t Props2, const CellMap &Inputs, bool &Result) {
+bool MachineConstEvaluator::evaluateCMPrp(uint32_t Cmp, const RegSubRegPair &R1,
+ uint64_t Props2,
+ const CellMap &Inputs, bool &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS;
if (!getCell(R1, Inputs, LS))
@@ -1360,13 +1345,16 @@ bool MachineConstEvaluator::evaluateCMPpp(uint32_t Cmp, uint32_t Props1,
return false;
}
-bool MachineConstEvaluator::evaluateCOPY(const RegisterSubReg &R1,
- const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateCOPY(const RegSubRegPair &R1,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
return getCell(R1, Inputs, Result);
}
-bool MachineConstEvaluator::evaluateANDrr(const RegisterSubReg &R1,
- const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateANDrr(const RegSubRegPair &R1,
+ const RegSubRegPair &R2,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
const LatticeCell &L1 = Inputs.get(R2.Reg);
const LatticeCell &L2 = Inputs.get(R2.Reg);
@@ -1396,8 +1384,10 @@ bool MachineConstEvaluator::evaluateANDrr(const RegisterSubReg &R1,
return !Result.isBottom();
}
-bool MachineConstEvaluator::evaluateANDri(const RegisterSubReg &R1,
- const APInt &A2, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateANDri(const RegSubRegPair &R1,
+ const APInt &A2,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
if (A2 == -1)
return getCell(R1, Inputs, Result);
@@ -1432,8 +1422,10 @@ bool MachineConstEvaluator::evaluateANDii(const APInt &A1,
return true;
}
-bool MachineConstEvaluator::evaluateORrr(const RegisterSubReg &R1,
- const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateORrr(const RegSubRegPair &R1,
+ const RegSubRegPair &R2,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
const LatticeCell &L1 = Inputs.get(R2.Reg);
const LatticeCell &L2 = Inputs.get(R2.Reg);
@@ -1463,8 +1455,9 @@ bool MachineConstEvaluator::evaluateORrr(const RegisterSubReg &R1,
return !Result.isBottom();
}
-bool MachineConstEvaluator::evaluateORri(const RegisterSubReg &R1,
- const APInt &A2, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateORri(const RegSubRegPair &R1,
+ const APInt &A2, const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
if (A2 == 0)
return getCell(R1, Inputs, Result);
@@ -1499,8 +1492,10 @@ bool MachineConstEvaluator::evaluateORii(const APInt &A1,
return true;
}
-bool MachineConstEvaluator::evaluateXORrr(const RegisterSubReg &R1,
- const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateXORrr(const RegSubRegPair &R1,
+ const RegSubRegPair &R2,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
LatticeCell LS1, LS2;
if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2))
@@ -1528,8 +1523,10 @@ bool MachineConstEvaluator::evaluateXORrr(const RegisterSubReg &R1,
return !Result.isBottom();
}
-bool MachineConstEvaluator::evaluateXORri(const RegisterSubReg &R1,
- const APInt &A2, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateXORri(const RegSubRegPair &R1,
+ const APInt &A2,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS1;
if (!getCell(R1, Inputs, LS1))
@@ -1561,8 +1558,10 @@ bool MachineConstEvaluator::evaluateXORii(const APInt &A1,
return true;
}
-bool MachineConstEvaluator::evaluateZEXTr(const RegisterSubReg &R1, unsigned Width,
- unsigned Bits, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateZEXTr(const RegSubRegPair &R1,
+ unsigned Width, unsigned Bits,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS1;
if (!getCell(R1, Inputs, LS1))
@@ -1592,8 +1591,10 @@ bool MachineConstEvaluator::evaluateZEXTi(const APInt &A1, unsigned Width,
return true;
}
-bool MachineConstEvaluator::evaluateSEXTr(const RegisterSubReg &R1, unsigned Width,
- unsigned Bits, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateSEXTr(const RegSubRegPair &R1,
+ unsigned Width, unsigned Bits,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS1;
if (!getCell(R1, Inputs, LS1))
@@ -1657,8 +1658,9 @@ bool MachineConstEvaluator::evaluateSEXTi(const APInt &A1, unsigned Width,
return true;
}
-bool MachineConstEvaluator::evaluateCLBr(const RegisterSubReg &R1, bool Zeros,
- bool Ones, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateCLBr(const RegSubRegPair &R1, bool Zeros,
+ bool Ones, const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS1;
if (!getCell(R1, Inputs, LS1))
@@ -1692,8 +1694,9 @@ bool MachineConstEvaluator::evaluateCLBi(const APInt &A1, bool Zeros,
return true;
}
-bool MachineConstEvaluator::evaluateCTBr(const RegisterSubReg &R1, bool Zeros,
- bool Ones, const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateCTBr(const RegSubRegPair &R1, bool Zeros,
+ bool Ones, const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS1;
if (!getCell(R1, Inputs, LS1))
@@ -1727,9 +1730,11 @@ bool MachineConstEvaluator::evaluateCTBi(const APInt &A1, bool Zeros,
return true;
}
-bool MachineConstEvaluator::evaluateEXTRACTr(const RegisterSubReg &R1,
- unsigned Width, unsigned Bits, unsigned Offset, bool Signed,
- const CellMap &Inputs, LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateEXTRACTr(const RegSubRegPair &R1,
+ unsigned Width, unsigned Bits,
+ unsigned Offset, bool Signed,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
assert(Bits+Offset <= Width);
LatticeCell LS1;
@@ -1785,9 +1790,10 @@ bool MachineConstEvaluator::evaluateEXTRACTi(const APInt &A1, unsigned Bits,
return true;
}
-bool MachineConstEvaluator::evaluateSplatr(const RegisterSubReg &R1,
- unsigned Bits, unsigned Count, const CellMap &Inputs,
- LatticeCell &Result) {
+bool MachineConstEvaluator::evaluateSplatr(const RegSubRegPair &R1,
+ unsigned Bits, unsigned Count,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS1;
if (!getCell(R1, Inputs, LS1))
@@ -1835,8 +1841,8 @@ namespace {
bool evaluate(const MachineInstr &MI, const CellMap &Inputs,
CellMap &Outputs) override;
- bool evaluate(const RegisterSubReg &R, const LatticeCell &SrcC,
- LatticeCell &Result) override;
+ bool evaluate(const RegSubRegPair &R, const LatticeCell &SrcC,
+ LatticeCell &Result) override;
bool evaluate(const MachineInstr &BrI, const CellMap &Inputs,
SetVector<const MachineBasicBlock*> &Targets, bool &FallsThru)
override;
@@ -1850,8 +1856,8 @@ namespace {
const MachineOperand &MO);
void replaceWithNop(MachineInstr &MI);
- bool evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, const CellMap &Inputs,
- LatticeCell &Result);
+ bool evaluateHexRSEQ32(RegSubRegPair RL, RegSubRegPair RH,
+ const CellMap &Inputs, LatticeCell &Result);
bool evaluateHexCompare(const MachineInstr &MI, const CellMap &Inputs,
CellMap &Outputs);
// This is suitable to be called for compare-and-jump instructions.
@@ -1924,14 +1930,14 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
return false;
unsigned Opc = MI.getOpcode();
- RegisterSubReg DefR(MD);
+ RegSubRegPair DefR(getRegSubRegPair(MD));
assert(!DefR.SubReg);
if (!DefR.Reg.isVirtual())
return false;
if (MI.isCopy()) {
LatticeCell RC;
- RegisterSubReg SrcR(MI.getOperand(1));
+ RegSubRegPair SrcR(getRegSubRegPair(MI.getOperand(1)));
bool Eval = evaluateCOPY(SrcR, Inputs, RC);
if (!Eval)
return false;
@@ -1953,7 +1959,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
const MachineOperand &OpLo = LoIs1 ? MI.getOperand(1) : MI.getOperand(3);
const MachineOperand &OpHi = LoIs1 ? MI.getOperand(3) : MI.getOperand(1);
LatticeCell RC;
- RegisterSubReg SrcRL(OpLo), SrcRH(OpHi);
+ RegSubRegPair SrcRL(getRegSubRegPair(OpLo)), SrcRH(getRegSubRegPair(OpHi));
bool Eval = evaluateHexRSEQ32(SrcRL, SrcRH, Inputs, RC);
if (!Eval)
return false;
@@ -2040,7 +2046,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
int64_t B = MI.getOperand(2).getImm();
assert(B >=0 && B < 32);
APInt A(32, (1ull << B), false);
- RegisterSubReg R(MI.getOperand(1));
+ RegSubRegPair R(getRegSubRegPair(MI.getOperand(1)));
LatticeCell RC = Outputs.get(DefR.Reg);
bool Eval = evaluateORri(R, A, Inputs, RC);
if (!Eval)
@@ -2080,7 +2086,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
using namespace Hexagon;
bool Ones = (Opc == S2_ct1) || (Opc == S2_ct1p);
- RegisterSubReg R1(MI.getOperand(1));
+ RegSubRegPair R1(getRegSubRegPair(MI.getOperand(1)));
assert(Inputs.has(R1.Reg));
LatticeCell T;
bool Eval = evaluateCTBr(R1, !Ones, Ones, Inputs, T);
@@ -2112,7 +2118,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
bool OnlyZeros = (Opc == S2_cl0) || (Opc == S2_cl0p);
bool OnlyOnes = (Opc == S2_cl1) || (Opc == S2_cl1p);
- RegisterSubReg R1(MI.getOperand(1));
+ RegSubRegPair R1(getRegSubRegPair(MI.getOperand(1)));
assert(Inputs.has(R1.Reg));
LatticeCell T;
bool Eval = evaluateCLBr(R1, !OnlyOnes, !OnlyZeros, Inputs, T);
@@ -2140,7 +2146,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
{
bool Signed = (Opc == Hexagon::S4_extract) ||
(Opc == Hexagon::S4_extractp);
- RegisterSubReg R1(MI.getOperand(1));
+ RegSubRegPair R1(getRegSubRegPair(MI.getOperand(1)));
unsigned BW = getRegBitWidth(R1.Reg);
unsigned Bits = MI.getOperand(2).getImm();
unsigned Offset = MI.getOperand(3).getImm();
@@ -2191,8 +2197,9 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
return true;
}
-bool HexagonConstEvaluator::evaluate(const RegisterSubReg &R,
- const LatticeCell &Input, LatticeCell &Result) {
+bool HexagonConstEvaluator::evaluate(const RegSubRegPair &R,
+ const LatticeCell &Input,
+ LatticeCell &Result) {
if (!R.SubReg) {
Result = Input;
return true;
@@ -2282,7 +2289,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &BrI,
if (SimpleBranch) {
const MachineOperand &MD = BrI.getOperand(0);
- RegisterSubReg PR(MD);
+ RegSubRegPair PR(getRegSubRegPair(MD));
// If the condition operand has a subregister, this is not something
// we currently recognize.
if (PR.SubReg)
@@ -2505,8 +2512,10 @@ void HexagonConstEvaluator::replaceWithNop(MachineInstr &MI) {
MI.removeOperand(0);
}
-bool HexagonConstEvaluator::evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH,
- const CellMap &Inputs, LatticeCell &Result) {
+bool HexagonConstEvaluator::evaluateHexRSEQ32(RegSubRegPair RL,
+ RegSubRegPair RH,
+ const CellMap &Inputs,
+ LatticeCell &Result) {
assert(Inputs.has(RL.Reg) && Inputs.has(RH.Reg));
LatticeCell LSL, LSH;
if (!getCell(RL, Inputs, LSL) || !getCell(RH, Inputs, LSH))
@@ -2574,7 +2583,7 @@ bool HexagonConstEvaluator::evaluateHexCompare(const MachineInstr &MI,
if (Computed) {
// Only create a zero/non-zero cell. At this time there isn't really
// much need for specific values.
- RegisterSubReg DefR(MI.getOperand(0));
+ RegSubRegPair DefR(getRegSubRegPair(MI.getOperand(0)));
LatticeCell L = Outputs.get(DefR.Reg);
uint32_t P = Result ? ConstantProperties::NonZero
: ConstantProperties::Zero;
@@ -2594,9 +2603,9 @@ bool HexagonConstEvaluator::evaluateHexCompare2(unsigned Opc,
bool Reg1 = Src1.isReg(), Reg2 = Src2.isReg();
bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm();
if (Reg1) {
- RegisterSubReg R1(Src1);
+ RegSubRegPair R1(getRegSubRegPair(Src1));
if (Reg2) {
- RegisterSubReg R2(Src2);
+ RegSubRegPair R2(getRegSubRegPair(Src2));
return evaluateCMPrr(Cmp, R1, R2, Inputs, Result);
} else if (Imm2) {
APInt A2 = getCmpImm(Opc, 2, Src2);
@@ -2605,7 +2614,7 @@ bool HexagonConstEvaluator::evaluateHexCompare2(unsigned Opc,
} else if (Imm1) {
APInt A1 = getCmpImm(Opc, 1, Src1);
if (Reg2) {
- RegisterSubReg R2(Src2);
+ RegSubRegPair R2(getRegSubRegPair(Src2));
uint32_t NegCmp = Comparison::negate(Cmp);
return evaluateCMPri(NegCmp, R2, A1, Inputs, Result);
} else if (Imm2) {
@@ -2624,7 +2633,7 @@ bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI,
return false;
const MachineOperand &Src1 = MI.getOperand(1);
const MachineOperand &Src2 = MI.getOperand(2);
- RegisterSubReg R1(Src1);
+ RegSubRegPair R1(getRegSubRegPair(Src1));
bool Eval = false;
LatticeCell RC;
switch (Opc) {
@@ -2632,7 +2641,8 @@ bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI,
return false;
case Hexagon::A2_and:
case Hexagon::A2_andp:
- Eval = evaluateANDrr(R1, RegisterSubReg(Src2), Inputs, RC);
+ Eval =
+ evaluateANDrr(R1, RegSubRegPair(getRegSubRegPair(Src2)), Inputs, RC);
break;
case Hexagon::A2_andir: {
if (!Src2.isImm())
@@ -2643,7 +2653,8 @@ bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI,
}
case Hexagon::A2_or:
case Hexagon::A2_orp:
- Eval = evaluateORrr(R1, RegisterSubReg(Src2), Inputs, RC);
+ Eval =
+ evaluateORrr(R1, RegSubRegPair(getRegSubRegPair(Src2)), Inputs, RC);
break;
case Hexagon::A2_orir: {
if (!Src2.isImm())
@@ -2654,11 +2665,12 @@ bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI,
}
case Hexagon::A2_xor:
case Hexagon::A2_xorp:
- Eval = evaluateXORrr(R1, RegisterSubReg(Src2), Inputs, RC);
+ Eval =
+ evaluateXORrr(R1, RegSubRegPair(getRegSubRegPair(Src2)), Inputs, RC);
break;
}
if (Eval) {
- RegisterSubReg DefR(MI.getOperand(0));
+ RegSubRegPair DefR(getRegSubRegPair(MI.getOperand(0)));
Outputs.update(DefR.Reg, RC);
}
return Eval;
@@ -2667,7 +2679,7 @@ bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI,
bool HexagonConstEvaluator::evaluateHexCondMove(const MachineInstr &MI,
const CellMap &Inputs, CellMap &Outputs) {
// Dst0 = Cond1 ? Src2 : Src3
- RegisterSubReg CR(MI.getOperand(1));
+ RegSubRegPair CR(getRegSubRegPair(MI.getOperand(1)));
assert(Inputs.has(CR.Reg));
LatticeCell LS;
if (!getCell(CR, Inputs, LS))
@@ -2682,7 +2694,7 @@ bool HexagonConstEvaluator::evaluateHexCondMove(const MachineInstr &MI,
return false;
const MachineOperand &ValOp = MI.getOperand(TakeOp);
- RegisterSubReg DefR(MI.getOperand(0));
+ RegSubRegPair DefR(getRegSubRegPair(MI.getOperand(0)));
LatticeCell RC = Outputs.get(DefR.Reg);
if (ValOp.isImm()) {
@@ -2695,7 +2707,7 @@ bool HexagonConstEvaluator::evaluateHexCondMove(const MachineInstr &MI,
return true;
}
if (ValOp.isReg()) {
- RegisterSubReg R(ValOp);
+ RegSubRegPair R(getRegSubRegPair(ValOp));
const LatticeCell &LR = Inputs.get(R.Reg);
LatticeCell LSR;
if (!evaluate(R, LR, LSR))
@@ -2710,7 +2722,7 @@ bool HexagonConstEvaluator::evaluateHexCondMove(const MachineInstr &MI,
bool HexagonConstEvaluator::evaluateHexExt(const MachineInstr &MI,
const CellMap &Inputs, CellMap &Outputs) {
// Dst0 = ext R1
- RegisterSubReg R1(MI.getOperand(1));
+ RegSubRegPair R1(getRegSubRegPair(MI.getOperand(1)));
assert(Inputs.has(R1.Reg));
unsigned Opc = MI.getOpcode();
@@ -2740,7 +2752,7 @@ bool HexagonConstEvaluator::evaluateHexExt(const MachineInstr &MI,
break;
}
- RegisterSubReg DefR(MI.getOperand(0));
+ RegSubRegPair DefR(getRegSubRegPair(MI.getOperand(0)));
unsigned BW = getRegBitWidth(DefR.Reg);
LatticeCell RC = Outputs.get(DefR.Reg);
bool Eval = Signed ? evaluateSEXTr(R1, BW, Bits, Inputs, RC)
@@ -2754,8 +2766,8 @@ bool HexagonConstEvaluator::evaluateHexExt(const MachineInstr &MI,
bool HexagonConstEvaluator::evaluateHexVector1(const MachineInstr &MI,
const CellMap &Inputs, CellMap &Outputs) {
// DefR = op R1
- RegisterSubReg DefR(MI.getOperand(0));
- RegisterSubReg R1(MI.getOperand(1));
+ RegSubRegPair DefR(getRegSubRegPair(MI.getOperand(0)));
+ RegSubRegPair R1(getRegSubRegPair(MI.getOperand(1)));
assert(Inputs.has(R1.Reg));
LatticeCell RC = Outputs.get(DefR.Reg);
bool Eval;
@@ -2793,7 +2805,7 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI,
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.isUse() || MO.isImplicit())
continue;
- RegisterSubReg R(MO);
+ RegSubRegPair R(getRegSubRegPair(MO));
if (!R.Reg.isVirtual())
continue;
HasUse = true;
@@ -2963,10 +2975,10 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI,
// to DefR += mpyi(R, #imm),
// or DefR -= mpyi(R, #imm).
{
- RegisterSubReg DefR(MI.getOperand(0));
+ RegSubRegPair DefR(getRegSubRegPair(MI.getOperand(0)));
assert(!DefR.SubReg);
- RegisterSubReg R2(MI.getOperand(2));
- RegisterSubReg R3(MI.getOperand(3));
+ RegSubRegPair R2(getRegSubRegPair(MI.getOperand(2)));
+ RegSubRegPair R3(getRegSubRegPair(MI.getOperand(3)));
assert(Inputs.has(R2.Reg) && Inputs.has(R3.Reg));
LatticeCell LS2, LS3;
// It is enough to get one of the input cells, since we will only try
@@ -2980,7 +2992,7 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI,
if (Zero) {
// DefR == R1 (tied operands).
MachineOperand &Acc = MI.getOperand(1);
- RegisterSubReg R1(Acc);
+ RegSubRegPair R1(getRegSubRegPair(Acc));
unsigned NewR = R1.Reg;
if (R1.SubReg) {
// Generate COPY. FIXME: Replace with the register:subregister.
@@ -3027,8 +3039,8 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI,
case Hexagon::A2_and:
{
- RegisterSubReg R1(MI.getOperand(1));
- RegisterSubReg R2(MI.getOperand(2));
+ RegSubRegPair R1(getRegSubRegPair(MI.getOperand(1)));
+ RegSubRegPair R2(getRegSubRegPair(MI.getOperand(2)));
assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
LatticeCell LS1, LS2;
unsigned CopyOf = 0;
@@ -3046,8 +3058,8 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI,
if (!CopyOf)
return false;
MachineOperand &SO = MI.getOperand(CopyOf);
- RegisterSubReg SR(SO);
- RegisterSubReg DefR(MI.getOperand(0));
+ RegSubRegPair SR(getRegSubRegPair(SO));
+ RegSubRegPair DefR(getRegSubRegPair(MI.getOperand(0)));
unsigned NewR = SR.Reg;
if (SR.SubReg) {
const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
@@ -3063,8 +3075,8 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI,
case Hexagon::A2_or:
{
- RegisterSubReg R1(MI.getOperand(1));
- RegisterSubReg R2(MI.getOperand(2));
+ RegSubRegPair R1(getRegSubRegPair(MI.getOperand(1)));
+ RegSubRegPair R2(getRegSubRegPair(MI.getOperand(2)));
assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
LatticeCell LS1, LS2;
unsigned CopyOf = 0;
@@ -3078,8 +3090,8 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI,
if (!CopyOf)
return false;
MachineOperand &SO = MI.getOperand(CopyOf);
- RegisterSubReg SR(SO);
- RegisterSubReg DefR(MI.getOperand(0));
+ RegSubRegPair SR(getRegSubRegPair(SO));
+ RegSubRegPair DefR(getRegSubRegPair(MI.getOperand(0)));
unsigned NewR = SR.Reg;
if (SR.SubReg) {
const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
index cbe644e24bd36..d037de173764a 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
@@ -40,38 +40,23 @@ using namespace llvm;
namespace {
- // FIXME: Use TargetInstrInfo::RegSubRegPair
- struct RegisterSubReg {
- Register R;
- unsigned S;
-
- RegisterSubReg(unsigned r = 0, unsigned s = 0) : R(r), S(s) {}
- RegisterSubReg(const MachineOperand &MO) : R(MO.getReg()), S(MO.getSubReg()) {}
- RegisterSubReg(const Register &Reg) : R(Reg), S(0) {}
-
- bool operator== (const RegisterSubReg &Reg) const {
- return R == Reg.R && S == Reg.S;
- }
-
- bool operator< (const RegisterSubReg &Reg) const {
- return R < Reg.R || (R == Reg.R && S < Reg.S);
- }
- };
-
struct PrintRegister {
- friend raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR);
+ friend raw_ostream &operator<<(raw_ostream &OS, const PrintRegister &PR);
- PrintRegister(RegisterSubReg R, const TargetRegisterInfo &I) : Reg(R), TRI(I) {}
+ PrintRegister(RegSubRegPair R, const TargetRegisterInfo &I)
+ : Reg(R), TRI(I) {}
private:
- RegisterSubReg Reg;
+ RegSubRegPair Reg;
const TargetRegisterInfo &TRI;
};
+ using RegSubRegPair = TargetInstrInfo::RegSubRegPair;
+
raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR)
LLVM_ATTRIBUTE_UNUSED;
raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) {
- return OS << printReg(PR.Reg.R, &PR.TRI, PR.Reg.S);
+ return OS << printReg(PR.Reg.Reg, &PR.TRI, PR.Reg.SubReg);
}
class HexagonGenPredicate : public MachineFunctionPass {
@@ -94,8 +79,8 @@ namespace {
private:
using VectOfInst = SetVector<MachineInstr *>;
- using SetOfReg = std::set<RegisterSubReg>;
- using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>;
+ using SetOfReg = SetVector<RegSubRegPair>;
+ using RegToRegMap = DenseMap<RegSubRegPair, RegSubRegPair>;
const HexagonInstrInfo *TII = nullptr;
const HexagonRegisterInfo *TRI = nullptr;
@@ -106,12 +91,12 @@ namespace {
bool isPredReg(Register R);
void collectPredicateGPR(MachineFunction &MF);
- void processPredicateGPR(const RegisterSubReg &Reg);
+ void processPredicateGPR(const RegSubRegPair &Reg);
unsigned getPredForm(unsigned Opc);
bool isConvertibleToPredForm(const MachineInstr *MI);
bool isScalarCmp(unsigned Opc);
- bool isScalarPred(RegisterSubReg PredReg);
- RegisterSubReg getPredRegFor(const RegisterSubReg &Reg);
+ bool isScalarPred(RegSubRegPair PredReg);
+ RegSubRegPair getPredRegFor(const RegSubRegPair &Reg);
bool convertToPredForm(MachineInstr *MI);
bool eliminatePredCopies(MachineFunction &MF);
};
@@ -204,8 +189,8 @@ void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) {
case Hexagon::C2_tfrpr:
case TargetOpcode::COPY:
if (isPredReg(MI.getOperand(1).getReg())) {
- RegisterSubReg RD = MI.getOperand(0);
- if (RD.R.isVirtual())
+ RegSubRegPair RD = getRegSubRegPair(MI.getOperand(0));
+ if (RD.Reg.isVirtual())
PredGPRs.insert(RD);
}
break;
@@ -214,14 +199,16 @@ void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) {
}
}
-void HexagonGenPredicate::processPredicateGPR(const RegisterSubReg &Reg) {
- LLVM_DEBUG(dbgs() << __func__ << ": " << printReg(Reg.R, TRI, Reg.S) << "\n");
+void HexagonGenPredicate::processPredicateGPR(const RegSubRegPair &Reg) {
+ LLVM_DEBUG(dbgs() << __func__ << ": " << printReg(Reg.Reg, TRI, Reg.SubReg)
+ << "\n");
using use_iterator = MachineRegisterInfo::use_iterator;
- use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end();
+ use_iterator I = MRI->use_begin(Reg.Reg), E = MRI->use_end();
if (I == E) {
- LLVM_DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n');
- MachineInstr *DefI = MRI->getVRegDef(Reg.R);
+ LLVM_DEBUG(dbgs() << "Dead reg: " << printReg(Reg.Reg, TRI, Reg.SubReg)
+ << '\n');
+ MachineInstr *DefI = MRI->getVRegDef(Reg.Reg);
DefI->eraseFromParent();
return;
}
@@ -233,22 +220,22 @@ void HexagonGenPredicate::processPredicateGPR(const RegisterSubReg &Reg) {
}
}
-RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) {
+RegSubRegPair HexagonGenPredicate::getPredRegFor(const RegSubRegPair &Reg) {
// Create a predicate register for a given Reg. The newly created register
// will have its value copied from Reg, so that it can be later used as
// an operand in other instructions.
- assert(Reg.R.isVirtual());
+ assert(Reg.Reg.isVirtual());
RegToRegMap::iterator F = G2P.find(Reg);
if (F != G2P.end())
return F->second;
LLVM_DEBUG(dbgs() << __func__ << ": " << PrintRegister(Reg, *TRI));
- MachineInstr *DefI = MRI->getVRegDef(Reg.R);
+ MachineInstr *DefI = MRI->getVRegDef(Reg.Reg);
assert(DefI);
unsigned Opc = DefI->getOpcode();
if (Opc == Hexagon::C2_tfrpr || Opc == TargetOpcode::COPY) {
assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse());
- RegisterSubReg PR = DefI->getOperand(1);
+ RegSubRegPair PR = getRegSubRegPair(DefI->getOperand(1));
G2P.insert(std::make_pair(Reg, PR));
LLVM_DEBUG(dbgs() << " -> " << PrintRegister(PR, *TRI) << '\n');
return PR;
@@ -264,11 +251,11 @@ RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) {
if (isConvertibleToPredForm(DefI)) {
MachineBasicBlock::iterator DefIt = DefI;
BuildMI(B, std::next(DefIt), DL, TII->get(TargetOpcode::COPY), NewPR)
- .addReg(Reg.R, 0, Reg.S);
- G2P.insert(std::make_pair(Reg, RegisterSubReg(NewPR)));
- LLVM_DEBUG(dbgs() << " -> !" << PrintRegister(RegisterSubReg(NewPR), *TRI)
+ .addReg(Reg.Reg, 0, Reg.SubReg);
+ G2P.insert(std::make_pair(Reg, RegSubRegPair(NewPR)));
+ LLVM_DEBUG(dbgs() << " -> !" << PrintRegister(RegSubRegPair(NewPR), *TRI)
<< '\n');
- return RegisterSubReg(NewPR);
+ return RegSubRegPair(NewPR);
}
llvm_unreachable("Invalid argument");
@@ -310,21 +297,21 @@ bool HexagonGenPredicate::isScalarCmp(unsigned Opc) {
return false;
}
-bool HexagonGenPredicate::isScalarPred(RegisterSubReg PredReg) {
- std::queue<RegisterSubReg> WorkQ;
+bool HexagonGenPredicate::isScalarPred(RegSubRegPair PredReg) {
+ std::queue<RegSubRegPair> WorkQ;
WorkQ.push(PredReg);
while (!WorkQ.empty()) {
- RegisterSubReg PR = WorkQ.front();
+ RegSubRegPair PR = WorkQ.front();
WorkQ.pop();
- const MachineInstr *DefI = MRI->getVRegDef(PR.R);
+ const MachineInstr *DefI = MRI->getVRegDef(PR.Reg);
if (!DefI)
return false;
unsigned DefOpc = DefI->getOpcode();
switch (DefOpc) {
case TargetOpcode::COPY: {
const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
- if (MRI->getRegClass(PR.R) != PredRC)
+ if (MRI->getRegClass(PR.Reg) != PredRC)
return false;
// If it is a copy between two predicate registers, fall through.
[[fallthrough]];
@@ -344,7 +331,7 @@ bool HexagonGenPredicate::isScalarPred(RegisterSubReg PredReg) {
// Add operands to the queue.
for (const MachineOperand &MO : DefI->operands())
if (MO.isReg() && MO.isUse())
- WorkQ.push(RegisterSubReg(MO.getReg()));
+ WorkQ.push(RegSubRegPair(MO.getReg()));
break;
// All non-vector compares are ok, everything else is bad.
@@ -366,8 +353,8 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) {
MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isUse())
continue;
- RegisterSubReg Reg(MO);
- if (Reg.S && Reg.S != Hexagon::isub_lo)
+ RegSubRegPair Reg(getRegSubRegPair(MO));
+ if (Reg.SubReg && Reg.SubReg != Hexagon::isub_lo)
return false;
if (!PredGPRs.count(Reg))
return false;
@@ -393,7 +380,7 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) {
// If it's a scalar predicate register, then all bits in it are
// the same. Otherwise, to determine whether all bits are 0 or not
// we would need to use any8.
- RegisterSubReg PR = getPredRegFor(MI->getOperand(1));
+ RegSubRegPair PR = getPredRegFor(getRegSubRegPair(MI->getOperand(1)));
if (!isScalarPred(PR))
return false;
// This will skip the immediate argument when creating the predicate
@@ -404,37 +391,37 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) {
// Check that def is in operand #0.
MachineOperand &Op0 = MI->getOperand(0);
assert(Op0.isDef());
- RegisterSubReg OutR(Op0);
+ RegSubRegPair OutR(getRegSubRegPair(Op0));
// Don't use getPredRegFor, since it will create an association between
// the argument and a created predicate register (i.e. it will insert a
// copy if a new predicate register is created).
const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
- RegisterSubReg NewPR = MRI->createVirtualRegister(PredRC);
- MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R);
+ RegSubRegPair NewPR = MRI->createVirtualRegister(PredRC);
+ MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.Reg);
// Add predicate counterparts of the GPRs.
for (unsigned i = 1; i < NumOps; ++i) {
- RegisterSubReg GPR = MI->getOperand(i);
- RegisterSubReg Pred = getPredRegFor(GPR);
- MIB.addReg(Pred.R, 0, Pred.S);
+ RegSubRegPair GPR = getRegSubRegPair(MI->getOperand(i));
+ RegSubRegPair Pred = getPredRegFor(GPR);
+ MIB.addReg(Pred.Reg, 0, Pred.SubReg);
}
LLVM_DEBUG(dbgs() << "generated: " << *MIB);
// Generate a copy-out: NewGPR = NewPR, and replace all uses of OutR
// with NewGPR.
- const TargetRegisterClass *RC = MRI->getRegClass(OutR.R);
+ const TargetRegisterClass *RC = MRI->getRegClass(OutR.Reg);
Register NewOutR = MRI->createVirtualRegister(RC);
BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), NewOutR)
- .addReg(NewPR.R, 0, NewPR.S);
- MRI->replaceRegWith(OutR.R, NewOutR);
+ .addReg(NewPR.Reg, 0, NewPR.SubReg);
+ MRI->replaceRegWith(OutR.Reg, NewOutR);
MI->eraseFromParent();
// If the processed instruction was C2_tfrrp (i.e. Rn = Pm; Pk = Rn),
// then the output will be a predicate register. Do not visit the
// users of it.
if (!isPredReg(NewOutR)) {
- RegisterSubReg R(NewOutR);
+ RegSubRegPair R(NewOutR);
PredGPRs.insert(R);
processPredicateGPR(R);
}
@@ -461,18 +448,18 @@ bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) {
for (MachineInstr &MI : MBB) {
if (MI.getOpcode() != TargetOpcode::COPY)
continue;
- RegisterSubReg DR = MI.getOperand(0);
- RegisterSubReg SR = MI.getOperand(1);
- if (!DR.R.isVirtual())
+ RegSubRegPair DR = getRegSubRegPair(MI.getOperand(0));
+ RegSubRegPair SR = getRegSubRegPair(MI.getOperand(1));
+ if (!DR.Reg.isVirtual())
continue;
- if (!SR.R.isVirtual())
+ if (!SR.Reg.isVirtual())
continue;
- if (MRI->getRegClass(DR.R) != PredRC)
+ if (MRI->getRegClass(DR.Reg) != PredRC)
continue;
- if (MRI->getRegClass(SR.R) != PredRC)
+ if (MRI->getRegClass(SR.Reg) != PredRC)
continue;
- assert(!DR.S && !SR.S && "Unexpected subregister");
- MRI->replaceRegWith(DR.R, SR.R);
+ assert(!DR.SubReg && !SR.SubReg && "Unexpected subregister");
+ MRI->replaceRegWith(DR.Reg, SR.Reg);
Erase.insert(&MI);
Changed = true;
}
@@ -497,7 +484,7 @@ bool HexagonGenPredicate::runOnMachineFunction(MachineFunction &MF) {
bool Changed = false;
collectPredicateGPR(MF);
- for (const RegisterSubReg &R : PredGPRs)
+ for (const RegSubRegPair &R : PredGPRs)
processPredicateGPR(R);
bool Again;
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
index b8f345581b7ac..086cb1fdd8ac4 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -534,6 +534,13 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
MCInst getNop() const override;
};
+/// \brief Create RegSubRegPair from a register MachineOperand
+inline TargetInstrInfo::RegSubRegPair
+getRegSubRegPair(const MachineOperand &O) {
+ assert(O.isReg());
+ return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
+}
+
} // end namespace llvm
#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
>From a5230b3eec7dc2fb4404a3394b8fa47d0f901df0 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: Tue, 6 May 2025 14:57:01 +0530
Subject: [PATCH 2/2] Move code
---
.../lib/Target/Hexagon/HexagonGenPredicate.cpp | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
index d037de173764a..e0ed9174daa93 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
@@ -40,18 +40,18 @@ using namespace llvm;
namespace {
- struct PrintRegister {
- friend raw_ostream &operator<<(raw_ostream &OS, const PrintRegister &PR);
+using RegSubRegPair = TargetInstrInfo::RegSubRegPair;
- PrintRegister(RegSubRegPair R, const TargetRegisterInfo &I)
- : Reg(R), TRI(I) {}
+struct PrintRegister {
+ friend raw_ostream &operator<<(raw_ostream &OS, const PrintRegister &PR);
- private:
- RegSubRegPair Reg;
- const TargetRegisterInfo &TRI;
- };
+ PrintRegister(RegSubRegPair R, const TargetRegisterInfo &I)
+ : Reg(R), TRI(I) {}
- using RegSubRegPair = TargetInstrInfo::RegSubRegPair;
+private:
+ RegSubRegPair Reg;
+ const TargetRegisterInfo &TRI;
+};
raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR)
LLVM_ATTRIBUTE_UNUSED;
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