[llvm] [CodeGen] For ad hoc aliasing, additional regUnits are needed to fix lanemask representation (PR #139206)

[Vikash Gupta via llvm-commits]

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@@ -424,20 +424,33 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
   // These units correspond to the maximal cliques in the register overlap
   // graph which is optimal.
   //
-  // When there is ad hoc aliasing, we simply create one unit per edge in the
-  // undirected ad hoc aliasing graph. Technically, we could do better by
-  // identifying maximal cliques in the ad hoc graph, but cliques larger than 2
-  // are extremely rare anyway (I've never seen one), so we don't bother with
-  // the added complexity.
+  // When there is ad hoc aliasing, while we create one unit per edge in the
+  // undirected ad hoc aliasing graph to represent aliasing, one unit per each
+  // node leaf register is needed extra to identify them uniquely, in case these
+  // aliasing register are used as subregister(with disjoint lanemasks) to have
+  // an accurate lanemask generation for these leaf register.
+  // For example, In VE, SX0 is made out of disjoint subregister SW0 & SF0
+  // respectively, where SF0 is an alias for SW0. So while 2 register units will
+  // uniquely define these 2 subregister, the shared register unit will account
+  // for aliasing.
+  //
+  // Technically, we could do better by identifying maximal cliques in the ad
+  // hoc graph, but cliques larger than 2 are extremely rare anyway (I've never
+  // seen one), so we don't bother with the added complexity.
   for (CodeGenRegister *AR : ExplicitAliases) {
     // Only visit each edge once.
     if (AR->SubRegsComplete)
       continue;
     // Create a RegUnit representing this alias edge, and add it to both
     // registers.
-    unsigned Unit = RegBank.newRegUnit(this, AR);
-    RegUnits.set(Unit);
-    AR->RegUnits.set(Unit);
+    unsigned SharedUnit = RegBank.newRegUnit(this, AR);
+    RegUnits.set(SharedUnit);
+    AR->RegUnits.set(SharedUnit);
+
+    // Create a RegUnit that now corresponds uniquely to each of the both
+    // alias leaf register nodes.
----------------
vg0204 wrote:

> This is assuming that a register that has aliases is also a leaf, i.e. it has no sburegs. I am not sure whether that is a valid assumption.

It should not have subregs, as the register units are created corresponding only to leaf registers, while other regs inherit the regunits of their corresponding subregs. If you see few lines above this changes you would observe.

https://github.com/llvm/llvm-project/pull/139206